sanchayanmaity/gem5
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity
gem5/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt

568 lines
65 KiB
Text
Raw Normal View History

X86: Add stats for the new x86 fs regressions.
2011-02-07 10:23:16 +01:00
---------- Begin Simulation Statistics ----------
Stats: Update stats for cache timings in cycles This patch updates the stats to reflect the change in how cache latencies are expressed. In addition, the latencies are now rounded to multiples of the clock period, thus also affecting other stats.
2012-10-15 14:12:21 +02:00
sim_seconds 5.112041 # Number of seconds simulated
x86 regressions: updates due to new instructions and cpuid
2013-01-15 14:43:23 +01:00
sim_ticks 5112040970500 # Number of ticks simulated
final_tick 5112040970500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
X86: Add stats for the new x86 fs regressions.
2011-02-07 10:23:16 +01:00
sim_freq 1000000000000 # Frequency of simulated ticks
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
host_inst_rate 1074050 # Simulator instruction rate (inst/s)
host_op_rate 2199194 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 27479001055 # Simulator tick rate (ticks/s)
host_mem_usage 583620 # Number of bytes of host memory used
host_seconds 186.03 # Real time elapsed on the host
x86 regressions: updates due to new instructions and cpuid
2013-01-15 14:43:23 +01:00
sim_insts 199810242 # Number of instructions simulated
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
sim_ops 409125913 # Number of ops (including micro ops) simulated
Stats: Update stats for cache timings in cycles This patch updates the stats to reflect the change in how cache latencies are expressed. In addition, the latencies are now rounded to multiples of the clock period, thus also affecting other stats.
2012-10-15 14:12:21 +02:00
system.physmem.bytes_read::pc.south_bridge.ide 2464640 # Number of bytes read from this memory
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.physmem.bytes_read::cpu.dtb.walker 128 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.inst 853824 # Number of bytes read from this memory
Stats: Update stats for cache timings in cycles This patch updates the stats to reflect the change in how cache latencies are expressed. In addition, the latencies are now rounded to multiples of the clock period, thus also affecting other stats.
2012-10-15 14:12:21 +02:00
system.physmem.bytes_read::cpu.data 10600128 # Number of bytes read from this memory
system.physmem.bytes_read::total 13919040 # Number of bytes read from this memory
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.physmem.bytes_inst_read::cpu.inst 853824 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 853824 # Number of instructions bytes read from this memory
Stats: Update stats for cache timings in cycles This patch updates the stats to reflect the change in how cache latencies are expressed. In addition, the latencies are now rounded to multiples of the clock period, thus also affecting other stats.
2012-10-15 14:12:21 +02:00
system.physmem.bytes_written::writebacks 9292608 # Number of bytes written to this memory
system.physmem.bytes_written::total 9292608 # Number of bytes written to this memory
system.physmem.num_reads::pc.south_bridge.ide 38510 # Number of read requests responded to by this memory
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.physmem.num_reads::cpu.dtb.walker 2 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.itb.walker 5 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.inst 13341 # Number of read requests responded to by this memory
Stats: Update stats for cache timings in cycles This patch updates the stats to reflect the change in how cache latencies are expressed. In addition, the latencies are now rounded to multiples of the clock period, thus also affecting other stats.
2012-10-15 14:12:21 +02:00
system.physmem.num_reads::cpu.data 165627 # Number of read requests responded to by this memory
system.physmem.num_reads::total 217485 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 145197 # Number of write requests responded to by this memory
system.physmem.num_writes::total 145197 # Number of write requests responded to by this memory
system.physmem.bw_read::pc.south_bridge.ide 482124 # Total read bandwidth from this memory (bytes/s)
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.physmem.bw_read::cpu.dtb.walker 25 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.itb.walker 63 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.inst 167022 # Total read bandwidth from this memory (bytes/s)
Stats: Update stats for cache timings in cycles This patch updates the stats to reflect the change in how cache latencies are expressed. In addition, the latencies are now rounded to multiples of the clock period, thus also affecting other stats.
2012-10-15 14:12:21 +02:00
system.physmem.bw_read::cpu.data 2073561 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 2722795 # Total read bandwidth from this memory (bytes/s)
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.physmem.bw_inst_read::cpu.inst 167022 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 167022 # Instruction read bandwidth from this memory (bytes/s)
Stats: Update stats for cache timings in cycles This patch updates the stats to reflect the change in how cache latencies are expressed. In addition, the latencies are now rounded to multiples of the clock period, thus also affecting other stats.
2012-10-15 14:12:21 +02:00
system.physmem.bw_write::writebacks 1817788 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 1817788 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 1817788 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::pc.south_bridge.ide 482124 # Total bandwidth to/from this memory (bytes/s)
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.physmem.bw_total::cpu.dtb.walker 25 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.itb.walker 63 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 167022 # Total bandwidth to/from this memory (bytes/s)
Stats: Update stats for cache timings in cycles This patch updates the stats to reflect the change in how cache latencies are expressed. In addition, the latencies are now rounded to multiples of the clock period, thus also affecting other stats.
2012-10-15 14:12:21 +02:00
system.physmem.bw_total::cpu.data 2073561 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 4540583 # Total bandwidth to/from this memory (bytes/s)
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.physmem.readReqs 0 # Total number of read requests seen
system.physmem.writeReqs 0 # Total number of write requests seen
system.physmem.cpureqs 0 # Reqs generatd by CPU via cache - shady
system.physmem.bytesRead 0 # Total number of bytes read from memory
system.physmem.bytesWritten 0 # Total number of bytes written to memory
system.physmem.bytesConsumedRd 0 # bytesRead derated as per pkt->getSize()
system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
system.physmem.perBankRdReqs::0 0 # Track reads on a per bank basis
system.physmem.perBankRdReqs::1 0 # Track reads on a per bank basis
system.physmem.perBankRdReqs::2 0 # Track reads on a per bank basis
system.physmem.perBankRdReqs::3 0 # Track reads on a per bank basis
system.physmem.perBankRdReqs::4 0 # Track reads on a per bank basis
system.physmem.perBankRdReqs::5 0 # Track reads on a per bank basis
system.physmem.perBankRdReqs::6 0 # Track reads on a per bank basis
system.physmem.perBankRdReqs::7 0 # Track reads on a per bank basis
system.physmem.perBankRdReqs::8 0 # Track reads on a per bank basis
system.physmem.perBankRdReqs::9 0 # Track reads on a per bank basis
system.physmem.perBankRdReqs::10 0 # Track reads on a per bank basis
system.physmem.perBankRdReqs::11 0 # Track reads on a per bank basis
system.physmem.perBankRdReqs::12 0 # Track reads on a per bank basis
system.physmem.perBankRdReqs::13 0 # Track reads on a per bank basis
system.physmem.perBankRdReqs::14 0 # Track reads on a per bank basis
system.physmem.perBankRdReqs::15 0 # Track reads on a per bank basis
system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
system.physmem.totGap 0 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 0 # Categorize read packet sizes
system.physmem.readPktSize::3 0 # Categorize read packet sizes
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
system.physmem.readPktSize::6 0 # Categorize read packet sizes
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.physmem.writePktSize::0 0 # Categorize write packet sizes
system.physmem.writePktSize::1 0 # Categorize write packet sizes
system.physmem.writePktSize::2 0 # Categorize write packet sizes
system.physmem.writePktSize::3 0 # Categorize write packet sizes
system.physmem.writePktSize::4 0 # Categorize write packet sizes
system.physmem.writePktSize::5 0 # Categorize write packet sizes
system.physmem.writePktSize::6 0 # Categorize write packet sizes
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.physmem.rdQLenPdf::0 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
system.physmem.totQLat 0 # Total cycles spent in queuing delays
system.physmem.totMemAccLat 0 # Sum of mem lat for all requests
system.physmem.totBusLat 0 # Total cycles spent in databus access
system.physmem.totBankLat 0 # Total cycles spent in bank access
system.physmem.avgQLat nan # Average queueing delay per request
system.physmem.avgBankLat nan # Average bank access latency per request
system.physmem.avgBusLat nan # Average bus latency per request
system.physmem.avgMemAccLat nan # Average memory access latency
system.physmem.avgRdBW 0.00 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW 0.00 # Average consumed read bandwidth in MB/s
system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.physmem.busUtil 0.00 # Data bus utilization in percentage
system.physmem.avgRdQLen 0.00 # Average read queue length over time
system.physmem.avgWrQLen 0.00 # Average write queue length over time
system.physmem.readRowHits 0 # Number of row buffer hits during reads
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
system.physmem.readRowHitRate nan # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
system.physmem.avgGap nan # Average gap between requests
Stats: Update stats for cache timings in cycles This patch updates the stats to reflect the change in how cache latencies are expressed. In addition, the latencies are now rounded to multiples of the clock period, thus also affecting other stats.
2012-10-15 14:12:21 +02:00
system.iocache.replacements 47569 # number of replacements
system.iocache.tagsinuse 0.042402 # Cycle average of tags in use
Tests: Update stats due to addition of fence microop
2011-11-05 21:32:23 +01:00
system.iocache.total_refs 0 # Total number of references to valid blocks.
Stats: Update stats for cache timings in cycles This patch updates the stats to reflect the change in how cache latencies are expressed. In addition, the latencies are now rounded to multiples of the clock period, thus also affecting other stats.
2012-10-15 14:12:21 +02:00
system.iocache.sampled_refs 47585 # Sample count of references to valid blocks.
X86: Add stats for the new x86 fs regressions.
2011-02-07 10:23:16 +01:00
system.iocache.avg_refs 0 # Average number of references to valid blocks.
x86 regressions: updates due to new instructions and cpuid
2013-01-15 14:43:23 +01:00
system.iocache.warmup_cycle 4994776682059 # Cycle when the warmup percentage was hit.
Stats: Update stats for cache timings in cycles This patch updates the stats to reflect the change in how cache latencies are expressed. In addition, the latencies are now rounded to multiples of the clock period, thus also affecting other stats.
2012-10-15 14:12:21 +02:00
system.iocache.occ_blocks::pc.south_bridge.ide 0.042402 # Average occupied blocks per requestor
system.iocache.occ_percent::pc.south_bridge.ide 0.002650 # Average percentage of cache occupancy
system.iocache.occ_percent::total 0.002650 # Average percentage of cache occupancy
system.iocache.ReadReq_misses::pc.south_bridge.ide 904 # number of ReadReq misses
system.iocache.ReadReq_misses::total 904 # number of ReadReq misses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.iocache.WriteReq_misses::pc.south_bridge.ide 46720 # number of WriteReq misses
Tests: Update stats due to addition of fence microop
2011-11-05 21:32:23 +01:00
system.iocache.WriteReq_misses::total 46720 # number of WriteReq misses
Stats: Update stats for cache timings in cycles This patch updates the stats to reflect the change in how cache latencies are expressed. In addition, the latencies are now rounded to multiples of the clock period, thus also affecting other stats.
2012-10-15 14:12:21 +02:00
system.iocache.demand_misses::pc.south_bridge.ide 47624 # number of demand (read+write) misses
system.iocache.demand_misses::total 47624 # number of demand (read+write) misses
system.iocache.overall_misses::pc.south_bridge.ide 47624 # number of overall misses
system.iocache.overall_misses::total 47624 # number of overall misses
system.iocache.ReadReq_accesses::pc.south_bridge.ide 904 # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total 904 # number of ReadReq accesses(hits+misses)
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.iocache.WriteReq_accesses::pc.south_bridge.ide 46720 # number of WriteReq accesses(hits+misses)
Tests: Update stats due to addition of fence microop
2011-11-05 21:32:23 +01:00
system.iocache.WriteReq_accesses::total 46720 # number of WriteReq accesses(hits+misses)
Stats: Update stats for cache timings in cycles This patch updates the stats to reflect the change in how cache latencies are expressed. In addition, the latencies are now rounded to multiples of the clock period, thus also affecting other stats.
2012-10-15 14:12:21 +02:00
system.iocache.demand_accesses::pc.south_bridge.ide 47624 # number of demand (read+write) accesses
system.iocache.demand_accesses::total 47624 # number of demand (read+write) accesses
system.iocache.overall_accesses::pc.south_bridge.ide 47624 # number of overall (read+write) accesses
system.iocache.overall_accesses::total 47624 # number of overall (read+write) accesses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.iocache.WriteReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteReq accesses
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.iocache.demand_miss_rate::pc.south_bridge.ide 1 # miss rate for demand accesses
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
Tests: Update stats due to addition of fence microop
2011-11-05 21:32:23 +01:00
system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
Tests: Update stats due to addition of fence microop
2011-11-05 21:32:23 +01:00
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.iocache.writebacks::writebacks 46667 # number of writebacks
system.iocache.writebacks::total 46667 # number of writebacks
Tests: Update stats due to addition of fence microop
2011-11-05 21:32:23 +01:00
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
X86: Add stats for the new x86 fs regressions.
2011-02-07 10:23:16 +01:00
system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
Tests: Update stats due to addition of fence microop
2011-11-05 21:32:23 +01:00
system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD).
Stats: Update stats for cache timings in cycles This patch updates the stats to reflect the change in how cache latencies are expressed. In addition, the latencies are now rounded to multiples of the clock period, thus also affecting other stats.
2012-10-15 14:12:21 +02:00
system.pc.south_bridge.ide.disks0.dma_read_txs 31 # Number of DMA read transactions (not PRD).
X86: Add stats for the new x86 fs regressions.
2011-02-07 10:23:16 +01:00
system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes.
Tests: Update stats due to addition of fence microop
2011-11-05 21:32:23 +01:00
system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes.
X86: Add stats for the new x86 fs regressions.
2011-02-07 10:23:16 +01:00
system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions.
system.pc.south_bridge.ide.disks1.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
Tests: Update stats due to addition of fence microop
2011-11-05 21:32:23 +01:00
system.pc.south_bridge.ide.disks1.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
X86: Add stats for the new x86 fs regressions.
2011-02-07 10:23:16 +01:00
system.pc.south_bridge.ide.disks1.dma_read_txs 0 # Number of DMA read transactions (not PRD).
system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes.
Tests: Update stats due to addition of fence microop
2011-11-05 21:32:23 +01:00
system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes.
X86: Add stats for the new x86 fs regressions.
2011-02-07 10:23:16 +01:00
system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions.
x86 regressions: updates due to new instructions and cpuid
2013-01-15 14:43:23 +01:00
system.cpu.numCycles 10224081964 # number of cpu cycles simulated
Tests: Update stats due to addition of fence microop
2011-11-05 21:32:23 +01:00
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
x86 regressions: updates due to new instructions and cpuid
2013-01-15 14:43:23 +01:00
system.cpu.committedInsts 199810242 # Number of instructions committed
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.cpu.committedOps 409125913 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 374289904 # Number of integer alu accesses
Tests: Update stats due to addition of fence microop
2011-11-05 21:32:23 +01:00
system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
system.cpu.num_func_calls 0 # number of times a function call or return occured
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.cpu.num_conditional_control_insts 39954533 # number of instructions that are conditional controls
system.cpu.num_int_insts 374289904 # number of integer instructions
Tests: Update stats due to addition of fence microop
2011-11-05 21:32:23 +01:00
system.cpu.num_fp_insts 0 # number of float instructions
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.cpu.num_int_register_reads 915450656 # number of times the integer registers were read
system.cpu.num_int_register_writes 480322719 # number of times the integer registers were written
Tests: Update stats due to addition of fence microop
2011-11-05 21:32:23 +01:00
system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
x86 regressions: updates due to new instructions and cpuid
2013-01-15 14:43:23 +01:00
system.cpu.num_mem_refs 35624590 # number of memory refs
Stats: Update stats for cache timings in cycles This patch updates the stats to reflect the change in how cache latencies are expressed. In addition, the latencies are now rounded to multiples of the clock period, thus also affecting other stats.
2012-10-15 14:12:21 +02:00
system.cpu.num_load_insts 27216588 # Number of load instructions
x86 regressions: updates due to new instructions and cpuid
2013-01-15 14:43:23 +01:00
system.cpu.num_store_insts 8408002 # Number of store instructions
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.cpu.num_idle_cycles 9770609609.165962 # Number of idle cycles
system.cpu.num_busy_cycles 453472354.834038 # Number of busy cycles
Stats: Update stats for cache timings in cycles This patch updates the stats to reflect the change in how cache latencies are expressed. In addition, the latencies are now rounded to multiples of the clock period, thus also affecting other stats.
2012-10-15 14:12:21 +02:00
system.cpu.not_idle_fraction 0.044353 # Percentage of non-idle cycles
system.cpu.idle_fraction 0.955647 # Percentage of idle cycles
Tests: Update stats due to addition of fence microop
2011-11-05 21:32:23 +01:00
system.cpu.kern.inst.arm 0 # number of arm instructions executed
system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed
Stats: Update stats for cache timings in cycles This patch updates the stats to reflect the change in how cache latencies are expressed. In addition, the latencies are now rounded to multiples of the clock period, thus also affecting other stats.
2012-10-15 14:12:21 +02:00
system.cpu.icache.replacements 790732 # number of replacements
x86 regressions: updates due to new instructions and cpuid
2013-01-15 14:43:23 +01:00
system.cpu.icache.tagsinuse 510.627675 # Cycle average of tags in use
system.cpu.icache.total_refs 243360727 # Total number of references to valid blocks.
Stats: Update stats for cache timings in cycles This patch updates the stats to reflect the change in how cache latencies are expressed. In addition, the latencies are now rounded to multiples of the clock period, thus also affecting other stats.
2012-10-15 14:12:21 +02:00
system.cpu.icache.sampled_refs 791244 # Sample count of references to valid blocks.
x86 regressions: updates due to new instructions and cpuid
2013-01-15 14:43:23 +01:00
system.cpu.icache.avg_refs 307.567232 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 148763114500 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst 510.627675 # Average occupied blocks per requestor
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.icache.occ_percent::cpu.inst 0.997320 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.997320 # Average percentage of cache occupancy
x86 regressions: updates due to new instructions and cpuid
2013-01-15 14:43:23 +01:00
system.cpu.icache.ReadReq_hits::cpu.inst 243360727 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 243360727 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 243360727 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 243360727 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 243360727 # number of overall hits
system.cpu.icache.overall_hits::total 243360727 # number of overall hits
Stats: Update stats for cache timings in cycles This patch updates the stats to reflect the change in how cache latencies are expressed. In addition, the latencies are now rounded to multiples of the clock period, thus also affecting other stats.
2012-10-15 14:12:21 +02:00
system.cpu.icache.ReadReq_misses::cpu.inst 791251 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 791251 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 791251 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 791251 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 791251 # number of overall misses
system.cpu.icache.overall_misses::total 791251 # number of overall misses
x86 regressions: updates due to new instructions and cpuid
2013-01-15 14:43:23 +01:00
system.cpu.icache.ReadReq_accesses::cpu.inst 244151978 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 244151978 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 244151978 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 244151978 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 244151978 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 244151978 # number of overall (read+write) accesses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.003241 # miss rate for ReadReq accesses
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu.icache.ReadReq_miss_rate::total 0.003241 # miss rate for ReadReq accesses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.icache.demand_miss_rate::cpu.inst 0.003241 # miss rate for demand accesses
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu.icache.demand_miss_rate::total 0.003241 # miss rate for demand accesses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.icache.overall_miss_rate::cpu.inst 0.003241 # miss rate for overall accesses
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu.icache.overall_miss_rate::total 0.003241 # miss rate for overall accesses
Tests: Update stats due to addition of fence microop
2011-11-05 21:32:23 +01:00
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
Tests: Update stats due to addition of fence microop
2011-11-05 21:32:23 +01:00
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.cpu.itb_walker_cache.replacements 3335 # number of replacements
Stats: Update stats for cache timings in cycles This patch updates the stats to reflect the change in how cache latencies are expressed. In addition, the latencies are now rounded to multiples of the clock period, thus also affecting other stats.
2012-10-15 14:12:21 +02:00
system.cpu.itb_walker_cache.tagsinuse 3.026483 # Cycle average of tags in use
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.cpu.itb_walker_cache.total_refs 8029 # Total number of references to valid blocks.
system.cpu.itb_walker_cache.sampled_refs 3346 # Sample count of references to valid blocks.
system.cpu.itb_walker_cache.avg_refs 2.399582 # Average number of references to valid blocks.
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.cpu.itb_walker_cache.warmup_cycle 5102019607500 # Cycle when the warmup percentage was hit.
Stats: Update stats for cache timings in cycles This patch updates the stats to reflect the change in how cache latencies are expressed. In addition, the latencies are now rounded to multiples of the clock period, thus also affecting other stats.
2012-10-15 14:12:21 +02:00
system.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker 3.026483 # Average occupied blocks per requestor
system.cpu.itb_walker_cache.occ_percent::cpu.itb.walker 0.189155 # Average percentage of cache occupancy
system.cpu.itb_walker_cache.occ_percent::total 0.189155 # Average percentage of cache occupancy
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 8031 # number of ReadReq hits
system.cpu.itb_walker_cache.ReadReq_hits::total 8031 # number of ReadReq hits
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 2 # number of WriteReq hits
Tests: Update stats due to addition of fence microop
2011-11-05 21:32:23 +01:00
system.cpu.itb_walker_cache.WriteReq_hits::total 2 # number of WriteReq hits
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 8033 # number of demand (read+write) hits
system.cpu.itb_walker_cache.demand_hits::total 8033 # number of demand (read+write) hits
system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 8033 # number of overall hits
system.cpu.itb_walker_cache.overall_hits::total 8033 # number of overall hits
system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 4194 # number of ReadReq misses
system.cpu.itb_walker_cache.ReadReq_misses::total 4194 # number of ReadReq misses
system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 4194 # number of demand (read+write) misses
system.cpu.itb_walker_cache.demand_misses::total 4194 # number of demand (read+write) misses
system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 4194 # number of overall misses
system.cpu.itb_walker_cache.overall_misses::total 4194 # number of overall misses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 12225 # number of ReadReq accesses(hits+misses)
X86 Regressions: Update stats due to fence instruction
2012-01-10 16:59:01 +01:00
system.cpu.itb_walker_cache.ReadReq_accesses::total 12225 # number of ReadReq accesses(hits+misses)
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 2 # number of WriteReq accesses(hits+misses)
Tests: Update stats due to addition of fence microop
2011-11-05 21:32:23 +01:00
system.cpu.itb_walker_cache.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses)
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 12227 # number of demand (read+write) accesses
X86 Regressions: Update stats due to fence instruction
2012-01-10 16:59:01 +01:00
system.cpu.itb_walker_cache.demand_accesses::total 12227 # number of demand (read+write) accesses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 12227 # number of overall (read+write) accesses
X86 Regressions: Update stats due to fence instruction
2012-01-10 16:59:01 +01:00
system.cpu.itb_walker_cache.overall_accesses::total 12227 # number of overall (read+write) accesses
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.343067 # miss rate for ReadReq accesses
system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.343067 # miss rate for ReadReq accesses
system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.343011 # miss rate for demand accesses
system.cpu.itb_walker_cache.demand_miss_rate::total 0.343011 # miss rate for demand accesses
system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.343011 # miss rate for overall accesses
system.cpu.itb_walker_cache.overall_miss_rate::total 0.343011 # miss rate for overall accesses
Tests: Update stats due to addition of fence microop
2011-11-05 21:32:23 +01:00
system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.itb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
Tests: Update stats due to addition of fence microop
2011-11-05 21:32:23 +01:00
system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed
system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.cpu.itb_walker_cache.writebacks::writebacks 593 # number of writebacks
system.cpu.itb_walker_cache.writebacks::total 593 # number of writebacks
Tests: Update stats due to addition of fence microop
2011-11-05 21:32:23 +01:00
system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate
Stats: Update stats for cache timings in cycles This patch updates the stats to reflect the change in how cache latencies are expressed. In addition, the latencies are now rounded to multiples of the clock period, thus also affecting other stats.
2012-10-15 14:12:21 +02:00
system.cpu.dtb_walker_cache.replacements 7597 # number of replacements
system.cpu.dtb_walker_cache.tagsinuse 5.013746 # Cycle average of tags in use
system.cpu.dtb_walker_cache.total_refs 13015 # Total number of references to valid blocks.
system.cpu.dtb_walker_cache.sampled_refs 7611 # Sample count of references to valid blocks.
system.cpu.dtb_walker_cache.avg_refs 1.710025 # Average number of references to valid blocks.
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.cpu.dtb_walker_cache.warmup_cycle 5101206385500 # Cycle when the warmup percentage was hit.
Stats: Update stats for cache timings in cycles This patch updates the stats to reflect the change in how cache latencies are expressed. In addition, the latencies are now rounded to multiples of the clock period, thus also affecting other stats.
2012-10-15 14:12:21 +02:00
system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker 5.013746 # Average occupied blocks per requestor
system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker 0.313359 # Average percentage of cache occupancy
system.cpu.dtb_walker_cache.occ_percent::total 0.313359 # Average percentage of cache occupancy
system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 13017 # number of ReadReq hits
system.cpu.dtb_walker_cache.ReadReq_hits::total 13017 # number of ReadReq hits
system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 13017 # number of demand (read+write) hits
system.cpu.dtb_walker_cache.demand_hits::total 13017 # number of demand (read+write) hits
system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 13017 # number of overall hits
system.cpu.dtb_walker_cache.overall_hits::total 13017 # number of overall hits
system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 8791 # number of ReadReq misses
system.cpu.dtb_walker_cache.ReadReq_misses::total 8791 # number of ReadReq misses
system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 8791 # number of demand (read+write) misses
system.cpu.dtb_walker_cache.demand_misses::total 8791 # number of demand (read+write) misses
system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 8791 # number of overall misses
system.cpu.dtb_walker_cache.overall_misses::total 8791 # number of overall misses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 21808 # number of ReadReq accesses(hits+misses)
X86 Regressions: Update stats due to fence instruction
2012-01-10 16:59:01 +01:00
system.cpu.dtb_walker_cache.ReadReq_accesses::total 21808 # number of ReadReq accesses(hits+misses)
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 21808 # number of demand (read+write) accesses
X86 Regressions: Update stats due to fence instruction
2012-01-10 16:59:01 +01:00
system.cpu.dtb_walker_cache.demand_accesses::total 21808 # number of demand (read+write) accesses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 21808 # number of overall (read+write) accesses
X86 Regressions: Update stats due to fence instruction
2012-01-10 16:59:01 +01:00
system.cpu.dtb_walker_cache.overall_accesses::total 21808 # number of overall (read+write) accesses
Stats: Update stats for cache timings in cycles This patch updates the stats to reflect the change in how cache latencies are expressed. In addition, the latencies are now rounded to multiples of the clock period, thus also affecting other stats.
2012-10-15 14:12:21 +02:00
system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.403109 # miss rate for ReadReq accesses
system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.403109 # miss rate for ReadReq accesses
system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.403109 # miss rate for demand accesses
system.cpu.dtb_walker_cache.demand_miss_rate::total 0.403109 # miss rate for demand accesses
system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.403109 # miss rate for overall accesses
system.cpu.dtb_walker_cache.overall_miss_rate::total 0.403109 # miss rate for overall accesses
Tests: Update stats due to addition of fence microop
2011-11-05 21:32:23 +01:00
system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dtb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
Tests: Update stats due to addition of fence microop
2011-11-05 21:32:23 +01:00
system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed
system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.cpu.dtb_walker_cache.writebacks::writebacks 2556 # number of writebacks
system.cpu.dtb_walker_cache.writebacks::total 2556 # number of writebacks
Tests: Update stats due to addition of fence microop
2011-11-05 21:32:23 +01:00
system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate
Stats: Update stats for cache timings in cycles This patch updates the stats to reflect the change in how cache latencies are expressed. In addition, the latencies are now rounded to multiples of the clock period, thus also affecting other stats.
2012-10-15 14:12:21 +02:00
system.cpu.dcache.replacements 1621135 # number of replacements
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.cpu.dcache.tagsinuse 511.999456 # Cycle average of tags in use
x86 regressions: updates due to new instructions and cpuid
2013-01-15 14:43:23 +01:00
system.cpu.dcache.total_refs 20140431 # Total number of references to valid blocks.
Stats: Update stats for cache timings in cycles This patch updates the stats to reflect the change in how cache latencies are expressed. In addition, the latencies are now rounded to multiples of the clock period, thus also affecting other stats.
2012-10-15 14:12:21 +02:00
system.cpu.dcache.sampled_refs 1621647 # Sample count of references to valid blocks.
x86 regressions: updates due to new instructions and cpuid
2013-01-15 14:43:23 +01:00
system.cpu.dcache.avg_refs 12.419738 # Average number of references to valid blocks.
Tests: Update stats due to addition of fence microop
2011-11-05 21:32:23 +01:00
system.cpu.dcache.warmup_cycle 7549500 # Cycle when the warmup percentage was hit.
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.cpu.dcache.occ_blocks::cpu.data 511.999456 # Average occupied blocks per requestor
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.dcache.occ_percent::cpu.data 0.999999 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.999999 # Average percentage of cache occupancy
Stats: Update stats for cache timings in cycles This patch updates the stats to reflect the change in how cache latencies are expressed. In addition, the latencies are now rounded to multiples of the clock period, thus also affecting other stats.
2012-10-15 14:12:21 +02:00
system.cpu.dcache.ReadReq_hits::cpu.data 12055941 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 12055941 # number of ReadReq hits
x86 regressions: updates due to new instructions and cpuid
2013-01-15 14:43:23 +01:00
system.cpu.dcache.WriteReq_hits::cpu.data 8082228 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 8082228 # number of WriteReq hits
system.cpu.dcache.demand_hits::cpu.data 20138169 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 20138169 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 20138169 # number of overall hits
system.cpu.dcache.overall_hits::total 20138169 # number of overall hits
Stats: Update stats for cache timings in cycles This patch updates the stats to reflect the change in how cache latencies are expressed. In addition, the latencies are now rounded to multiples of the clock period, thus also affecting other stats.
2012-10-15 14:12:21 +02:00
system.cpu.dcache.ReadReq_misses::cpu.data 1308091 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 1308091 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 315828 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 315828 # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data 1623919 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 1623919 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 1623919 # number of overall misses
system.cpu.dcache.overall_misses::total 1623919 # number of overall misses
system.cpu.dcache.ReadReq_accesses::cpu.data 13364032 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 13364032 # number of ReadReq accesses(hits+misses)
x86 regressions: updates due to new instructions and cpuid
2013-01-15 14:43:23 +01:00
system.cpu.dcache.WriteReq_accesses::cpu.data 8398056 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 8398056 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 21762088 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 21762088 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 21762088 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 21762088 # number of overall (read+write) accesses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.097881 # miss rate for ReadReq accesses
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu.dcache.ReadReq_miss_rate::total 0.097881 # miss rate for ReadReq accesses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037607 # miss rate for WriteReq accesses
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu.dcache.WriteReq_miss_rate::total 0.037607 # miss rate for WriteReq accesses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.dcache.demand_miss_rate::cpu.data 0.074621 # miss rate for demand accesses
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu.dcache.demand_miss_rate::total 0.074621 # miss rate for demand accesses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.dcache.overall_miss_rate::cpu.data 0.074621 # miss rate for overall accesses
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu.dcache.overall_miss_rate::total 0.074621 # miss rate for overall accesses
Tests: Update stats due to addition of fence microop
2011-11-05 21:32:23 +01:00
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
Tests: Update stats due to addition of fence microop
2011-11-05 21:32:23 +01:00
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
Stats: Update stats for cache timings in cycles This patch updates the stats to reflect the change in how cache latencies are expressed. In addition, the latencies are now rounded to multiples of the clock period, thus also affecting other stats.
2012-10-15 14:12:21 +02:00
system.cpu.dcache.writebacks::writebacks 1534848 # number of writebacks
system.cpu.dcache.writebacks::total 1534848 # number of writebacks
Tests: Update stats due to addition of fence microop
2011-11-05 21:32:23 +01:00
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
Stats: Update stats for cache timings in cycles This patch updates the stats to reflect the change in how cache latencies are expressed. In addition, the latencies are now rounded to multiples of the clock period, thus also affecting other stats.
2012-10-15 14:12:21 +02:00
system.cpu.l2cache.replacements 106558 # number of replacements
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.cpu.l2cache.tagsinuse 64822.149220 # Cycle average of tags in use
Stats: Update stats for cache timings in cycles This patch updates the stats to reflect the change in how cache latencies are expressed. In addition, the latencies are now rounded to multiples of the clock period, thus also affecting other stats.
2012-10-15 14:12:21 +02:00
system.cpu.l2cache.total_refs 3456224 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 170677 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 20.250086 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
x86 regressions: updates due to new instructions and cpuid
2013-01-15 14:43:23 +01:00
system.cpu.l2cache.occ_blocks::writebacks 51981.453118 # Average occupied blocks per requestor
Stats: Update stats for cache timings in cycles This patch updates the stats to reflect the change in how cache latencies are expressed. In addition, the latencies are now rounded to multiples of the clock period, thus also affecting other stats.
2012-10-15 14:12:21 +02:00
system.cpu.l2cache.occ_blocks::cpu.dtb.walker 0.004954 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.itb.walker 0.132114 # Average occupied blocks per requestor
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.cpu.l2cache.occ_blocks::cpu.inst 2434.994083 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data 10405.564952 # Average occupied blocks per requestor
Stats: Update stats for cache timings in cycles This patch updates the stats to reflect the change in how cache latencies are expressed. In addition, the latencies are now rounded to multiples of the clock period, thus also affecting other stats.
2012-10-15 14:12:21 +02:00
system.cpu.l2cache.occ_percent::writebacks 0.793174 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.dtb.walker 0.000000 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.inst 0.037155 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data 0.158776 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::total 0.989108 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 6578 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 2700 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.inst 777896 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data 1275281 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 2062455 # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks 1537997 # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total 1537997 # number of Writeback hits
system.cpu.l2cache.UpgradeReq_hits::cpu.data 28 # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_hits::total 28 # number of UpgradeReq hits
system.cpu.l2cache.ReadExReq_hits::cpu.data 179183 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 179183 # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.dtb.walker 6578 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.itb.walker 2700 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.inst 777896 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data 1454464 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 2241638 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.dtb.walker 6578 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.itb.walker 2700 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.inst 777896 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data 1454464 # number of overall hits
system.cpu.l2cache.overall_hits::total 2241638 # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 2 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 5 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.inst 13342 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data 32182 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total 45531 # number of ReadReq misses
system.cpu.l2cache.UpgradeReq_misses::cpu.data 1796 # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total 1796 # number of UpgradeReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data 134378 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 134378 # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.dtb.walker 2 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.itb.walker 5 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.inst 13342 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 166560 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 179909 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.dtb.walker 2 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.itb.walker 5 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.inst 13342 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 166560 # number of overall misses
system.cpu.l2cache.overall_misses::total 179909 # number of overall misses
system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 6580 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 2705 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.inst 791238 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 1307463 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 2107986 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks 1537997 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total 1537997 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1824 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total 1824 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 313561 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 313561 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.dtb.walker 6580 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.itb.walker 2705 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.inst 791238 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 1621024 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 2421547 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.dtb.walker 6580 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.itb.walker 2705 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 791238 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 1621024 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 2421547 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000304 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.001848 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.016862 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.024614 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total 0.021599 # miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.984649 # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total 0.984649 # miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.428555 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.428555 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000304 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.001848 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016862 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.102750 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.074295 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000304 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.001848 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016862 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.102750 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.074295 # miss rate for overall accesses
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks 98530 # number of writebacks
system.cpu.l2cache.writebacks::total 98530 # number of writebacks
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
X86: Add stats for the new x86 fs regressions.
2011-02-07 10:23:16 +01:00
---------- End Simulation Statistics ----------
Reference in a new issue Copy permalink