gem5/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/stats.txt

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---------- Begin Simulation Statistics ----------
Update Alpha reference stats for clock changes. tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini: tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.out: tests/long/00.gzip/ref/alpha/tru64/o3-timing/m5stats.txt: tests/long/00.gzip/ref/alpha/tru64/simple-atomic/config.ini: tests/long/00.gzip/ref/alpha/tru64/simple-atomic/config.out: tests/long/00.gzip/ref/alpha/tru64/simple-atomic/m5stats.txt: tests/long/00.gzip/ref/alpha/tru64/simple-atomic/stderr: tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.ini: tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.out: tests/long/00.gzip/ref/alpha/tru64/simple-timing/m5stats.txt: tests/long/00.gzip/ref/alpha/tru64/simple-timing/stderr: tests/long/30.eon/ref/alpha/tru64/o3-timing/config.ini: tests/long/30.eon/ref/alpha/tru64/o3-timing/config.out: tests/long/30.eon/ref/alpha/tru64/o3-timing/m5stats.txt: tests/long/30.eon/ref/alpha/tru64/o3-timing/stdout: tests/long/30.eon/ref/alpha/tru64/simple-atomic/config.ini: tests/long/30.eon/ref/alpha/tru64/simple-atomic/config.out: tests/long/30.eon/ref/alpha/tru64/simple-atomic/m5stats.txt: tests/long/30.eon/ref/alpha/tru64/simple-atomic/stderr: tests/long/30.eon/ref/alpha/tru64/simple-atomic/stdout: tests/long/30.eon/ref/alpha/tru64/simple-timing/config.ini: tests/long/30.eon/ref/alpha/tru64/simple-timing/config.out: tests/long/30.eon/ref/alpha/tru64/simple-timing/m5stats.txt: tests/long/30.eon/ref/alpha/tru64/simple-timing/stderr: tests/long/30.eon/ref/alpha/tru64/simple-timing/stdout: tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/config.ini: tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/config.out: tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/m5stats.txt: tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/stderr: tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini: tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/config.out: tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/m5stats.txt: tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/stderr: tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.ini: tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.out: tests/long/50.vortex/ref/alpha/tru64/o3-timing/m5stats.txt: tests/long/50.vortex/ref/alpha/tru64/o3-timing/smred.msg: tests/long/50.vortex/ref/alpha/tru64/simple-atomic/config.ini: tests/long/50.vortex/ref/alpha/tru64/simple-atomic/config.out: tests/long/50.vortex/ref/alpha/tru64/simple-atomic/m5stats.txt: tests/long/50.vortex/ref/alpha/tru64/simple-atomic/stderr: tests/long/50.vortex/ref/alpha/tru64/simple-timing/config.ini: tests/long/50.vortex/ref/alpha/tru64/simple-timing/config.out: tests/long/50.vortex/ref/alpha/tru64/simple-timing/m5stats.txt: tests/long/50.vortex/ref/alpha/tru64/simple-timing/stderr: tests/long/60.bzip2/ref/alpha/tru64/o3-timing/config.ini: tests/long/60.bzip2/ref/alpha/tru64/o3-timing/config.out: tests/long/60.bzip2/ref/alpha/tru64/o3-timing/m5stats.txt: tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/config.ini: tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/config.out: tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/m5stats.txt: tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/stderr: tests/long/60.bzip2/ref/alpha/tru64/simple-timing/config.ini: tests/long/60.bzip2/ref/alpha/tru64/simple-timing/config.out: tests/long/60.bzip2/ref/alpha/tru64/simple-timing/m5stats.txt: tests/long/60.bzip2/ref/alpha/tru64/simple-timing/stderr: tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.ini: tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.out: tests/long/70.twolf/ref/alpha/tru64/o3-timing/m5stats.txt: tests/long/70.twolf/ref/alpha/tru64/simple-atomic/config.ini: tests/long/70.twolf/ref/alpha/tru64/simple-atomic/config.out: tests/long/70.twolf/ref/alpha/tru64/simple-atomic/m5stats.txt: tests/long/70.twolf/ref/alpha/tru64/simple-atomic/smred.out: tests/long/70.twolf/ref/alpha/tru64/simple-atomic/stderr: tests/long/70.twolf/ref/alpha/tru64/simple-timing/config.ini: tests/long/70.twolf/ref/alpha/tru64/simple-timing/config.out: tests/long/70.twolf/ref/alpha/tru64/simple-timing/m5stats.txt: tests/long/70.twolf/ref/alpha/tru64/simple-timing/smred.out: tests/long/70.twolf/ref/alpha/tru64/simple-timing/stderr: Update refs for clock changes. --HG-- extra : convert_revision : 7c32a3362da60fd12b7bf9219842f707319cda42
2007-04-27 20:35:58 +02:00
sim_seconds 0.045952 # Number of seconds simulated
sim_ticks 45951567500 # Number of ticks simulated
final_tick 45951567500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 2845952 # Simulator instruction rate (inst/s)
host_op_rate 2845951 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1422976169 # Simulator tick rate (ticks/s)
host_mem_usage 283520 # Number of bytes of host memory used
host_seconds 32.29 # Real time elapsed on the host
sim_insts 91903056 # Number of instructions simulated
sim_ops 91903056 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::cpu.inst 367612356 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 108337521 # Number of bytes read from this memory
system.physmem.bytes_read::total 475949877 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 367612356 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 367612356 # Number of instructions bytes read from this memory
system.physmem.bytes_written::cpu.data 30920974 # Number of bytes written to this memory
system.physmem.bytes_written::total 30920974 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 91903089 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 19996198 # Number of read requests responded to by this memory
system.physmem.num_reads::total 111899287 # Number of read requests responded to by this memory
system.physmem.num_writes::cpu.data 6501103 # Number of write requests responded to by this memory
system.physmem.num_writes::total 6501103 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 7999995996 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 2357645819 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 10357641815 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 7999995996 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 7999995996 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data 672903574 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 672903574 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 7999995996 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 3030549393 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 11030545389 # Total bandwidth to/from this memory (bytes/s)
system.membus.trans_dist::ReadReq 111899287 # Transaction distribution
system.membus.trans_dist::ReadResp 111899287 # Transaction distribution
system.membus.trans_dist::WriteReq 6501103 # Transaction distribution
system.membus.trans_dist::WriteResp 6501103 # Transaction distribution
system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 183806178 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 52994602 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 236800780 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 367612356 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 139258495 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 506870851 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
system.membus.snoop_fanout::samples 118400390 # Request fanout histogram
system.membus.snoop_fanout::mean 0.776206 # Request fanout histogram
system.membus.snoop_fanout::stdev 0.416786 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 26497301 22.38% 22.38% # Request fanout histogram
system.membus.snoop_fanout::1 91903089 77.62% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
system.membus.snoop_fanout::total 118400390 # Request fanout histogram
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
system.cpu.dtb.read_hits 19996198 # DTB read hits
system.cpu.dtb.read_misses 10 # DTB read misses
system.cpu.dtb.read_acv 0 # DTB read access violations
system.cpu.dtb.read_accesses 19996208 # DTB read accesses
system.cpu.dtb.write_hits 6501103 # DTB write hits
system.cpu.dtb.write_misses 23 # DTB write misses
system.cpu.dtb.write_acv 0 # DTB write access violations
system.cpu.dtb.write_accesses 6501126 # DTB write accesses
system.cpu.dtb.data_hits 26497301 # DTB hits
system.cpu.dtb.data_misses 33 # DTB misses
system.cpu.dtb.data_acv 0 # DTB access violations
system.cpu.dtb.data_accesses 26497334 # DTB accesses
system.cpu.itb.fetch_hits 91903089 # ITB hits
system.cpu.itb.fetch_misses 47 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
system.cpu.itb.fetch_accesses 91903136 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.write_acv 0 # DTB write access violations
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.data_hits 0 # DTB hits
system.cpu.itb.data_misses 0 # DTB misses
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 389 # Number of system calls
system.cpu.numCycles 91903136 # number of cpu cycles simulated
2011-02-08 04:23:13 +01:00
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 91903056 # Number of instructions committed
system.cpu.committedOps 91903056 # Number of ops (including micro ops) committed
2011-02-08 04:23:13 +01:00
system.cpu.num_int_alu_accesses 79581109 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 6862064 # Number of float alu accesses
system.cpu.num_func_calls 2059216 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 7465012 # number of instructions that are conditional controls
2011-02-08 04:23:13 +01:00
system.cpu.num_int_insts 79581109 # number of integer instructions
system.cpu.num_fp_insts 6862064 # number of float instructions
2011-02-08 04:23:13 +01:00
system.cpu.num_int_register_reads 115028592 # number of times the integer registers were read
system.cpu.num_int_register_writes 62575473 # number of times the integer registers were written
system.cpu.num_fp_register_reads 6071661 # number of times the floating registers were read
system.cpu.num_fp_register_writes 5851888 # number of times the floating registers were written
2011-02-08 04:23:13 +01:00
system.cpu.num_mem_refs 26497334 # number of memory refs
system.cpu.num_load_insts 19996208 # Number of load instructions
2011-02-08 04:23:13 +01:00
system.cpu.num_store_insts 6501126 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_busy_cycles 91903136 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.Branches 10240685 # Number of branches fetched
system.cpu.op_class::No_OpClass 7723353 8.40% 8.40% # Class of executed instruction
system.cpu.op_class::IntAlu 51001454 55.49% 63.90% # Class of executed instruction
system.cpu.op_class::IntMult 458252 0.50% 64.40% # Class of executed instruction
system.cpu.op_class::IntDiv 0 0.00% 64.40% # Class of executed instruction
system.cpu.op_class::FloatAdd 2732553 2.97% 67.37% # Class of executed instruction
system.cpu.op_class::FloatCmp 104605 0.11% 67.48% # Class of executed instruction
system.cpu.op_class::FloatCvt 2333953 2.54% 70.02% # Class of executed instruction
system.cpu.op_class::FloatMult 296445 0.32% 70.35% # Class of executed instruction
system.cpu.op_class::FloatDiv 754822 0.82% 71.17% # Class of executed instruction
system.cpu.op_class::FloatSqrt 318 0.00% 71.17% # Class of executed instruction
system.cpu.op_class::SimdAdd 0 0.00% 71.17% # Class of executed instruction
system.cpu.op_class::SimdAddAcc 0 0.00% 71.17% # Class of executed instruction
system.cpu.op_class::SimdAlu 0 0.00% 71.17% # Class of executed instruction
system.cpu.op_class::SimdCmp 0 0.00% 71.17% # Class of executed instruction
system.cpu.op_class::SimdCvt 0 0.00% 71.17% # Class of executed instruction
system.cpu.op_class::SimdMisc 0 0.00% 71.17% # Class of executed instruction
system.cpu.op_class::SimdMult 0 0.00% 71.17% # Class of executed instruction
system.cpu.op_class::SimdMultAcc 0 0.00% 71.17% # Class of executed instruction
system.cpu.op_class::SimdShift 0 0.00% 71.17% # Class of executed instruction
system.cpu.op_class::SimdShiftAcc 0 0.00% 71.17% # Class of executed instruction
system.cpu.op_class::SimdSqrt 0 0.00% 71.17% # Class of executed instruction
system.cpu.op_class::SimdFloatAdd 0 0.00% 71.17% # Class of executed instruction
system.cpu.op_class::SimdFloatAlu 0 0.00% 71.17% # Class of executed instruction
system.cpu.op_class::SimdFloatCmp 0 0.00% 71.17% # Class of executed instruction
system.cpu.op_class::SimdFloatCvt 0 0.00% 71.17% # Class of executed instruction
system.cpu.op_class::SimdFloatDiv 0 0.00% 71.17% # Class of executed instruction
system.cpu.op_class::SimdFloatMisc 0 0.00% 71.17% # Class of executed instruction
system.cpu.op_class::SimdFloatMult 0 0.00% 71.17% # Class of executed instruction
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 71.17% # Class of executed instruction
system.cpu.op_class::SimdFloatSqrt 0 0.00% 71.17% # Class of executed instruction
system.cpu.op_class::MemRead 19996208 21.76% 92.93% # Class of executed instruction
system.cpu.op_class::MemWrite 6501126 7.07% 100.00% # Class of executed instruction
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 91903089 # Class of executed instruction
---------- End Simulation Statistics ----------