2006-09-01 23:59:36 +02:00
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---------- Begin Simulation Statistics ----------
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2011-04-22 19:18:51 +02:00
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host_inst_rate 96993 # Simulator instruction rate (inst/s)
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|
host_mem_usage 206980 # Number of bytes of host memory used
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|
host_seconds 0.07 # Real time elapsed on the host
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|
host_tick_rate 187197945 # Simulator tick rate (ticks/s)
|
2006-09-01 23:59:36 +02:00
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|
sim_freq 1000000000000 # Frequency of simulated ticks
|
2008-12-05 18:09:29 +01:00
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|
|
sim_insts 6386 # Number of instructions simulated
|
2008-08-04 00:13:29 +02:00
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|
sim_seconds 0.000012 # Number of seconds simulated
|
2011-04-04 18:42:25 +02:00
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|
sim_ticks 12357500 # Number of ticks simulated
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2009-03-07 23:30:55 +01:00
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|
|
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
2011-04-04 18:42:25 +02:00
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|
system.cpu.BPredUnit.BTBHits 670 # Number of BTB hits
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|
system.cpu.BPredUnit.BTBLookups 1765 # Number of BTB lookups
|
2010-05-14 05:45:59 +02:00
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|
system.cpu.BPredUnit.RASInCorrect 65 # Number of incorrect RAS predictions.
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|
system.cpu.BPredUnit.condIncorrect 443 # Number of conditional branches incorrect
|
2011-04-04 18:42:25 +02:00
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system.cpu.BPredUnit.condPredicted 1297 # Number of conditional branches predicted
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system.cpu.BPredUnit.lookups 2180 # Number of BP lookups
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system.cpu.BPredUnit.usedRAS 306 # Number of times the RAS was used to get a target.
|
2010-05-14 05:45:59 +02:00
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|
|
system.cpu.commit.branchMispredicts 369 # The number of times a branch was mispredicted
|
2011-04-20 03:45:23 +02:00
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|
system.cpu.commit.branches 1051 # Number of branches committed
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|
system.cpu.commit.bw_lim_events 127 # number cycles where commit BW limit reached
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system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
|
2008-12-05 18:09:29 +01:00
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system.cpu.commit.commitCommittedInsts 6403 # The number of committed instructions
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2006-09-01 23:59:36 +02:00
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|
system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards
|
2011-04-04 18:42:25 +02:00
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|
system.cpu.commit.commitSquashedInsts 4249 # The number of squashed insts skipped by commit
|
2011-04-20 03:45:23 +02:00
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system.cpu.commit.committed_per_cycle::samples 12090 # Number of insts commited each cycle
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system.cpu.commit.committed_per_cycle::mean 0.529611 # Number of insts commited each cycle
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system.cpu.commit.committed_per_cycle::stdev 1.331978 # Number of insts commited each cycle
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system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
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system.cpu.commit.committed_per_cycle::0 9222 76.28% 76.28% # Number of insts commited each cycle
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system.cpu.commit.committed_per_cycle::1 1613 13.34% 89.62% # Number of insts commited each cycle
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system.cpu.commit.committed_per_cycle::2 453 3.75% 93.37% # Number of insts commited each cycle
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system.cpu.commit.committed_per_cycle::3 264 2.18% 95.55% # Number of insts commited each cycle
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system.cpu.commit.committed_per_cycle::4 157 1.30% 96.85% # Number of insts commited each cycle
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|
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system.cpu.commit.committed_per_cycle::5 121 1.00% 97.85% # Number of insts commited each cycle
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|
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|
|
system.cpu.commit.committed_per_cycle::6 88 0.73% 98.58% # Number of insts commited each cycle
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|
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system.cpu.commit.committed_per_cycle::7 45 0.37% 98.95% # Number of insts commited each cycle
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|
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system.cpu.commit.committed_per_cycle::8 127 1.05% 100.00% # Number of insts commited each cycle
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|
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
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|
|
|
|
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
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system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
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system.cpu.commit.committed_per_cycle::total 12090 # Number of insts commited each cycle
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system.cpu.commit.count 6403 # Number of instructions committed
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system.cpu.commit.fp_insts 10 # Number of committed floating point instructions.
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system.cpu.commit.function_calls 127 # Number of function calls committed.
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system.cpu.commit.int_insts 6321 # Number of committed integer instructions.
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system.cpu.commit.loads 1185 # Number of loads committed
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system.cpu.commit.membars 0 # Number of memory barriers committed
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system.cpu.commit.refs 2050 # Number of memory references committed
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|
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
|
2008-12-05 18:09:29 +01:00
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|
system.cpu.committedInsts 6386 # Number of Instructions Simulated
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system.cpu.committedInsts_total 6386 # Number of Instructions Simulated
|
2011-04-04 18:42:25 +02:00
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|
system.cpu.cpi 3.870341 # CPI: Cycles Per Instruction
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system.cpu.cpi_total 3.870341 # CPI: Total CPI of All Threads
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system.cpu.dcache.ReadReq_accesses 1705 # number of ReadReq accesses(hits+misses)
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system.cpu.dcache.ReadReq_avg_miss_latency 36146.666667 # average ReadReq miss latency
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system.cpu.dcache.ReadReq_avg_mshr_miss_latency 36227.722772 # average ReadReq mshr miss latency
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system.cpu.dcache.ReadReq_hits 1555 # number of ReadReq hits
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system.cpu.dcache.ReadReq_miss_latency 5422000 # number of ReadReq miss cycles
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system.cpu.dcache.ReadReq_miss_rate 0.087977 # miss rate for ReadReq accesses
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system.cpu.dcache.ReadReq_misses 150 # number of ReadReq misses
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system.cpu.dcache.ReadReq_mshr_hits 49 # number of ReadReq MSHR hits
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system.cpu.dcache.ReadReq_mshr_miss_latency 3659000 # number of ReadReq MSHR miss cycles
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system.cpu.dcache.ReadReq_mshr_miss_rate 0.059238 # mshr miss rate for ReadReq accesses
|
2008-12-05 18:09:29 +01:00
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system.cpu.dcache.ReadReq_mshr_misses 101 # number of ReadReq MSHR misses
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system.cpu.dcache.WriteReq_accesses 865 # number of WriteReq accesses(hits+misses)
|
2011-04-04 18:42:25 +02:00
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system.cpu.dcache.WriteReq_avg_miss_latency 35022.471910 # average WriteReq miss latency
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system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35883.561644 # average WriteReq mshr miss latency
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system.cpu.dcache.WriteReq_hits 509 # number of WriteReq hits
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|
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system.cpu.dcache.WriteReq_miss_latency 12468000 # number of WriteReq miss cycles
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system.cpu.dcache.WriteReq_miss_rate 0.411561 # miss rate for WriteReq accesses
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system.cpu.dcache.WriteReq_misses 356 # number of WriteReq misses
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|
|
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system.cpu.dcache.WriteReq_mshr_hits 283 # number of WriteReq MSHR hits
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system.cpu.dcache.WriteReq_mshr_miss_latency 2619500 # number of WriteReq MSHR miss cycles
|
2010-09-09 20:40:19 +02:00
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|
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system.cpu.dcache.WriteReq_mshr_miss_rate 0.084393 # mshr miss rate for WriteReq accesses
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system.cpu.dcache.WriteReq_mshr_misses 73 # number of WriteReq MSHR misses
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2009-04-22 19:25:17 +02:00
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system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
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|
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|
|
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
2011-04-04 18:42:25 +02:00
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system.cpu.dcache.avg_refs 11.862069 # Average number of references to valid blocks.
|
2009-04-22 19:25:17 +02:00
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|
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system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
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|
|
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system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
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|
|
|
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system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
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|
|
|
|
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
2006-09-01 23:59:36 +02:00
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system.cpu.dcache.cache_copies 0 # number of cache copies performed
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2011-04-04 18:42:25 +02:00
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system.cpu.dcache.demand_accesses 2570 # number of demand (read+write) accesses
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system.cpu.dcache.demand_avg_miss_latency 35355.731225 # average overall miss latency
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system.cpu.dcache.demand_avg_mshr_miss_latency 36083.333333 # average overall mshr miss latency
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system.cpu.dcache.demand_hits 2064 # number of demand (read+write) hits
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system.cpu.dcache.demand_miss_latency 17890000 # number of demand (read+write) miss cycles
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system.cpu.dcache.demand_miss_rate 0.196887 # miss rate for demand accesses
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system.cpu.dcache.demand_misses 506 # number of demand (read+write) misses
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system.cpu.dcache.demand_mshr_hits 332 # number of demand (read+write) MSHR hits
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system.cpu.dcache.demand_mshr_miss_latency 6278500 # number of demand (read+write) MSHR miss cycles
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system.cpu.dcache.demand_mshr_miss_rate 0.067704 # mshr miss rate for demand accesses
|
2010-09-09 20:40:19 +02:00
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system.cpu.dcache.demand_mshr_misses 174 # number of demand (read+write) MSHR misses
|
2006-09-01 23:59:36 +02:00
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system.cpu.dcache.fast_writes 0 # number of fast writes performed
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|
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system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
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system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2011-04-04 18:42:25 +02:00
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system.cpu.dcache.occ_blocks::0 109.940770 # Average occupied blocks per context
|
2011-04-20 03:45:23 +02:00
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system.cpu.dcache.occ_percent::0 0.026841 # Average percentage of cache occupancy
|
2011-04-04 18:42:25 +02:00
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system.cpu.dcache.overall_accesses 2570 # number of overall (read+write) accesses
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system.cpu.dcache.overall_avg_miss_latency 35355.731225 # average overall miss latency
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system.cpu.dcache.overall_avg_mshr_miss_latency 36083.333333 # average overall mshr miss latency
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2009-04-22 19:25:17 +02:00
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system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
2011-04-04 18:42:25 +02:00
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system.cpu.dcache.overall_hits 2064 # number of overall hits
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|
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system.cpu.dcache.overall_miss_latency 17890000 # number of overall miss cycles
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system.cpu.dcache.overall_miss_rate 0.196887 # miss rate for overall accesses
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|
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system.cpu.dcache.overall_misses 506 # number of overall misses
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|
|
|
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system.cpu.dcache.overall_mshr_hits 332 # number of overall MSHR hits
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|
|
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system.cpu.dcache.overall_mshr_miss_latency 6278500 # number of overall MSHR miss cycles
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|
|
|
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system.cpu.dcache.overall_mshr_miss_rate 0.067704 # mshr miss rate for overall accesses
|
2010-09-09 20:40:19 +02:00
|
|
|
system.cpu.dcache.overall_mshr_misses 174 # number of overall MSHR misses
|
2006-09-01 23:59:36 +02:00
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|
|
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
|
|
|
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
|
|
|
|
system.cpu.dcache.replacements 0 # number of replacements
|
2008-12-05 18:09:29 +01:00
|
|
|
system.cpu.dcache.sampled_refs 174 # Sample count of references to valid blocks.
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
2011-04-04 18:42:25 +02:00
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|
|
system.cpu.dcache.tagsinuse 109.940770 # Cycle average of tags in use
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system.cpu.dcache.total_refs 2064 # Total number of references to valid blocks.
|
2006-09-01 23:59:36 +02:00
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|
|
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
|
|
|
system.cpu.dcache.writebacks 0 # number of writebacks
|
2011-04-20 03:45:23 +02:00
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|
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system.cpu.decode.BlockedCycles 1035 # Number of cycles decode is blocked
|
|
|
|
|
system.cpu.decode.BranchMispred 75 # Number of times decode detected a branch misprediction
|
|
|
|
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system.cpu.decode.BranchResolved 181 # Number of times decode resolved a branch
|
|
|
|
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system.cpu.decode.DecodedInsts 12021 # Number of instructions handled by decode
|
|
|
|
|
system.cpu.decode.IdleCycles 8780 # Number of cycles decode is idle
|
|
|
|
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system.cpu.decode.RunCycles 2228 # Number of cycles decode is running
|
|
|
|
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system.cpu.decode.SquashCycles 825 # Number of cycles decode is squashing
|
|
|
|
|
system.cpu.decode.SquashedInsts 209 # Number of squashed instructions handled by decode
|
|
|
|
|
system.cpu.decode.UnblockCycles 47 # Number of cycles decode is unblocking
|
2011-04-04 18:42:25 +02:00
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|
|
system.cpu.dtb.data_accesses 2822 # DTB accesses
|
2009-04-09 07:21:30 +02:00
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|
|
system.cpu.dtb.data_acv 0 # DTB access violations
|
2011-04-04 18:42:25 +02:00
|
|
|
system.cpu.dtb.data_hits 2761 # DTB hits
|
2009-04-09 07:21:30 +02:00
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|
|
system.cpu.dtb.data_misses 61 # DTB misses
|
|
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|
system.cpu.dtb.fetch_accesses 0 # ITB accesses
|
|
|
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|
system.cpu.dtb.fetch_acv 0 # ITB acv
|
|
|
|
|
system.cpu.dtb.fetch_hits 0 # ITB hits
|
|
|
|
|
system.cpu.dtb.fetch_misses 0 # ITB misses
|
2011-04-04 18:42:25 +02:00
|
|
|
system.cpu.dtb.read_accesses 1786 # DTB read accesses
|
2007-08-27 05:27:53 +02:00
|
|
|
system.cpu.dtb.read_acv 0 # DTB read access violations
|
2011-04-04 18:42:25 +02:00
|
|
|
system.cpu.dtb.read_hits 1750 # DTB read hits
|
2008-08-04 00:13:29 +02:00
|
|
|
system.cpu.dtb.read_misses 36 # DTB read misses
|
2011-04-04 18:42:25 +02:00
|
|
|
system.cpu.dtb.write_accesses 1036 # DTB write accesses
|
2007-08-27 05:27:53 +02:00
|
|
|
system.cpu.dtb.write_acv 0 # DTB write access violations
|
2011-04-04 18:42:25 +02:00
|
|
|
system.cpu.dtb.write_hits 1011 # DTB write hits
|
2008-08-04 00:13:29 +02:00
|
|
|
system.cpu.dtb.write_misses 25 # DTB write misses
|
2011-04-04 18:42:25 +02:00
|
|
|
system.cpu.fetch.Branches 2180 # Number of branches that fetch encountered
|
|
|
|
|
system.cpu.fetch.CacheLines 1711 # Number of cache lines fetched
|
|
|
|
|
system.cpu.fetch.Cycles 2325 # Number of cycles fetch has run and was not squashing or blocked
|
|
|
|
|
system.cpu.fetch.IcacheSquashes 248 # Number of outstanding Icache misses that were squashed
|
|
|
|
|
system.cpu.fetch.Insts 12863 # Number of instructions fetch has processed
|
|
|
|
|
system.cpu.fetch.MiscStallCycles 33 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
|
|
|
|
system.cpu.fetch.SquashCycles 482 # Number of cycles fetch has spent squashing
|
|
|
|
|
system.cpu.fetch.branchRate 0.088202 # Number of branch fetches per cycle
|
|
|
|
|
system.cpu.fetch.icacheStallCycles 1711 # Number of cycles fetch is stalled on an Icache miss
|
|
|
|
|
system.cpu.fetch.predictedBranches 976 # Number of branches that fetch has predicted taken
|
|
|
|
|
system.cpu.fetch.rate 0.520432 # Number of inst fetches per cycle
|
|
|
|
|
system.cpu.fetch.rateDist::samples 12915 # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.rateDist::mean 0.995974 # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.rateDist::stdev 2.389736 # Number of instructions fetched each cycle (Total)
|
2009-07-07 00:49:48 +02:00
|
|
|
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
2011-04-04 18:42:25 +02:00
|
|
|
system.cpu.fetch.rateDist::0 10590 82.00% 82.00% # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.rateDist::1 233 1.80% 83.80% # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.rateDist::2 211 1.63% 85.44% # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.rateDist::3 179 1.39% 86.82% # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.rateDist::4 229 1.77% 88.59% # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.rateDist::5 156 1.21% 89.80% # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.rateDist::6 218 1.69% 91.49% # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.rateDist::7 125 0.97% 92.46% # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.rateDist::8 974 7.54% 100.00% # Number of instructions fetched each cycle (Total)
|
2009-07-07 00:49:48 +02:00
|
|
|
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
2011-04-04 18:42:25 +02:00
|
|
|
system.cpu.fetch.rateDist::total 12915 # Number of instructions fetched each cycle (Total)
|
2011-02-08 04:23:13 +01:00
|
|
|
system.cpu.fp_regfile_reads 8 # number of floating regfile reads
|
|
|
|
|
system.cpu.fp_regfile_writes 2 # number of floating regfile writes
|
2011-04-04 18:42:25 +02:00
|
|
|
system.cpu.icache.ReadReq_accesses 1711 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.icache.ReadReq_avg_miss_latency 35919.512195 # average ReadReq miss latency
|
2010-05-14 05:45:59 +02:00
|
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency 35283.387622 # average ReadReq mshr miss latency
|
2011-04-04 18:42:25 +02:00
|
|
|
system.cpu.icache.ReadReq_hits 1301 # number of ReadReq hits
|
|
|
|
|
system.cpu.icache.ReadReq_miss_latency 14727000 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.icache.ReadReq_miss_rate 0.239626 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.icache.ReadReq_misses 410 # number of ReadReq misses
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_hits 103 # number of ReadReq MSHR hits
|
2010-05-14 05:45:59 +02:00
|
|
|
system.cpu.icache.ReadReq_mshr_miss_latency 10832000 # number of ReadReq MSHR miss cycles
|
2011-04-04 18:42:25 +02:00
|
|
|
system.cpu.icache.ReadReq_mshr_miss_rate 0.179427 # mshr miss rate for ReadReq accesses
|
2008-12-05 18:09:29 +01:00
|
|
|
system.cpu.icache.ReadReq_mshr_misses 307 # number of ReadReq MSHR misses
|
2009-04-22 19:25:17 +02:00
|
|
|
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
2011-04-04 18:42:25 +02:00
|
|
|
system.cpu.icache.avg_refs 4.237785 # Average number of references to valid blocks.
|
2009-04-22 19:25:17 +02:00
|
|
|
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
2011-04-04 18:42:25 +02:00
|
|
|
system.cpu.icache.demand_accesses 1711 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.icache.demand_avg_miss_latency 35919.512195 # average overall miss latency
|
2010-05-14 05:45:59 +02:00
|
|
|
system.cpu.icache.demand_avg_mshr_miss_latency 35283.387622 # average overall mshr miss latency
|
2011-04-04 18:42:25 +02:00
|
|
|
system.cpu.icache.demand_hits 1301 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.icache.demand_miss_latency 14727000 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.icache.demand_miss_rate 0.239626 # miss rate for demand accesses
|
|
|
|
|
system.cpu.icache.demand_misses 410 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.icache.demand_mshr_hits 103 # number of demand (read+write) MSHR hits
|
2010-05-14 05:45:59 +02:00
|
|
|
system.cpu.icache.demand_mshr_miss_latency 10832000 # number of demand (read+write) MSHR miss cycles
|
2011-04-04 18:42:25 +02:00
|
|
|
system.cpu.icache.demand_mshr_miss_rate 0.179427 # mshr miss rate for demand accesses
|
2008-12-05 18:09:29 +01:00
|
|
|
system.cpu.icache.demand_mshr_misses 307 # number of demand (read+write) MSHR misses
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
|
|
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2011-04-04 18:42:25 +02:00
|
|
|
system.cpu.icache.occ_blocks::0 157.666490 # Average occupied blocks per context
|
2011-04-20 03:45:23 +02:00
|
|
|
system.cpu.icache.occ_percent::0 0.076986 # Average percentage of cache occupancy
|
2011-04-04 18:42:25 +02:00
|
|
|
system.cpu.icache.overall_accesses 1711 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.icache.overall_avg_miss_latency 35919.512195 # average overall miss latency
|
2010-05-14 05:45:59 +02:00
|
|
|
system.cpu.icache.overall_avg_mshr_miss_latency 35283.387622 # average overall mshr miss latency
|
2009-04-22 19:25:17 +02:00
|
|
|
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
2011-04-04 18:42:25 +02:00
|
|
|
system.cpu.icache.overall_hits 1301 # number of overall hits
|
|
|
|
|
system.cpu.icache.overall_miss_latency 14727000 # number of overall miss cycles
|
|
|
|
|
system.cpu.icache.overall_miss_rate 0.239626 # miss rate for overall accesses
|
|
|
|
|
system.cpu.icache.overall_misses 410 # number of overall misses
|
|
|
|
|
system.cpu.icache.overall_mshr_hits 103 # number of overall MSHR hits
|
2010-05-14 05:45:59 +02:00
|
|
|
system.cpu.icache.overall_mshr_miss_latency 10832000 # number of overall MSHR miss cycles
|
2011-04-04 18:42:25 +02:00
|
|
|
system.cpu.icache.overall_mshr_miss_rate 0.179427 # mshr miss rate for overall accesses
|
2008-12-05 18:09:29 +01:00
|
|
|
system.cpu.icache.overall_mshr_misses 307 # number of overall MSHR misses
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
|
|
|
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
|
|
|
|
system.cpu.icache.replacements 0 # number of replacements
|
2008-12-05 18:09:29 +01:00
|
|
|
system.cpu.icache.sampled_refs 307 # Sample count of references to valid blocks.
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
2011-04-04 18:42:25 +02:00
|
|
|
system.cpu.icache.tagsinuse 157.666490 # Cycle average of tags in use
|
|
|
|
|
system.cpu.icache.total_refs 1301 # Total number of references to valid blocks.
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
|
|
|
system.cpu.icache.writebacks 0 # number of writebacks
|
2011-04-04 18:42:25 +02:00
|
|
|
system.cpu.idleCycles 11801 # Total number of cycles that the CPU has spent unscheduled due to idling
|
|
|
|
|
system.cpu.iew.branchMispredicts 429 # Number of branch mispredicts detected at execute
|
2011-04-20 03:45:23 +02:00
|
|
|
system.cpu.iew.exec_branches 1424 # Number of branches executed
|
|
|
|
|
system.cpu.iew.exec_nop 82 # number of nop insts executed
|
|
|
|
|
system.cpu.iew.exec_rate 0.357542 # Inst execution rate
|
|
|
|
|
system.cpu.iew.exec_refs 2832 # number of memory reference insts executed
|
|
|
|
|
system.cpu.iew.exec_stores 1038 # Number of stores executed
|
|
|
|
|
system.cpu.iew.exec_swp 0 # number of swp insts executed
|
2011-04-04 18:42:25 +02:00
|
|
|
system.cpu.iew.iewBlockCycles 67 # Number of cycles IEW is blocking
|
|
|
|
|
system.cpu.iew.iewDispLoadInsts 2144 # Number of dispatched load instructions
|
2010-05-14 05:45:59 +02:00
|
|
|
system.cpu.iew.iewDispNonSpecInsts 25 # Number of dispatched non-speculative instructions
|
2010-09-09 20:40:19 +02:00
|
|
|
system.cpu.iew.iewDispSquashedInsts 193 # Number of squashed instructions skipped by dispatch
|
2011-04-04 18:42:25 +02:00
|
|
|
system.cpu.iew.iewDispStoreInsts 1195 # Number of dispatched store instructions
|
|
|
|
|
system.cpu.iew.iewDispatchedInsts 10669 # Number of instructions dispatched to IQ
|
|
|
|
|
system.cpu.iew.iewExecLoadInsts 1794 # Number of load instructions executed
|
|
|
|
|
system.cpu.iew.iewExecSquashedInsts 271 # Number of squashed instructions skipped in execute
|
|
|
|
|
system.cpu.iew.iewExecutedInsts 8837 # Number of executed instructions
|
2010-05-14 05:45:59 +02:00
|
|
|
system.cpu.iew.iewIQFullEvents 7 # Number of times the IQ has become full, causing a stall
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
2007-04-22 20:50:37 +02:00
|
|
|
system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
|
2011-04-04 18:42:25 +02:00
|
|
|
system.cpu.iew.iewSquashCycles 825 # Number of cycles IEW is squashing
|
2010-09-09 20:40:19 +02:00
|
|
|
system.cpu.iew.iewUnblockCycles 9 # Number of cycles IEW is unblocking
|
2011-04-22 19:18:51 +02:00
|
|
|
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
|
|
|
|
system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
|
|
|
|
|
system.cpu.iew.lsq.thread0.forwLoads 44 # Number of loads that had data forwarded from stores
|
|
|
|
|
system.cpu.iew.lsq.thread0.ignoredResponses 6 # Number of memory responses ignored because the instruction is squashed
|
|
|
|
|
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
|
|
|
|
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
|
|
|
|
system.cpu.iew.lsq.thread0.memOrderViolation 16 # Number of memory ordering violations
|
|
|
|
|
system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled
|
|
|
|
|
system.cpu.iew.lsq.thread0.squashedLoads 959 # Number of loads squashed
|
|
|
|
|
system.cpu.iew.lsq.thread0.squashedStores 330 # Number of stores squashed
|
2011-04-04 18:42:25 +02:00
|
|
|
system.cpu.iew.memOrderViolationEvents 16 # Number of memory order violations
|
|
|
|
|
system.cpu.iew.predictedNotTakenIncorrect 304 # Number of branches that were predicted not taken incorrectly
|
2010-05-14 05:45:59 +02:00
|
|
|
system.cpu.iew.predictedTakenIncorrect 125 # Number of branches that were predicted taken incorrectly
|
2011-04-20 03:45:23 +02:00
|
|
|
system.cpu.iew.wb_consumers 5952 # num instructions consuming a value
|
|
|
|
|
system.cpu.iew.wb_count 8559 # cumulative count of insts written-back
|
|
|
|
|
system.cpu.iew.wb_fanout 0.744120 # average fanout of values written-back
|
|
|
|
|
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
|
|
|
|
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
|
|
|
|
system.cpu.iew.wb_producers 4429 # num instructions producing a value
|
|
|
|
|
system.cpu.iew.wb_rate 0.346294 # insts written-back per cycle
|
|
|
|
|
system.cpu.iew.wb_sent 8658 # cumulative count of insts sent to commit
|
2011-04-04 18:42:25 +02:00
|
|
|
system.cpu.int_regfile_reads 11291 # number of integer regfile reads
|
|
|
|
|
system.cpu.int_regfile_writes 6385 # number of integer regfile writes
|
|
|
|
|
system.cpu.ipc 0.258375 # IPC: Instructions Per Cycle
|
|
|
|
|
system.cpu.ipc_total 0.258375 # IPC: Total IPC of All Threads
|
2011-04-20 03:45:23 +02:00
|
|
|
system.cpu.iq.FU_type_0::No_OpClass 2 0.02% 0.02% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::IntAlu 6174 67.79% 67.81% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::IntMult 1 0.01% 67.82% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.82% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 67.84% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.84% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.84% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.84% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.84% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.84% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.84% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.84% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.84% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.84% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.84% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.84% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.84% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.84% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.84% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.84% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.84% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.84% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.84% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.84% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.84% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.84% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.84% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.84% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.84% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.84% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::MemRead 1875 20.59% 88.43% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::MemWrite 1054 11.57% 100.00% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::total 9108 # Type of FU issued
|
2011-02-08 04:23:13 +01:00
|
|
|
system.cpu.iq.fp_alu_accesses 11 # Number of floating point alu accesses
|
|
|
|
|
system.cpu.iq.fp_inst_queue_reads 21 # Number of floating instruction queue reads
|
|
|
|
|
system.cpu.iq.fp_inst_queue_wakeup_accesses 10 # Number of floating instruction queue wakeup accesses
|
|
|
|
|
system.cpu.iq.fp_inst_queue_writes 10 # Number of floating instruction queue writes
|
2011-04-20 03:45:23 +02:00
|
|
|
system.cpu.iq.fu_busy_cnt 88 # FU busy when requested
|
|
|
|
|
system.cpu.iq.fu_busy_rate 0.009662 # FU busy rate (busy events/executed inst)
|
|
|
|
|
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::IntAlu 1 1.14% 1.14% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::IntMult 0 0.00% 1.14% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::IntDiv 0 0.00% 1.14% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::FloatAdd 0 0.00% 1.14% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::FloatCmp 0 0.00% 1.14% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::FloatCvt 0 0.00% 1.14% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::FloatMult 0 0.00% 1.14% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::FloatDiv 0 0.00% 1.14% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 1.14% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdAdd 0 0.00% 1.14% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 1.14% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdAlu 0 0.00% 1.14% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdCmp 0 0.00% 1.14% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdCvt 0 0.00% 1.14% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdMisc 0 0.00% 1.14% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdMult 0 0.00% 1.14% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 1.14% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdShift 0 0.00% 1.14% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 1.14% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 1.14% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 1.14% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.14% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 1.14% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 1.14% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 1.14% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.14% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.14% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.14% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.14% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::MemRead 52 59.09% 60.23% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::MemWrite 35 39.77% 100.00% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
2011-04-04 18:42:25 +02:00
|
|
|
system.cpu.iq.int_alu_accesses 9183 # Number of integer alu accesses
|
|
|
|
|
system.cpu.iq.int_inst_queue_reads 31223 # Number of integer instruction queue reads
|
|
|
|
|
system.cpu.iq.int_inst_queue_wakeup_accesses 8549 # Number of integer instruction queue wakeup accesses
|
|
|
|
|
system.cpu.iq.int_inst_queue_writes 14386 # Number of integer instruction queue writes
|
|
|
|
|
system.cpu.iq.iqInstsAdded 10562 # Number of instructions added to the IQ (excludes non-spec)
|
|
|
|
|
system.cpu.iq.iqInstsIssued 9108 # Number of instructions issued
|
2010-05-14 05:45:59 +02:00
|
|
|
system.cpu.iq.iqNonSpecInstsAdded 25 # Number of non-speculative instructions added to the IQ
|
2011-04-04 18:42:25 +02:00
|
|
|
system.cpu.iq.iqSquashedInstsExamined 3797 # Number of squashed instructions iterated over during squash; mainly for profiling
|
|
|
|
|
system.cpu.iq.iqSquashedInstsIssued 25 # Number of squashed instructions issued
|
2010-05-14 05:45:59 +02:00
|
|
|
system.cpu.iq.iqSquashedNonSpecRemoved 8 # Number of squashed non-spec instructions that were removed
|
2011-04-04 18:42:25 +02:00
|
|
|
system.cpu.iq.iqSquashedOperandsExamined 2286 # Number of squashed operands that are examined and possibly removed from graph
|
2011-04-20 03:45:23 +02:00
|
|
|
system.cpu.iq.issued_per_cycle::samples 12915 # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.issued_per_cycle::mean 0.705226 # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.issued_per_cycle::stdev 1.305176 # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.issued_per_cycle::0 8840 68.45% 68.45% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.issued_per_cycle::1 1652 12.79% 81.24% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.issued_per_cycle::2 1039 8.04% 89.28% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.issued_per_cycle::3 684 5.30% 94.58% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.issued_per_cycle::4 367 2.84% 97.42% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.issued_per_cycle::5 198 1.53% 98.95% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.issued_per_cycle::6 88 0.68% 99.64% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.issued_per_cycle::7 36 0.28% 99.91% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.issued_per_cycle::8 11 0.09% 100.00% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.issued_per_cycle::total 12915 # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.rate 0.368506 # Inst issue rate
|
2009-04-09 07:21:30 +02:00
|
|
|
system.cpu.itb.data_accesses 0 # DTB accesses
|
|
|
|
|
system.cpu.itb.data_acv 0 # DTB access violations
|
|
|
|
|
system.cpu.itb.data_hits 0 # DTB hits
|
|
|
|
|
system.cpu.itb.data_misses 0 # DTB misses
|
2011-04-04 18:42:25 +02:00
|
|
|
system.cpu.itb.fetch_accesses 1744 # ITB accesses
|
2009-04-09 07:21:30 +02:00
|
|
|
system.cpu.itb.fetch_acv 0 # ITB acv
|
2011-04-04 18:42:25 +02:00
|
|
|
system.cpu.itb.fetch_hits 1711 # ITB hits
|
|
|
|
|
system.cpu.itb.fetch_misses 33 # ITB misses
|
2009-04-09 07:21:30 +02:00
|
|
|
system.cpu.itb.read_accesses 0 # DTB read accesses
|
|
|
|
|
system.cpu.itb.read_acv 0 # DTB read access violations
|
|
|
|
|
system.cpu.itb.read_hits 0 # DTB read hits
|
|
|
|
|
system.cpu.itb.read_misses 0 # DTB read misses
|
|
|
|
|
system.cpu.itb.write_accesses 0 # DTB write accesses
|
|
|
|
|
system.cpu.itb.write_acv 0 # DTB write access violations
|
|
|
|
|
system.cpu.itb.write_hits 0 # DTB write hits
|
|
|
|
|
system.cpu.itb.write_misses 0 # DTB write misses
|
2008-08-04 00:13:29 +02:00
|
|
|
system.cpu.l2cache.ReadExReq_accesses 73 # number of ReadExReq accesses(hits+misses)
|
2011-04-04 18:42:25 +02:00
|
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency 34493.150685 # average ReadExReq miss latency
|
|
|
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31383.561644 # average ReadExReq mshr miss latency
|
|
|
|
|
system.cpu.l2cache.ReadExReq_miss_latency 2518000 # number of ReadExReq miss cycles
|
2007-08-04 00:04:30 +02:00
|
|
|
system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
|
2008-08-04 00:13:29 +02:00
|
|
|
system.cpu.l2cache.ReadExReq_misses 73 # number of ReadExReq misses
|
2011-04-04 18:42:25 +02:00
|
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency 2291000 # number of ReadExReq MSHR miss cycles
|
2007-08-04 00:04:30 +02:00
|
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
|
2008-08-04 00:13:29 +02:00
|
|
|
system.cpu.l2cache.ReadExReq_mshr_misses 73 # number of ReadExReq MSHR misses
|
2008-12-05 18:09:29 +01:00
|
|
|
system.cpu.l2cache.ReadReq_accesses 408 # number of ReadReq accesses(hits+misses)
|
2011-04-04 18:42:25 +02:00
|
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency 34409.090909 # average ReadReq miss latency
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31228.501229 # average ReadReq mshr miss latency
|
2007-08-27 05:27:53 +02:00
|
|
|
system.cpu.l2cache.ReadReq_hits 1 # number of ReadReq hits
|
2011-04-04 18:42:25 +02:00
|
|
|
system.cpu.l2cache.ReadReq_miss_latency 14004500 # number of ReadReq miss cycles
|
2008-12-05 18:09:29 +01:00
|
|
|
system.cpu.l2cache.ReadReq_miss_rate 0.997549 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_misses 407 # number of ReadReq misses
|
2011-04-04 18:42:25 +02:00
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency 12710000 # number of ReadReq MSHR miss cycles
|
2008-12-05 18:09:29 +01:00
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.997549 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_misses 407 # number of ReadReq MSHR misses
|
2009-04-22 19:25:17 +02:00
|
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
2010-09-09 20:40:19 +02:00
|
|
|
system.cpu.l2cache.avg_refs 0.002457 # Average number of references to valid blocks.
|
2009-04-22 19:25:17 +02:00
|
|
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
2008-12-05 18:09:29 +01:00
|
|
|
system.cpu.l2cache.demand_accesses 481 # number of demand (read+write) accesses
|
2011-04-04 18:42:25 +02:00
|
|
|
system.cpu.l2cache.demand_avg_miss_latency 34421.875000 # average overall miss latency
|
|
|
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency 31252.083333 # average overall mshr miss latency
|
2007-08-27 05:27:53 +02:00
|
|
|
system.cpu.l2cache.demand_hits 1 # number of demand (read+write) hits
|
2011-04-04 18:42:25 +02:00
|
|
|
system.cpu.l2cache.demand_miss_latency 16522500 # number of demand (read+write) miss cycles
|
2008-12-05 18:09:29 +01:00
|
|
|
system.cpu.l2cache.demand_miss_rate 0.997921 # miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.demand_misses 480 # number of demand (read+write) misses
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
2011-04-04 18:42:25 +02:00
|
|
|
system.cpu.l2cache.demand_mshr_miss_latency 15001000 # number of demand (read+write) MSHR miss cycles
|
2008-12-05 18:09:29 +01:00
|
|
|
system.cpu.l2cache.demand_mshr_miss_rate 0.997921 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.demand_mshr_misses 480 # number of demand (read+write) MSHR misses
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
|
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2011-04-04 18:42:25 +02:00
|
|
|
system.cpu.l2cache.occ_blocks::0 219.485914 # Average occupied blocks per context
|
2011-04-20 03:45:23 +02:00
|
|
|
system.cpu.l2cache.occ_percent::0 0.006698 # Average percentage of cache occupancy
|
2008-12-05 18:09:29 +01:00
|
|
|
system.cpu.l2cache.overall_accesses 481 # number of overall (read+write) accesses
|
2011-04-04 18:42:25 +02:00
|
|
|
system.cpu.l2cache.overall_avg_miss_latency 34421.875000 # average overall miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency 31252.083333 # average overall mshr miss latency
|
2009-04-22 19:25:17 +02:00
|
|
|
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
2007-08-27 05:27:53 +02:00
|
|
|
system.cpu.l2cache.overall_hits 1 # number of overall hits
|
2011-04-04 18:42:25 +02:00
|
|
|
system.cpu.l2cache.overall_miss_latency 16522500 # number of overall miss cycles
|
2008-12-05 18:09:29 +01:00
|
|
|
system.cpu.l2cache.overall_miss_rate 0.997921 # miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.overall_misses 480 # number of overall misses
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
2011-04-04 18:42:25 +02:00
|
|
|
system.cpu.l2cache.overall_mshr_miss_latency 15001000 # number of overall MSHR miss cycles
|
2008-12-05 18:09:29 +01:00
|
|
|
system.cpu.l2cache.overall_mshr_miss_rate 0.997921 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_misses 480 # number of overall MSHR misses
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
|
|
|
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
|
|
|
|
system.cpu.l2cache.replacements 0 # number of replacements
|
2010-09-09 20:40:19 +02:00
|
|
|
system.cpu.l2cache.sampled_refs 407 # Sample count of references to valid blocks.
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
2011-04-04 18:42:25 +02:00
|
|
|
system.cpu.l2cache.tagsinuse 219.485914 # Cycle average of tags in use
|
2007-08-27 05:27:53 +02:00
|
|
|
system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks.
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
|
|
|
system.cpu.l2cache.writebacks 0 # number of writebacks
|
2011-04-04 18:42:25 +02:00
|
|
|
system.cpu.memDep0.conflictingLoads 0 # Number of conflicting loads.
|
|
|
|
|
system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores.
|
|
|
|
|
system.cpu.memDep0.insertedLoads 2144 # Number of loads inserted to the mem dependence unit.
|
|
|
|
|
system.cpu.memDep0.insertedStores 1195 # Number of stores inserted to the mem dependence unit.
|
2011-02-08 04:23:13 +01:00
|
|
|
system.cpu.misc_regfile_reads 1 # number of misc regfile reads
|
|
|
|
|
system.cpu.misc_regfile_writes 1 # number of misc regfile writes
|
2011-04-04 18:42:25 +02:00
|
|
|
system.cpu.numCycles 24716 # number of cpu cycles simulated
|
2011-02-08 04:23:13 +01:00
|
|
|
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
|
|
|
|
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
2011-04-20 03:45:23 +02:00
|
|
|
system.cpu.rename.BlockCycles 337 # Number of cycles rename is blocking
|
|
|
|
|
system.cpu.rename.CommittedMaps 4583 # Number of HB maps that are committed
|
|
|
|
|
system.cpu.rename.IQFullEvents 8 # Number of times rename has blocked due to IQ full
|
|
|
|
|
system.cpu.rename.IdleCycles 8928 # Number of cycles rename is idle
|
|
|
|
|
system.cpu.rename.LSQFullEvents 260 # Number of times rename has blocked due to LSQ full
|
|
|
|
|
system.cpu.rename.RenameLookups 14615 # Number of register rename lookups that rename has made
|
|
|
|
|
system.cpu.rename.RenamedInsts 11616 # Number of instructions processed by rename
|
|
|
|
|
system.cpu.rename.RenamedOperands 8669 # Number of destination operands rename has renamed
|
|
|
|
|
system.cpu.rename.RunCycles 2118 # Number of cycles rename is running
|
|
|
|
|
system.cpu.rename.SquashCycles 825 # Number of cycles rename is squashing
|
|
|
|
|
system.cpu.rename.UnblockCycles 301 # Number of cycles rename is unblocking
|
|
|
|
|
system.cpu.rename.UndoneMaps 4086 # Number of HB maps that are undone due to squashing
|
|
|
|
|
system.cpu.rename.fp_rename_lookups 17 # Number of floating rename lookups
|
|
|
|
|
system.cpu.rename.int_rename_lookups 14598 # Number of integer rename lookups
|
|
|
|
|
system.cpu.rename.serializeStallCycles 406 # count of cycles rename stalled for serializing inst
|
|
|
|
|
system.cpu.rename.serializingInsts 28 # count of serializing insts renamed
|
|
|
|
|
system.cpu.rename.skidInsts 754 # count of insts added to the skid buffer
|
|
|
|
|
system.cpu.rename.tempSerializingInsts 22 # count of temporary serializing insts renamed
|
2011-04-04 18:42:25 +02:00
|
|
|
system.cpu.rob.rob_reads 22264 # The number of ROB reads
|
|
|
|
|
system.cpu.rob.rob_writes 22135 # The number of ROB writes
|
|
|
|
|
system.cpu.timesIdled 240 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
2011-04-20 03:45:23 +02:00
|
|
|
system.cpu.workload.num_syscalls 17 # Number of system calls
|
2006-09-01 23:59:36 +02:00
|
|
|
|
|
|
|
|
---------- End Simulation Statistics ----------
|
