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checker
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Minor remote GDB cleanup.
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2010-06-03 16:54:26 -07:00 |
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directedtest
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ruby: Resurrected Ruby's deterministic tests
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2010-08-20 11:46:13 -07:00 |
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inorder
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Inorder: Fix compilation of m5.fast.
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2010-08-14 01:00:45 -07:00 |
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memtest
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memtest: Memtester support for DMA
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2010-08-20 11:46:12 -07:00 |
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o3
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ARM: Improve printing of uop disassembly.
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2010-08-23 11:18:42 -05:00 |
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ozone
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stats: get rid of the never-really-used event stuff
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2010-06-14 23:24:46 -07:00 |
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pred
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BPRED: Fixed the treshold-bug in the tournament predictor.
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2010-05-13 23:45:57 -04:00 |
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rubytest
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ruby: Fixed minor bug in ruby test for setting the request type
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2010-08-20 11:46:14 -07:00 |
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simple
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CPU: Make Exec trace to print predication result (if false) for memory instructions
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2010-08-23 11:18:41 -05:00 |
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trace
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request: rename INST_READ to INST_FETCH.
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2009-04-20 18:54:02 -07:00 |
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activity.cc
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o3cpu: give a name to the activity recorder for better tracing
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2009-01-21 14:56:18 -08:00 |
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activity.hh
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o3cpu: give a name to the activity recorder for better tracing
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2009-01-21 14:56:18 -08:00 |
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base.cc
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commit Soumyaroop's bug catch about max_insts_all_threads
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2009-09-29 18:03:10 -04:00 |
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base.hh
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tick: rename Clock namespace to SimClock
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2010-04-15 16:24:12 -07:00 |
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base_dyn_inst.hh
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CPU: Make Exec trace to print predication result (if false) for memory instructions
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2010-08-23 11:18:41 -05:00 |
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base_dyn_inst_impl.hh
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ARM: mark msr/mrs instructions as SerializeBefore/After
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2010-08-23 11:18:41 -05:00 |
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BaseCPU.py
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ARM: Implement the ARM TLB/Tablewalker. Needs performance improvements.
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2010-06-02 12:58:16 -05:00 |
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CheckerCPU.py
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python: Move more code into m5.util allow SCons to use that code.
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2009-09-22 15:24:16 -07:00 |
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cpuevent.cc
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Change ExecContext to ThreadContext. This is being renamed to differentiate between the interface used objects outside of the CPU, and the interface used by the ISA. ThreadContext is used by objects outside of the CPU and is specifically defined in thread_context.hh. ExecContext is more implicit, and is defined by files such as base_dyn_inst.hh or cpu/simple/base.hh.
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2006-06-06 17:32:21 -04:00 |
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cpuevent.hh
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eventq: convert all usage of events to use the new API.
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2008-10-09 04:58:24 -07:00 |
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exec_context.hh
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CPU: Add readBytes and writeBytes functions to the exec contexts.
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2010-08-13 06:16:02 -07:00 |
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exetrace.cc
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CPU: Make Exec trace to print predication result (if false) for memory instructions
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2010-08-23 11:18:41 -05:00 |
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exetrace.hh
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includes: sort includes again
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2009-05-17 14:34:52 -07:00 |
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ExeTracer.py
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SimObjects: Clean up handling of C++ namespaces.
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2008-10-09 22:19:39 -07:00 |
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func_unit.cc
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params: Deprecate old-style constructors; update most SimObject constructors.
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2007-08-30 15:16:59 -04:00 |
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func_unit.hh
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params: Deprecate old-style constructors; update most SimObject constructors.
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2007-08-30 15:16:59 -04:00 |
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FuncUnit.py
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Rename enum from OpType to OpClass so it's consistent with the
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2007-06-11 23:10:58 -07:00 |
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inst_seq.hh
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build: fix compile problems pointed out by gcc 4.4
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2009-11-04 16:57:01 -08:00 |
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inteltrace.cc
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arch: nuke arch/isa_specific.hh and move stuff to generated config/the_isa.hh
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2009-09-23 08:34:21 -07:00 |
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inteltrace.hh
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includes: sort includes again
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2009-05-17 14:34:52 -07:00 |
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IntelTrace.py
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SimObjects: Clean up handling of C++ namespaces.
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2008-10-09 22:19:39 -07:00 |
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intr_control.cc
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style: Use the correct m5 style for things relating to interrupts.
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2008-10-21 07:12:53 -07:00 |
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intr_control.hh
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Interrupts: Inline some code and remove duplication.
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2007-11-08 10:46:41 -05:00 |
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IntrControl.py
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Move SimObject python files alongside the C++ and fix
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2007-05-27 19:21:17 -07:00 |
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legiontrace.cc
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build: fix compile problems pointed out by gcc 4.4
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2009-11-04 16:57:01 -08:00 |
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legiontrace.hh
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includes: sort includes again
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2009-05-17 14:34:52 -07:00 |
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LegionTrace.py
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SimObjects: Clean up handling of C++ namespaces.
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2008-10-09 22:19:39 -07:00 |
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m5legion_interface.h
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add fsr to the list of registers we are interested in
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2007-01-30 18:27:04 -05:00 |
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nativetrace.cc
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ARM: Make native trace print out what instruction caused an error.
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2009-07-27 00:54:09 -07:00 |
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nativetrace.hh
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ARM: Make native trace print out what instruction caused an error.
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2009-07-27 00:54:09 -07:00 |
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NativeTrace.py
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ARM: Make native trace print out what instruction caused an error.
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2009-07-27 00:54:09 -07:00 |
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op_class.hh
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Major changes to how SimObjects are created and initialized. Almost all
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2007-07-23 21:51:38 -07:00 |
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pc_event.cc
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debug: Move debug_break into src/base
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2009-02-23 11:48:40 -08:00 |
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pc_event.hh
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types: Move stuff for global types into src/base/types.hh
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2009-05-17 14:34:50 -07:00 |
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profile.cc
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Change ExecContext to ThreadContext. This is being renamed to differentiate between the interface used objects outside of the CPU, and the interface used by the ISA. ThreadContext is used by objects outside of the CPU and is specifically defined in thread_context.hh. ExecContext is more implicit, and is defined by files such as base_dyn_inst.hh or cpu/simple/base.hh.
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2006-06-06 17:32:21 -04:00 |
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profile.hh
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arch: nuke arch/isa_specific.hh and move stuff to generated config/the_isa.hh
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2009-09-23 08:34:21 -07:00 |
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quiesce_event.cc
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eventq: convert all usage of events to use the new API.
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2008-10-09 04:58:24 -07:00 |
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quiesce_event.hh
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Make the Event::description() a const function
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2008-02-06 16:32:40 -05:00 |
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SConscript
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cpu_models: get rid of cpu_models.py and move the stuff into SCons
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2010-02-26 18:14:48 -08:00 |
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simple_thread.cc
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ISA: Fix compilation.
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2009-10-17 01:13:41 -07:00 |
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simple_thread.hh
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CPU: Print out flatten-out register index as with IntRegs/FloatRegs traceflag
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2010-08-23 11:18:41 -05:00 |
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smt.hh
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types: add a type for thread IDs and try to use it everywhere
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2009-05-26 09:23:13 -07:00 |
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static_inst.cc
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inorder-tlb-cunit: merge the TLB as implicit to any memory access
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2009-05-12 15:01:16 -04:00 |
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static_inst.hh
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arch: nuke arch/isa_specific.hh and move stuff to generated config/the_isa.hh
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2009-09-23 08:34:21 -07:00 |
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thread_context.cc
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arch: nuke arch/isa_specific.hh and move stuff to generated config/the_isa.hh
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2009-09-23 08:34:21 -07:00 |
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thread_context.hh
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ARM/O3: store the result of the predicate evaluation in DynInst or Threadstate.
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2010-08-23 11:18:40 -05:00 |
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thread_state.cc
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Get rid of the unused get(Data|Inst)Asid and (inst|data)Asid functions.
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2009-07-08 23:02:22 -07:00 |
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thread_state.hh
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arch: nuke arch/isa_specific.hh and move stuff to generated config/the_isa.hh
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2009-09-23 08:34:21 -07:00 |
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translation.hh
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CPU: Added comments to address translation classes.
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2010-03-25 12:43:52 +00:00 |
