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gem5/src/sim
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Andreas Sandberg d4342aff4c stats: Silence unused power stats 
The power stats are currently very noisy even if no power model has
been loaded. Silence stats that are either zero or nan.

Change-Id: I7d0220c2fcf01131084a219228f140cfaddaf95b
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
2016-06-06 17:16:43 +01:00
..
power stats: Fixing regStats function for some SimObjects 2016-06-06 17:16:43 +01:00
probe mem: Add Program Counter to MemTraceProbe 2016-04-07 11:32:38 -05:00
arguments.cc GetArgument: Rework getArgument so that X86_FS compiles again. 2010-10-15 23:57:06 -07:00
arguments.hh dev: Use shared_ptr for Arguments::Data 2014-10-16 05:49:45 -04:00
async.cc base: Fix race in PollQueue and remove SIGALRM workaround 2013-11-29 14:36:10 +01:00
async.hh base: Fix race in PollQueue and remove SIGALRM workaround 2013-11-29 14:36:10 +01:00
backtrace.hh sim: Add support for generating back traces on errors 2015-12-04 00:12:58 +00:00
backtrace_glibc.cc style: fix missing spaces in control statements 2016-02-06 17:21:19 -08:00
backtrace_none.cc sim: Add support for generating back traces on errors 2015-12-04 00:12:58 +00:00
byteswap.hh base: Redesign internal frame buffer handling 2015-05-23 13:37:03 +01:00
clock_domain.cc stats: Fixing regStats function for some SimObjects 2016-06-06 17:16:43 +01:00
clock_domain.hh sim: Fix clock_domain unserialization 2016-04-01 16:22:44 +01:00
ClockDomain.py power: Add basic DVFS support for gem5 2014-06-30 13:56:06 -04:00
clocked_object.cc stats: Silence unused power stats 2016-06-06 17:16:43 +01:00
clocked_object.hh pwr: Add power states to ClockedObject 2016-06-06 17:16:43 +01:00
ClockedObject.py pwr: Add power states to ClockedObject 2016-06-06 17:16:43 +01:00
core.cc sim: simulate with multiple threads and event queues 2013-11-25 11:21:00 -06:00
core.hh sim: simulate with multiple threads and event queues 2013-11-25 11:21:00 -06:00
cxx_config.cc config: Add the ability to read a config file using C++ and Python 2014-10-16 05:49:37 -04:00
cxx_config.hh config: Add the ability to read a config file using C++ and Python 2014-10-16 05:49:37 -04:00
cxx_config_ini.cc config: Add the ability to read a config file using C++ and Python 2014-10-16 05:49:37 -04:00
cxx_config_ini.hh config: Add the ability to read a config file using C++ and Python 2014-10-16 05:49:37 -04:00
cxx_manager.cc sim: Decouple draining from the SimObject hierarchy 2015-07-07 09:51:05 +01:00
cxx_manager.hh sim: Decouple draining from the SimObject hierarchy 2015-07-07 09:51:05 +01:00
debug.cc sim: Add relative break scheduling 2015-10-09 14:27:09 -05:00
debug.hh sim: Add relative break scheduling 2015-10-09 14:27:09 -05:00
drain.cc sim: Add additional debug information when draining 2015-12-11 17:29:53 +00:00
drain.hh sim: Add support for notifying Drainable objects of a fork 2015-11-26 10:03:43 +00:00
dvfs_handler.cc style: fix missing spaces in control statements 2016-02-06 17:21:19 -08:00
dvfs_handler.hh misc: Remove redundant compiler-specific defines 2015-10-12 04:07:59 -04:00
DVFSHandler.py power: Add basic DVFS support for gem5 2014-06-30 13:56:06 -04:00
emul_driver.hh syscall_emul: add EmulatedDriver object 2014-10-22 15:53:34 -07:00
eventq.cc style: remove trailing whitespace 2016-02-06 17:21:18 -08:00
eventq.hh style: remove trailing whitespace 2016-02-06 17:21:18 -08:00
eventq_impl.hh sim: simulate with multiple threads and event queues 2013-11-25 11:21:00 -06:00
faults.cc cpu: Remove all notion that we know when the cpu is misspeculating. 2015-01-25 07:22:26 -05:00
faults.hh arch: Use shared_ptr for all Faults 2014-10-16 05:49:51 -04:00
fd_entry.cc base: refactor process class (specifically FdMap and friends) 2015-07-24 12:25:22 -07:00
fd_entry.hh misc: Remove redundant compiler-specific defines 2015-10-12 04:07:59 -04:00
full_system.hh clang: Fix recently introduced clang compilation errors 2012-03-19 06:35:04 -04:00
global_event.cc sim: Fix resource leak in BaseGlobalEvent 2014-09-09 04:36:32 -04:00
global_event.hh dev: Distributed Ethernet link for distributed gem5 simulations 2016-01-07 16:33:47 -06:00
init.cc config: Add a --without-python option to build process 2014-10-16 05:49:32 -04:00
init.hh config: Add a --without-python option to build process 2014-10-16 05:49:32 -04:00
init_signals.cc sim: don't ignore SIG_TRAP 2016-01-17 18:27:46 -08:00
init_signals.hh config: Add a --without-python option to build process 2014-10-16 05:49:32 -04:00
initparam_keys.hh dev: Distributed Ethernet link for distributed gem5 simulations 2016-01-07 16:33:47 -06:00
insttracer.hh style: remove trailing whitespace 2016-02-06 17:21:18 -08:00
InstTracer.py sim: Include object header files in SWIG interfaces 2012-11-02 11:32:01 -05:00
linear_solver.cc sim: Adding thermal model support 2015-05-12 10:26:47 +01:00
linear_solver.hh sim: Adding thermal model support 2015-05-12 10:26:47 +01:00
main.cc config: Add a --without-python option to build process 2014-10-16 05:49:32 -04:00
microcode_rom.hh CPU: Create a microcode ROM object in the CPU which is defined by the ISA. 2008-10-12 15:59:21 -07:00
process.cc sim: Call regStats of base-class as well 2016-06-06 17:16:43 +01:00
process.hh base: add symbol support for dynamic libraries 2016-03-17 10:34:27 -07:00
Process.py mem: Page Table map api modification 2014-11-23 18:01:09 -08:00
process_impl.hh MEM: Make port proxies use references rather than pointers 2012-02-24 11:45:30 -05:00
pseudo_inst.cc base: Add support for changing output directories 2015-11-27 14:41:59 +00:00
pseudo_inst.hh pseudo inst,util: Add optional key to initparam pseudo instruction 2016-01-07 16:33:47 -06:00
py_interact.cc config: Add a --without-python option to build process 2014-10-16 05:49:32 -04:00
py_interact.hh config: Add a --without-python option to build process 2014-10-16 05:49:32 -04:00
root.cc sim: tag-based checkpoint versioning 2015-09-02 15:23:30 -05:00
root.hh misc: Add explicit overrides and fix other clang >= 3.5 issues 2015-10-12 04:08:01 -04:00
Root.py style: remove trailing whitespace 2016-02-06 17:21:18 -08:00
SConscript pwr: Add power states to ClockedObject 2016-06-06 17:16:43 +01:00
serialize.cc sim: Get rid of the non-const serialize() method 2015-12-04 09:48:48 +00:00
serialize.hh style: fix missing spaces in control statements 2016-02-06 17:21:19 -08:00
sim_events.cc sim: Remove autoserialize support for exit events 2015-09-01 13:41:45 +01:00
sim_events.hh scons: Enable -Wextra by default 2016-01-11 05:52:20 -05:00
sim_exit.hh sim: simulate with multiple threads and event queues 2013-11-25 11:21:00 -06:00
sim_object.cc sim: Get rid of the non-const serialize() method 2015-12-04 09:48:48 +00:00
sim_object.hh misc: Remove redundant compiler-specific defines 2015-10-12 04:07:59 -04:00
simulate.cc sim: Update limit_event reuse to final version 2015-03-26 11:16:44 -04:00
simulate.hh sim: Update limit_event reuse to final version 2015-03-26 11:16:44 -04:00
stat_control.cc style: Fix line continuation, especially in debug messages 2014-09-12 10:22:47 -04:00
stat_control.hh scons: Add warning for missing declarations 2013-02-19 05:56:07 -05:00
stat_register.cc config: Add a --without-python option to build process 2014-10-16 05:49:32 -04:00
stat_register.hh config: Add a --without-python option to build process 2014-10-16 05:49:32 -04:00
stats.hh stats: make simTicks and simFreq accessible from stats.hh 2010-04-18 13:23:25 -07:00
sub_system.cc Revert power patch sets with unexpected interactions 2016-04-06 19:43:31 +01:00
sub_system.hh Revert power patch sets with unexpected interactions 2016-04-06 19:43:31 +01:00
SubSystem.py sim: Adding thermal model support 2015-05-12 10:26:47 +01:00
syscall_emul.cc syscall_emul: extend mmap system call to support file backed mmaps 2016-03-17 10:24:17 -07:00
syscall_emul.hh base: add symbol support for dynamic libraries 2016-03-17 10:34:27 -07:00
syscall_emul_buf.hh syscall_emul: devirtualize BaseBufferArg methods 2014-10-22 15:53:34 -07:00
syscallreturn.hh syscall_emul: add retry flag to SyscallReturn 2014-09-02 16:07:50 -05:00
system.cc sim: Call regStats of base-class as well 2016-06-06 17:16:43 +01:00
system.hh sim: Adding thermal model support 2015-05-12 10:26:47 +01:00
System.py sim: Adding thermal model support 2015-05-12 10:26:47 +01:00
ticked_object.cc sim: Refactor the serialization base class 2015-07-07 09:51:03 +01:00
ticked_object.hh misc: Add explicit overrides and fix other clang >= 3.5 issues 2015-10-12 04:08:01 -04:00
TickedObject.py cpu: `Minor' in-order CPU model 2014-07-23 16:09:04 -05:00
voltage_domain.cc stats: Fixing regStats function for some SimObjects 2016-06-06 17:16:43 +01:00
voltage_domain.hh misc: Add explicit overrides and fix other clang >= 3.5 issues 2015-10-12 04:08:01 -04:00
VoltageDomain.py power: Add basic DVFS support for gem5 2014-06-30 13:56:06 -04:00
vptr.hh MEM: Make port proxies use references rather than pointers 2012-02-24 11:45:30 -05:00