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style: Fix line continuation, especially in debug messages

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This patch closes a number of space gaps in debug messages caused by
the incorrect use of line continuation within strings. (There's also
one consistency change to a similar, but correct, use of line
continuation)
This commit is contained in:
Andrew Bardsley 2014-09-12 10:22:47 -04:00
parent 2b4906fc64
commit c8b919aba2
8 changed files with 23 additions and 22 deletions
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4
src/arch/arm/faults.cc
View file

@ -1120,8 +1120,8 @@ DataAbort::ec(ThreadContext *tc) const
if (to64) {
// AArch64
if (source == ArmFault::AsynchronousExternalAbort) {
panic("Asynchronous External Abort should be handled with \
SystemErrors (SErrors)!");
panic("Asynchronous External Abort should be handled with "
"SystemErrors (SErrors)!");
}
if (toEL == fromEL)
return EC_DATA_ABORT_CURR_EL;

4
src/arch/arm/table_walker.cc
View file

@ -1116,8 +1116,8 @@ TableWalker::memAttrs(ThreadContext *tc, TlbEntry &te, SCTLR sctlr,
}
}
}
DPRINTF(TLBVerbose, "memAttrs: shareable: %d, innerAttrs: %d, \
outerAttrs: %d\n",
DPRINTF(TLBVerbose, "memAttrs: shareable: %d, innerAttrs: %d, "
"outerAttrs: %d\n",
te.shareable, te.innerAttrs, te.outerAttrs);
te.setAttributes(false);
}

10
src/arch/arm/tlb.cc
View file

@ -163,7 +163,7 @@ TLB::lookup(Addr va, uint16_t asn, uint8_t vmid, bool hyp, bool secure,
retval ? retval->pAddr(va) : 0, retval ? retval->ap : 0,
retval ? retval->ns : 0, retval ? retval->nstid : 0,
retval ? retval->global : 0, retval ? retval->asid : 0,
retval ? retval->el : 0, retval ? retval->el : 0);
retval ? retval->el : 0);
return retval;
}
@ -1027,8 +1027,8 @@ TLB::translateFs(RequestPtr req, ThreadContext *tc, Mode mode,
temp_te.outerShareable = false;
}
temp_te.setAttributes(long_desc_format);
DPRINTF(TLBVerbose, "(No MMU) setting memory attributes: shareable:\
%d, innerAttrs: %d, outerAttrs: %d, isStage2: %d\n",
DPRINTF(TLBVerbose, "(No MMU) setting memory attributes: shareable: "
"%d, innerAttrs: %d, outerAttrs: %d, isStage2: %d\n",
temp_te.shareable, temp_te.innerAttrs, temp_te.outerAttrs,
isStage2);
setAttr(temp_te.attributes);
@ -1052,8 +1052,8 @@ TLB::translateFs(RequestPtr req, ThreadContext *tc, Mode mode,
if (te != NULL) {
// Set memory attributes
DPRINTF(TLBVerbose,
"Setting memory attributes: shareable: %d, innerAttrs: %d, \
outerAttrs: %d, mtype: %d, isStage2: %d\n",
"Setting memory attributes: shareable: %d, innerAttrs: %d, "
"outerAttrs: %d, mtype: %d, isStage2: %d\n",
te->shareable, te->innerAttrs, te->outerAttrs,
static_cast<uint8_t>(te->mtype), isStage2);
setAttr(te->attributes);

4
src/cpu/checker/cpu.cc
View file

@ -306,8 +306,8 @@ CheckerCPU::writeMem(uint8_t *data, unsigned size,
if (unverifiedReq && unverifiedMemData &&
memcmp(data, unverifiedMemData, fullSize) && extraData) {
warn("%lli: Store value does not match value sent to memory!\
data: %#x inst_data: %#x", curTick(), data,
warn("%lli: Store value does not match value sent to memory! "
"data: %#x inst_data: %#x", curTick(), data,
unverifiedMemData);
handleError();
}

8
src/dev/arm/pl111.cc
View file

@ -196,8 +196,8 @@ Pl111::read(PacketPtr pkt)
data = lcdPalette[index];
break;
} else {
panic("Tried to read CLCD register at offset %#x that \
doesn't exist\n", daddr);
panic("Tried to read CLCD register at offset %#x that "
"doesn't exist\n", daddr);
break;
}
}
@ -369,8 +369,8 @@ Pl111::write(PacketPtr pkt)
lcdPalette[index] = data;
break;
} else {
panic("Tried to write PL111 register at offset %#x that \
doesn't exist\n", daddr);
panic("Tried to write PL111 register at offset %#x that "
"doesn't exist\n", daddr);
break;
}
}

4
src/dev/ns_gige.cc
View file

@ -732,8 +732,8 @@ NSGigE::write(PacketPtr pkt)
= (uint8_t)(reg >> 8);
break;
}
panic("writing RFDR for something other than pattern matching\
or hashing! %#x\n", rfaddr);
panic("writing RFDR for something other than pattern matching "
"or hashing! %#x\n", rfaddr);
}
case BRAR:

4
src/sim/stat_control.cc
View file

@ -157,8 +157,8 @@ Global::Global()
finalTick
.functor(statFinalTick)
.name("final_tick")
.desc("Number of ticks from beginning of simulation \
(restored from checkpoints and never reset)")
.desc("Number of ticks from beginning of simulation "
"(restored from checkpoints and never reset)")
;
hostInstRate

7
src/sim/system.cc
View file

@ -450,9 +450,10 @@ System::getMasterId(std::string master_name)
// Otherwise objects will have sized their stat buckets and
// they will be too small
if (Stats::enabled())
fatal("Can't request a masterId after regStats(). \
You must do so in init().\n");
if (Stats::enabled()) {
fatal("Can't request a masterId after regStats(). "
"You must do so in init().\n");
}
masterIds.push_back(master_name);