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cache
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mem: Print an MSHR without triggering any assertions
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2016-08-15 12:00:36 +01:00 |
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probes
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stats: Fixing regStats function for some SimObjects
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2016-06-06 17:16:43 +01:00 |
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protocol
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ruby: rename ALPHA_Network_test protocol to Garnet_standalone.
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2016-10-06 14:35:14 -04:00 |
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ruby
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ruby: remove the original garnet code.
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2016-10-06 14:35:21 -04:00 |
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slicc
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style: eliminate explicit boolean comparisons
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2016-02-06 17:21:20 -08:00 |
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abstract_mem.cc
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mem: minor dprintf fix to abstract mem
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2016-09-29 01:06:33 -04:00 |
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abstract_mem.hh
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cpu, mem, sim: Change how KVM maps memory
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2016-08-22 11:41:05 -04:00 |
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AbstractMemory.py
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cpu, mem, sim: Change how KVM maps memory
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2016-08-22 11:41:05 -04:00 |
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addr_mapper.cc
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mem: Make cache terminology easier to understand
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2015-12-31 09:32:58 -05:00 |
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addr_mapper.hh
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mem: Split port retry for all different packet classes
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2015-03-02 04:00:35 -05:00 |
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AddrMapper.py
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sim: Include object header files in SWIG interfaces
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2012-11-02 11:32:01 -05:00 |
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bridge.cc
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mem: Move the point of coherency to the coherent crossbar
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2016-02-10 04:08:25 -05:00 |
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bridge.hh
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mem: Align rules for sinking inhibited packets at the slave
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2015-11-06 03:26:35 -05:00 |
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Bridge.py
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mem: Tidy up the bridge with const and additional checks
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2013-06-27 05:49:49 -04:00 |
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coherent_xbar.cc
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mem: Add support for secure packets in the snoop filter
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2016-08-12 14:11:45 +01:00 |
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coherent_xbar.hh
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mem: Add snoop traffic statistic
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2016-07-21 17:19:14 +01:00 |
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comm_monitor.cc
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sim: Call regStats of base-class as well
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2016-06-06 17:16:43 +01:00 |
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comm_monitor.hh
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mem: Pass snoop retries through the CommMonitor
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2015-10-14 13:32:28 -04:00 |
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CommMonitor.py
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mem: Move trace functionality from the CommMonitor to a probe
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2015-08-04 10:29:13 +01:00 |
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dram_ctrl.cc
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mem: Move the point of coherency to the coherent crossbar
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2016-02-10 04:08:25 -05:00 |
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dram_ctrl.hh
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ext: Update DRAMPower
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2016-07-01 10:31:36 -05:00 |
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DRAMCtrl.py
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mem: hmc: minor fixes
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2015-11-03 12:17:58 -06:00 |
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drampower.cc
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mem: Fix search-replace issues in DRAMPower wrapper license
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2015-11-25 13:52:56 -05:00 |
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drampower.hh
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mem: Fix search-replace issues in DRAMPower wrapper license
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2015-11-25 13:52:56 -05:00 |
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dramsim2.cc
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mem: Make cache terminology easier to understand
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2015-12-31 09:32:58 -05:00 |
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dramsim2.hh
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mem: Unify delayed packet deletion
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2015-11-06 03:26:21 -05:00 |
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DRAMSim2.py
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mem: Add a wrapped DRAMSim2 memory controller
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2014-02-18 05:50:53 -05:00 |
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dramsim2_wrapper.cc
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mem: Add a wrapped DRAMSim2 memory controller
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2014-02-18 05:50:53 -05:00 |
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dramsim2_wrapper.hh
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mem: Add a wrapped DRAMSim2 memory controller
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2014-02-18 05:50:53 -05:00 |
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external_master.cc
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mem: Add ExternalMaster and ExternalSlave ports
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2014-10-16 05:49:56 -04:00 |
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external_master.hh
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mem: Add ExternalMaster and ExternalSlave ports
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2014-10-16 05:49:56 -04:00 |
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external_slave.cc
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mem: Split port retry for all different packet classes
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2015-03-02 04:00:35 -05:00 |
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external_slave.hh
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mem: Add ExternalMaster and ExternalSlave ports
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2014-10-16 05:49:56 -04:00 |
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ExternalMaster.py
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mem: Add ExternalMaster and ExternalSlave ports
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2014-10-16 05:49:56 -04:00 |
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ExternalSlave.py
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mem: Add ExternalMaster and ExternalSlave ports
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2014-10-16 05:49:56 -04:00 |
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fs_translating_port_proxy.cc
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mem: Use const pointers for port proxy write functions
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2014-12-02 06:07:38 -05:00 |
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fs_translating_port_proxy.hh
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mem: Use const pointers for port proxy write functions
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2014-12-02 06:07:38 -05:00 |
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hmc_controller.cc
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mem: Make cache terminology easier to understand
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2015-12-31 09:32:58 -05:00 |
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hmc_controller.hh
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mem: hmc: adds controller
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2015-11-03 12:17:56 -06:00 |
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HMCController.py
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mem: hmc: adds controller
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2015-11-03 12:17:56 -06:00 |
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mem_checker.cc
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mem: Fix initial value problem with MemChecker
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2015-02-16 03:34:47 -05:00 |
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mem_checker.hh
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misc: Remove redundant compiler-specific defines
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2015-10-12 04:07:59 -04:00 |
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mem_checker_monitor.cc
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mem: Fix MemChecker unique_ptr type mismatch
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2016-05-26 11:56:24 +01:00 |
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mem_checker_monitor.hh
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mem: Split port retry for all different packet classes
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2015-03-02 04:00:35 -05:00 |
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mem_object.cc
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Port: Add protocol-agnostic ports in the port hierarchy
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2012-10-15 08:12:35 -04:00 |
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mem_object.hh
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Port: Add protocol-agnostic ports in the port hierarchy
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2012-10-15 08:12:35 -04:00 |
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MemChecker.py
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mem: Add MemChecker and MemCheckerMonitor
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2014-12-23 09:31:17 -05:00 |
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MemObject.py
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sim: Include object header files in SWIG interfaces
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2012-11-02 11:32:01 -05:00 |
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mport.cc
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MEM: Separate snoops and normal memory requests/responses
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2012-04-14 05:45:07 -04:00 |
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mport.hh
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style: remove trailing whitespace
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2016-02-06 17:21:18 -08:00 |
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multi_level_page_table.cc
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mem: adding a multi-level page table class
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2014-04-01 12:18:12 -05:00 |
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multi_level_page_table.hh
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x86: Add missing explicit overrides for X86 devices
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2015-10-23 09:51:12 -04:00 |
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multi_level_page_table_impl.hh
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sim: Refactor the serialization base class
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2015-07-07 09:51:03 +01:00 |
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noncoherent_xbar.cc
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mem: Make cache terminology easier to understand
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2015-12-31 09:32:58 -05:00 |
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noncoherent_xbar.hh
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sim: Decouple draining from the SimObject hierarchy
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2015-07-07 09:51:05 +01:00 |
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packet.cc
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mem: Add a FromCache packet attribute
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2016-08-12 14:11:45 +01:00 |
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packet.hh
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mem: Add a FromCache packet attribute
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2016-08-12 14:11:45 +01:00 |
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packet_access.hh
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mem: fix bug in packet access endianness changes
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2016-01-11 16:20:38 -05:00 |
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packet_queue.cc
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mem: Order packet queue only on matching addresses
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2015-11-06 03:26:38 -05:00 |
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packet_queue.hh
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mem: Order packet queue only on matching addresses
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2015-11-06 03:26:38 -05:00 |
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page_table.cc
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sim: Refactor the serialization base class
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2015-07-07 09:51:03 +01:00 |
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page_table.hh
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scons: Enable -Wextra by default
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2016-01-11 05:52:20 -05:00 |
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physical.cc
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cpu, mem, sim: Change how KVM maps memory
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2016-08-22 11:41:05 -04:00 |
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physical.hh
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cpu, mem, sim: Change how KVM maps memory
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2016-08-22 11:41:05 -04:00 |
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port.cc
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style: fix missing spaces in control statements
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2016-02-06 17:21:19 -08:00 |
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port.hh
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mem: Split port retry for all different packet classes
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2015-03-02 04:00:35 -05:00 |
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port_proxy.cc
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mem: Clean up Request initialisation
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2015-01-22 05:00:53 -05:00 |
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port_proxy.hh
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mem: Use const pointers for port proxy write functions
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2014-12-02 06:07:38 -05:00 |
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qport.hh
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mem: Enforce insertion order on the cache response path
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2015-11-06 03:26:37 -05:00 |
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request.hh
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mem: Remove threadId from memory request class
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2016-04-07 09:30:20 -05:00 |
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SConscript
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mem: hmc: serial link model
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2015-11-03 12:17:57 -06:00 |
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se_translating_port_proxy.cc
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mem: Use const pointers for port proxy write functions
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2014-12-02 06:07:38 -05:00 |
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se_translating_port_proxy.hh
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mem: Use const pointers for port proxy write functions
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2014-12-02 06:07:38 -05:00 |
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serial_link.cc
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mem: different HMC configuration
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2016-07-01 09:45:21 -05:00 |
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serial_link.hh
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mem: different HMC configuration
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2016-07-01 09:45:21 -05:00 |
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SerialLink.py
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mem: different HMC configuration
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2016-07-01 09:45:21 -05:00 |
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simple_mem.cc
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mem: Move the point of coherency to the coherent crossbar
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2016-02-10 04:08:25 -05:00 |
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simple_mem.hh
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mem: Use the packet delays and do not just zero them out
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2015-11-06 03:26:36 -05:00 |
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SimpleMemory.py
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mem: Add an internal packet queue in SimpleMemory
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2013-08-19 03:52:25 -04:00 |
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snoop_filter.cc
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mem: Add support for secure packets in the snoop filter
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2016-08-12 14:11:45 +01:00 |
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snoop_filter.hh
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mem: Add support for secure packets in the snoop filter
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2016-08-12 14:11:45 +01:00 |
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stack_dist_calc.cc
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style: fix missing spaces in control statements
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2016-02-06 17:21:19 -08:00 |
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stack_dist_calc.hh
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mem: Redesign the stack distance calculator as a probe
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2015-08-04 10:29:13 +01:00 |
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tport.cc
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mem: Make cache terminology easier to understand
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2015-12-31 09:32:58 -05:00 |
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tport.hh
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mem: Unify delayed packet deletion
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2015-11-06 03:26:21 -05:00 |
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xbar.cc
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sim: Call regStats of base-class as well
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2016-06-06 17:16:43 +01:00 |
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xbar.hh
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mem: hmc: minor fixes
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2015-11-03 12:17:58 -06:00 |
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XBar.py
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mem: Add snoop filter to SystemXBar by default
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2016-08-12 14:11:45 +01:00 |
