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gem5/src/cpu
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Steve Reinhardt a13a706a20 Fix setting of INST_FETCH flag for O3 CPU. 
It's still broken in inorder.
Also enhance DPRINTFs in cache and physical memory so we
can see more easily whether it's getting set or not.
2009-08-01 22:50:14 -07:00
..
checker Get rid of the unused get(Data|Inst)Asid and (inst|data)Asid functions. 2009-07-08 23:02:22 -07:00
inorder Get rid of the unused get(Data|Inst)Asid and (inst|data)Asid functions. 2009-07-08 23:02:22 -07:00
memtest types: clean up types, especially signed vs unsigned 2009-06-04 23:21:12 -07:00
o3 Fix setting of INST_FETCH flag for O3 CPU. 2009-08-01 22:50:14 -07:00
ozone Fix setting of INST_FETCH flag for O3 CPU. 2009-08-01 22:50:14 -07:00
pred types: clean up types, especially signed vs unsigned 2009-06-04 23:21:12 -07:00
simple Fix setting of INST_FETCH flag for O3 CPU. 2009-08-01 22:50:14 -07:00
trace request: rename INST_READ to INST_FETCH. 2009-04-20 18:54:02 -07:00
activity.cc o3cpu: give a name to the activity recorder for better tracing 2009-01-21 14:56:18 -08:00
activity.hh o3cpu: give a name to the activity recorder for better tracing 2009-01-21 14:56:18 -08:00
base.cc types: add a type for thread IDs and try to use it everywhere 2009-05-26 09:23:13 -07:00
base.hh types: add a type for thread IDs and try to use it everywhere 2009-05-26 09:23:13 -07:00
base_dyn_inst.hh Fix setting of INST_FETCH flag for O3 CPU. 2009-08-01 22:50:14 -07:00
base_dyn_inst_impl.hh O3CPU: Make the instcount debugging stuff per-cpu. 2008-11-10 11:51:18 -08:00
BaseCPU.py arm: Unify the ARM tlb. We forgot about this when we did the rest. 2009-04-21 15:40:25 -07:00
CheckerCPU.py Changed BaseCPU::ProfileEvent's interval member to be of type Tick. This was done to be consistent with its 2008-08-18 10:50:58 -07:00
cpu_models.py InOrder: Import new inorder CPU model from MIPS. 2009-02-10 15:49:29 -08:00
cpuevent.cc Change ExecContext to ThreadContext. This is being renamed to differentiate between the interface used objects outside of the CPU, and the interface used by the ISA. ThreadContext is used by objects outside of the CPU and is specifically defined in thread_context.hh. ExecContext is more implicit, and is defined by files such as base_dyn_inst.hh or cpu/simple/base.hh. 2006-06-06 17:32:21 -04:00
cpuevent.hh eventq: convert all usage of events to use the new API. 2008-10-09 04:58:24 -07:00
exec_context.hh Registers: Get rid of the float register width parameter. 2009-07-08 23:02:20 -07:00
exetrace.cc CPU: Only look up the nearest symbol in the kernel if you're actually in kernel code. 2009-02-25 10:22:36 -08:00
exetrace.hh includes: sort includes again 2009-05-17 14:34:52 -07:00
ExeTracer.py SimObjects: Clean up handling of C++ namespaces. 2008-10-09 22:19:39 -07:00
func_unit.cc params: Deprecate old-style constructors; update most SimObject constructors. 2007-08-30 15:16:59 -04:00
func_unit.hh params: Deprecate old-style constructors; update most SimObject constructors. 2007-08-30 15:16:59 -04:00
FuncUnit.py Rename enum from OpType to OpClass so it's consistent with the 2007-06-11 23:10:58 -07:00
inst_seq.hh fixes so that M5 will compile under solaris 2006-11-04 21:41:01 -05:00
inteltrace.cc params: Deprecate old-style constructors; update most SimObject constructors. 2007-08-30 15:16:59 -04:00
inteltrace.hh includes: sort includes again 2009-05-17 14:34:52 -07:00
IntelTrace.py SimObjects: Clean up handling of C++ namespaces. 2008-10-09 22:19:39 -07:00
intr_control.cc style: Use the correct m5 style for things relating to interrupts. 2008-10-21 07:12:53 -07:00
intr_control.hh Interrupts: Inline some code and remove duplication. 2007-11-08 10:46:41 -05:00
IntrControl.py Move SimObject python files alongside the C++ and fix 2007-05-27 19:21:17 -07:00
legiontrace.cc Registers: Add a registers.hh file as an ISA switched header. 2009-07-08 23:02:21 -07:00
legiontrace.hh includes: sort includes again 2009-05-17 14:34:52 -07:00
LegionTrace.py SimObjects: Clean up handling of C++ namespaces. 2008-10-09 22:19:39 -07:00
m5legion_interface.h add fsr to the list of registers we are interested in 2007-01-30 18:27:04 -05:00
nativetrace.cc ARM: Make native trace print out what instruction caused an error. 2009-07-27 00:54:09 -07:00
nativetrace.hh ARM: Make native trace print out what instruction caused an error. 2009-07-27 00:54:09 -07:00
NativeTrace.py ARM: Make native trace print out what instruction caused an error. 2009-07-27 00:54:09 -07:00
op_class.hh Major changes to how SimObjects are created and initialized. Almost all 2007-07-23 21:51:38 -07:00
pc_event.cc debug: Move debug_break into src/base 2009-02-23 11:48:40 -08:00
pc_event.hh types: Move stuff for global types into src/base/types.hh 2009-05-17 14:34:50 -07:00
profile.cc Change ExecContext to ThreadContext. This is being renamed to differentiate between the interface used objects outside of the CPU, and the interface used by the ISA. ThreadContext is used by objects outside of the CPU and is specifically defined in thread_context.hh. ExecContext is more implicit, and is defined by files such as base_dyn_inst.hh or cpu/simple/base.hh. 2006-06-06 17:32:21 -04:00
profile.hh types: Move stuff for global types into src/base/types.hh 2009-05-17 14:34:50 -07:00
quiesce_event.cc eventq: convert all usage of events to use the new API. 2008-10-09 04:58:24 -07:00
quiesce_event.hh Make the Event::description() a const function 2008-02-06 16:32:40 -05:00
SConscript CPU: Separate out native trace into ISA (in)dependent code and SimObjects. 2009-07-19 23:54:56 -07:00
simple_thread.cc Get rid of the unused get(Data|Inst)Asid and (inst|data)Asid functions. 2009-07-08 23:02:22 -07:00
simple_thread.hh Simple CPU: Make the simple CPU handle the IntRegs trace flag. 2009-07-29 00:15:26 -07:00
smt.hh types: add a type for thread IDs and try to use it everywhere 2009-05-26 09:23:13 -07:00
static_inst.cc inorder-tlb-cunit: merge the TLB as implicit to any memory access 2009-05-12 15:01:16 -04:00
static_inst.hh includes: sort includes again 2009-05-17 14:34:52 -07:00
thread_context.cc Add in Context IDs to the simulator. From now on, cpuId is almost never used, 2008-11-02 21:57:07 -05:00
thread_context.hh Registers: Add a registers.hh file as an ISA switched header. 2009-07-08 23:02:21 -07:00
thread_state.cc Get rid of the unused get(Data|Inst)Asid and (inst|data)Asid functions. 2009-07-08 23:02:22 -07:00
thread_state.hh Get rid of the unused get(Data|Inst)Asid and (inst|data)Asid functions. 2009-07-08 23:02:22 -07:00