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resources
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Registers: Get rid of the float register width parameter.
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2009-07-08 23:02:20 -07:00 |
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comm.hh
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includes: sort includes again
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2009-05-17 14:34:52 -07:00 |
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cpu.cc
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Get rid of the unused get(Data|Inst)Asid and (inst|data)Asid functions.
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2009-07-08 23:02:22 -07:00 |
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cpu.hh
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Get rid of the unused get(Data|Inst)Asid and (inst|data)Asid functions.
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2009-07-08 23:02:22 -07:00 |
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first_stage.cc
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types: add a type for thread IDs and try to use it everywhere
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2009-05-26 09:23:13 -07:00 |
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first_stage.hh
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types: add a type for thread IDs and try to use it everywhere
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2009-05-26 09:23:13 -07:00 |
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inorder_cpu_builder.cc
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types: add a type for thread IDs and try to use it everywhere
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2009-05-26 09:23:13 -07:00 |
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inorder_dyn_inst.cc
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Registers: Get rid of the float register width parameter.
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2009-07-08 23:02:20 -07:00 |
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inorder_dyn_inst.hh
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Registers: Get rid of the float register width parameter.
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2009-07-08 23:02:20 -07:00 |
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inorder_trace.cc
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InOrder: Import new inorder CPU model from MIPS.
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2009-02-10 15:49:29 -08:00 |
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inorder_trace.hh
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includes: sort includes again
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2009-05-17 14:34:52 -07:00 |
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InOrderCPU.py
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InOrder didnt have all it's params set to a default value, which is now required for M5 objects; Also, a # of values need to be reset to 0 (or the appropriate value) before we assume they are OK for use.
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2009-03-04 13:17:05 -05:00 |
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InOrderTrace.py
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InOrder: Import new inorder CPU model from MIPS.
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2009-02-10 15:49:29 -08:00 |
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params.hh
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Remove unused functions/comments cluttering up the code.
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2009-03-04 13:17:08 -05:00 |
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pipeline_stage.cc
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types: add a type for thread IDs and try to use it everywhere
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2009-05-26 09:23:13 -07:00 |
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pipeline_stage.hh
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types: add a type for thread IDs and try to use it everywhere
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2009-05-26 09:23:13 -07:00 |
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pipeline_traits.5stage.cc
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InOrder: Import new inorder CPU model from MIPS.
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2009-02-10 15:49:29 -08:00 |
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pipeline_traits.5stage.hh
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InOrder: Import new inorder CPU model from MIPS.
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2009-02-10 15:49:29 -08:00 |
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pipeline_traits.9stage.cc
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InOrder: Import new inorder CPU model from MIPS.
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2009-02-10 15:49:29 -08:00 |
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pipeline_traits.9stage.hh
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InOrder: Import new inorder CPU model from MIPS.
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2009-02-10 15:49:29 -08:00 |
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pipeline_traits.9stage.smt2.cc
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InOrder: Import new inorder CPU model from MIPS.
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2009-02-10 15:49:29 -08:00 |
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pipeline_traits.9stage.smt2.hh
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InOrder: Import new inorder CPU model from MIPS.
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2009-02-10 15:49:29 -08:00 |
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pipeline_traits.cc
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inorder-tlb-cunit: merge the TLB as implicit to any memory access
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2009-05-12 15:01:16 -04:00 |
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pipeline_traits.hh
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types: clean up types, especially signed vs unsigned
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2009-06-04 23:21:12 -07:00 |
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reg_dep_map.cc
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InOrder: Import new inorder CPU model from MIPS.
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2009-02-10 15:49:29 -08:00 |
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reg_dep_map.hh
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InOrder: Import new inorder CPU model from MIPS.
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2009-02-10 15:49:29 -08:00 |
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resource.cc
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types: add a type for thread IDs and try to use it everywhere
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2009-05-26 09:23:13 -07:00 |
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resource.hh
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types: add a type for thread IDs and try to use it everywhere
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2009-05-26 09:23:13 -07:00 |
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resource_pool.9stage.cc
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types: add a type for thread IDs and try to use it everywhere
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2009-05-26 09:23:13 -07:00 |
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resource_pool.cc
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types: add a type for thread IDs and try to use it everywhere
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2009-05-26 09:23:13 -07:00 |
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resource_pool.hh
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types: add a type for thread IDs and try to use it everywhere
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2009-05-26 09:23:13 -07:00 |
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SConscript
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inorder-tlb-cunit: merge the TLB as implicit to any memory access
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2009-05-12 15:01:16 -04:00 |
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SConsopts
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cpus: add InOrderCPU to default build
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2009-05-12 20:55:21 -04:00 |
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thread_context.cc
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Registers: Get rid of the float register width parameter.
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2009-07-08 23:02:20 -07:00 |
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thread_context.hh
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Registers: Get rid of the float register width parameter.
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2009-07-08 23:02:20 -07:00 |
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thread_state.hh
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Get rid of the unused get(Data|Inst)Asid and (inst|data)Asid functions.
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2009-07-08 23:02:22 -07:00 |
