.. |
checker
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base: Declare a type for context IDs
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2015-08-07 09:59:13 +01:00 |
kvm
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sim: Refactor and simplify the drain API
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2015-07-07 09:51:05 +01:00 |
minor
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mem: Reflect that packet address and size are always valid
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2015-08-21 07:03:27 -04:00 |
nocpu
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arch, cpu: Factor out the ExecContext into a proper base class
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2014-09-03 07:42:22 -04:00 |
o3
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base: Declare a type for context IDs
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2015-08-07 09:59:13 +01:00 |
pred
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cpu: re-organizes the branch predictor structure.
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2015-04-13 17:33:57 -05:00 |
simple
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revert 5af8f40d8f2c
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2015-07-28 01:58:04 -05:00 |
testers
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ruby: eliminate type uint64 and int64
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2015-08-29 10:19:23 -05:00 |
activity.cc
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Fix: Address a few benign memory leaks
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2012-07-09 12:35:30 -04:00 |
activity.hh
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cpu: Useful getters for ActivityRecorder
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2014-05-09 18:58:48 -04:00 |
base.cc
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cpu: Move invldPid constant from Request to BaseCPU
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2015-08-21 07:03:14 -04:00 |
base.hh
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cpu: Move invldPid constant from Request to BaseCPU
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2015-08-21 07:03:14 -04:00 |
base_dyn_inst.hh
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base: Declare a type for context IDs
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2015-08-07 09:59:13 +01:00 |
base_dyn_inst_impl.hh
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arch: Use const StaticInstPtr references where possible
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2014-09-27 09:08:36 -04:00 |
BaseCPU.py
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mem: Move crossbar default latencies to subclasses
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2015-03-02 04:00:47 -05:00 |
CheckerCPU.py
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sim: Include object header files in SWIG interfaces
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2012-11-02 11:32:01 -05:00 |
cpuevent.cc
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cpuevent.hh
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includes: sort all includes
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2011-04-15 10:44:06 -07:00 |
CPUTracers.py
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cpu: Put all CPU instruction tracers in a single file
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2015-01-25 07:22:17 -05:00 |
decode_cache.hh
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ISA,CPU: Generalize and split out the components of the decode cache.
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2012-05-26 13:45:12 -07:00 |
dummy_checker.cc
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sim: Add the notion of clock domains to all ClockedObjects
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2013-06-27 05:49:49 -04:00 |
dummy_checker.hh
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cpu: Add header files for checker CPUs
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2012-11-02 11:32:01 -05:00 |
DummyChecker.py
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cpu: Make checker CPUs inherit from CheckerCPU in the Python hierarchy
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2013-02-15 17:40:08 -05:00 |
exec_context.cc
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arch, cpu: Factor out the ExecContext into a proper base class
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2014-09-03 07:42:22 -04:00 |
exec_context.hh
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revert 5af8f40d8f2c
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2015-07-28 01:58:04 -05:00 |
exetrace.cc
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sim: Clean up InstRecord
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2015-01-25 07:22:44 -05:00 |
exetrace.hh
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cpu: Remove all notion that we know when the cpu is misspeculating.
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2015-01-25 07:22:26 -05:00 |
func_unit.cc
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cpu: Fix issue identified by UBSan
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2015-07-30 03:41:22 -04:00 |
func_unit.hh
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cpu: Fix issue identified by UBSan
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2015-07-30 03:41:22 -04:00 |
FuncUnit.py
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cpu: o3: replace issueLatency with bool pipelined
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2015-04-29 22:35:22 -05:00 |
inst_pb_trace.cc
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cpu: add support for outputing a protobuf formatted CPU trace
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2015-02-16 03:32:38 -05:00 |
inst_pb_trace.hh
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cpu: Fix InstPBTrace inheritance
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2015-03-26 11:16:43 -04:00 |
inst_seq.hh
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build: fix compile problems pointed out by gcc 4.4
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2009-11-04 16:57:01 -08:00 |
InstPBTrace.py
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cpu: add support for outputing a protobuf formatted CPU trace
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2015-02-16 03:32:38 -05:00 |
inteltrace.cc
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gcc: Clean-up of non-C++0x compliant code, first steps
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2012-03-19 06:36:09 -04:00 |
inteltrace.hh
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cpu: Remove all notion that we know when the cpu is misspeculating.
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2015-01-25 07:22:26 -05:00 |
intr_control.cc
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SE/FS: Get rid of FULL_SYSTEM in the CPU directory.
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2011-11-18 01:33:28 -08:00 |
intr_control.hh
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arch: Header clean up for NOISA resurrection
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2013-09-04 13:22:55 -04:00 |
intr_control_noisa.cc
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arch: Resurrect the NOISA build target and rename it NULL
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2013-09-04 13:22:57 -04:00 |
IntrControl.py
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sim: Include object header files in SWIG interfaces
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2012-11-02 11:32:01 -05:00 |
nativetrace.cc
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trace: reimplement the DTRACE function so it doesn't use a vector
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2011-04-15 10:44:32 -07:00 |
nativetrace.hh
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cpu: Remove all notion that we know when the cpu is misspeculating.
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2015-01-25 07:22:26 -05:00 |
op_class.hh
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cpu: Work around gcc 4.9 issues with Num_OpClasses
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2015-05-05 03:22:19 -04:00 |
pc_event.cc
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arm: Enable support for triggering a sim panic on kernel panics
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2013-04-22 13:20:31 -04:00 |
pc_event.hh
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arm: Enable support for triggering a sim panic on kernel panics
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2013-04-22 13:20:31 -04:00 |
profile.cc
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includes: sort all includes
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2011-04-15 10:44:06 -07:00 |
profile.hh
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arch: Use const StaticInstPtr references where possible
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2014-09-27 09:08:36 -04:00 |
quiesce_event.cc
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trace: reimplement the DTRACE function so it doesn't use a vector
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2011-04-15 10:44:32 -07:00 |
quiesce_event.hh
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clang: Enable compiling gem5 using clang 2.9 and 3.0
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2012-01-31 12:05:52 -05:00 |
reg_class.cc
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revert 5af8f40d8f2c
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2015-07-28 01:58:04 -05:00 |
reg_class.hh
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revert 5af8f40d8f2c
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2015-07-28 01:58:04 -05:00 |
SConscript
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cpu: add support for outputing a protobuf formatted CPU trace
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2015-02-16 03:32:38 -05:00 |
simple_thread.cc
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sim: Refactor the serialization base class
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2015-07-07 09:51:03 +01:00 |
simple_thread.hh
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revert 5af8f40d8f2c
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2015-07-28 01:58:04 -05:00 |
smt.hh
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includes: fix up code after sorting
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2011-04-15 10:44:14 -07:00 |
static_inst.cc
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cpu: Add flag name printing to StaticInst
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2014-05-09 18:58:47 -04:00 |
static_inst.hh
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revert 5af8f40d8f2c
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2015-07-28 01:58:04 -05:00 |
static_inst_fwd.hh
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cpu: Don't forward declare RefCountingPtr
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2014-08-13 06:57:26 -04:00 |
StaticInstFlags.py
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revert 5af8f40d8f2c
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2015-07-28 01:58:04 -05:00 |
thread_context.cc
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base: Declare a type for context IDs
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2015-08-07 09:59:13 +01:00 |
thread_context.hh
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revert 5af8f40d8f2c
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2015-07-28 01:58:04 -05:00 |
thread_state.cc
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sim: Refactor the serialization base class
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2015-07-07 09:51:03 +01:00 |
thread_state.hh
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base: Declare a type for context IDs
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2015-08-07 09:59:13 +01:00 |
timebuf.hh
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cpu: Timebuf const accessors
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2014-05-09 18:58:47 -04:00 |
timing_expr.cc
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arch: Use const StaticInstPtr references where possible
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2014-09-27 09:08:36 -04:00 |
timing_expr.hh
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arch: Use const StaticInstPtr references where possible
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2014-09-27 09:08:36 -04:00 |
TimingExpr.py
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cpu: `Minor' in-order CPU model
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2014-07-23 16:09:04 -05:00 |
translation.hh
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mem, cpu: Add a separate flag for strictly ordered memory
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2015-05-05 03:22:33 -04:00 |