gem5/src/arch/arm
Nathanael Premillieu bfffbb6797 ARM: Inst writing to cntrlReg registers not set as control inst
Deletion of the fact that instructions that writes to registers of type
"cntrlReg" are not set as control instruction (flag IsControl not set).
2012-09-25 11:49:40 -05:00
..
insts ARM: Predict target of more instructions that modify PC. 2012-09-25 11:49:40 -05:00
isa ARM: Inst writing to cntrlReg registers not set as control inst 2012-09-25 11:49:40 -05:00
linux syscall emulation: Enabled getrlimit and getrusage for x86. 2012-08-06 19:52:56 -07:00
ArmInterrupts.py ARM: Boilerplate full-system code. 2009-11-17 18:02:08 -06:00
ArmNativeTrace.py ARM: Make the ARM native tracer stop M5 if control diverges. 2009-07-29 00:17:11 -07:00
ArmSystem.py ARM: Fix MPIDR and MIDR register implementation. 2012-06-05 01:23:10 -04:00
ArmTLB.py Packet: Remove NACKs from packet and its use in endpoints 2012-08-22 11:39:59 -04:00
decoder.cc ISA,CPU: Generalize and split out the components of the decode cache. 2012-05-26 13:45:12 -07:00
decoder.hh ISA,CPU: Generalize and split out the components of the decode cache. 2012-05-26 13:45:12 -07:00
faults.cc Implement Ali's review feedback. 2012-01-29 02:04:34 -08:00
faults.hh SE/FS: Get rid of FULL_SYSTEM in the ARM ISA. 2011-11-02 01:25:15 -07:00
interrupts.cc ARM: Implement ARM CPU interrupts 2010-06-02 12:58:16 -05:00
interrupts.hh Fix bugs due to interaction between SEV instructions and O3 pipeline 2011-08-19 15:08:07 -05:00
intregs.hh gcc: Clean-up of non-C++0x compliant code, first steps 2012-03-19 06:36:09 -04:00
isa.cc ARM: fix value of MISCREG_CTR returned by readMiscReg() 2012-07-27 16:08:04 -04:00
isa.hh trace: reimplement the DTRACE function so it doesn't use a vector 2011-04-15 10:44:32 -07:00
isa_traits.hh ISA: Back-out NoopMachInst as a StaticInstPtr change. 2012-06-05 13:52:30 -04:00
kernel_stats.hh Make commenting on close namespace brackets consistent. 2011-01-03 14:35:43 -08:00
locked_mem.hh includes: sort all includes 2011-04-15 10:44:06 -07:00
microcode_rom.hh arm: include missing file for arm 2009-04-21 15:40:26 -07:00
miscregs.cc gem5: Fix a number of incorrect case statements 2012-05-10 18:04:26 -05:00
miscregs.hh ARM: fix value of MISCREG_CTR returned by readMiscReg() 2012-07-27 16:08:04 -04:00
mmapped_ipr.hh Clock: Add a Cycles wrapper class and use where applicable 2012-08-28 14:30:33 -04:00
nativetrace.cc gcc: Clean-up of non-C++0x compliant code, first steps 2012-03-19 06:36:09 -04:00
nativetrace.hh ARM: Add vfpv3 support to native trace. 2011-05-04 20:38:26 -05:00
pagetable.hh gcc: Clean-up of non-C++0x compliant code, first steps 2012-03-19 06:36:09 -04:00
process.cc MEM: Make port proxies use references rather than pointers 2012-02-24 11:45:30 -05:00
process.hh includes: sort all includes 2011-04-15 10:44:06 -07:00
registers.hh O3: Clean up the O3 structures and try to pack them a bit better. 2012-06-05 01:23:09 -04:00
remote_gdb.cc Decode: Make the Decoder class defined per ISA. 2012-05-25 00:53:37 -07:00
remote_gdb.hh MEM: Enable multiple distributed generalized memories 2012-04-06 13:46:31 -04:00
SConscript ISA: Back-out NoopMachInst as a StaticInstPtr change. 2012-06-05 13:52:30 -04:00
SConsopts arm: add ARM support to M5 2009-04-05 18:53:15 -07:00
stacktrace.cc ARM: implement the ProcessInfo methods 2012-06-11 11:07:41 -04:00
stacktrace.hh trace: reimplement the DTRACE function so it doesn't use a vector 2011-04-15 10:44:32 -07:00
system.cc ARM: Fix MPIDR and MIDR register implementation. 2012-06-05 01:23:10 -04:00
system.hh ARM: Fix MPIDR and MIDR register implementation. 2012-06-05 01:23:10 -04:00
table_walker.cc Clock: Add a Cycles wrapper class and use where applicable 2012-08-28 14:30:33 -04:00
table_walker.hh Packet: Remove NACKs from packet and its use in endpoints 2012-08-22 11:39:59 -04:00
tlb.cc MEM: Introduce the master/slave port sub-classes in C++ 2012-03-30 09:40:11 -04:00
tlb.hh MEM: Introduce the master/slave port sub-classes in C++ 2012-03-30 09:40:11 -04:00
types.hh ARM: Fix issue with predicted next pc being wrong because of advance() ordering. 2012-06-29 11:18:28 -04:00
utility.cc cpu: Don't init simple and inorder CPUs if they are defered. 2012-06-05 14:20:13 -04:00
utility.hh Clock: Add a Cycles wrapper class and use where applicable 2012-08-28 14:30:33 -04:00
vtophys.cc MEM: Make port proxies use references rather than pointers 2012-02-24 11:45:30 -05:00
vtophys.hh gcc: Clean-up of non-C++0x compliant code, first steps 2012-03-19 06:36:09 -04:00