gem5/src/arch/arm/isa
Nathanael Premillieu bfffbb6797 ARM: Inst writing to cntrlReg registers not set as control inst
Deletion of the fact that instructions that writes to registers of type
"cntrlReg" are not set as control instruction (flag IsControl not set).
2012-09-25 11:49:40 -05:00
..
decoder ARM: Add limited CP14 support. 2012-03-01 17:26:31 -06:00
formats ARM: Clean up condCodes in IT blocks. 2012-03-21 10:34:06 -05:00
insts ARM: Predict target of more instructions that modify PC. 2012-09-25 11:49:40 -05:00
templates ARM: Predict target of more instructions that modify PC. 2012-09-25 11:49:40 -05:00
bitfields.isa ARM: Rearrange the load/store double/exclusive, table branch thumb decoding. 2010-06-02 12:58:07 -05:00
copyright.txt ARM: Remove IsControl from operands that don't imply control transfers. 2010-06-02 12:57:59 -05:00
includes.isa ISA: Make the decode function part of the ISA's decoder. 2012-05-25 00:55:24 -07:00
main.isa ARM: Define the load instructions from outside the decoder. 2010-06-02 12:58:01 -05:00
operands.isa ARM: Inst writing to cntrlReg registers not set as control inst 2012-09-25 11:49:40 -05:00