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checker
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mem: Refactor assignment of Packet types
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2014-05-13 12:20:48 -05:00 |
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inorder
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mem: Refactor assignment of Packet types
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2014-05-13 12:20:48 -05:00 |
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kvm
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kvm, x86: Add initial support for multicore simulation
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2014-04-09 16:01:58 +02:00 |
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minor
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arch, cpu: Factor out the ExecContext into a proper base class
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2014-09-03 07:42:22 -04:00 |
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nocpu
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arch, cpu: Factor out the ExecContext into a proper base class
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2014-09-03 07:42:22 -04:00 |
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o3
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mem: Refactor assignment of Packet types
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2014-05-13 12:20:48 -05:00 |
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ozone
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mem: Refactor assignment of Packet types
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2014-05-13 12:20:48 -05:00 |
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pred
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cpu: fix bimodal predictor to use correct global history reg
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2014-09-03 07:42:41 -04:00 |
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simple
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mem: Refactor assignment of Packet types
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2014-05-13 12:20:48 -05:00 |
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testers
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mem: change the namespace Message to ProtoMessage
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2014-09-01 16:55:46 -05:00 |
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activity.cc
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Fix: Address a few benign memory leaks
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2012-07-09 12:35:30 -04:00 |
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activity.hh
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cpu: Useful getters for ActivityRecorder
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2014-05-09 18:58:48 -04:00 |
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base.cc
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arch, arm: Preserve TLB bootUncacheability when switching CPUs
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2014-05-09 18:58:47 -04:00 |
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base.hh
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cpu, arm: Allow the specification of a socket field
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2014-05-09 18:58:46 -04:00 |
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base_dyn_inst.hh
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arch, cpu: Factor out the ExecContext into a proper base class
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2014-09-03 07:42:22 -04:00 |
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base_dyn_inst_impl.hh
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cpu: Add support for instructions that zero cache lines.
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2014-01-24 15:29:30 -06:00 |
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BaseCPU.py
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cpu, arm: Allow the specification of a socket field
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2014-05-09 18:58:46 -04:00 |
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CheckerCPU.py
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sim: Include object header files in SWIG interfaces
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2012-11-02 11:32:01 -05:00 |
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cpuevent.cc
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cpuevent.hh
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includes: sort all includes
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2011-04-15 10:44:06 -07:00 |
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decode_cache.hh
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ISA,CPU: Generalize and split out the components of the decode cache.
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2012-05-26 13:45:12 -07:00 |
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dummy_checker.cc
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sim: Add the notion of clock domains to all ClockedObjects
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2013-06-27 05:49:49 -04:00 |
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dummy_checker.hh
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cpu: Add header files for checker CPUs
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2012-11-02 11:32:01 -05:00 |
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DummyChecker.py
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cpu: Make checker CPUs inherit from CheckerCPU in the Python hierarchy
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2013-02-15 17:40:08 -05:00 |
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exec_context.cc
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arch, cpu: Factor out the ExecContext into a proper base class
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2014-09-03 07:42:22 -04:00 |
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exec_context.hh
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arch, cpu: Factor out the ExecContext into a proper base class
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2014-09-03 07:42:22 -04:00 |
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exetrace.cc
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style: eliminate equality tests with true and false
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2014-05-31 18:00:23 -07:00 |
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exetrace.hh
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trace: reimplement the DTRACE function so it doesn't use a vector
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2011-04-15 10:44:32 -07:00 |
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ExeTracer.py
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sim: Include object header files in SWIG interfaces
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2012-11-02 11:32:01 -05:00 |
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func_unit.cc
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params: Deprecate old-style constructors; update most SimObject constructors.
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2007-08-30 15:16:59 -04:00 |
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func_unit.hh
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Param: Transition to Cycles for relevant parameters
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2012-09-07 12:34:38 -04:00 |
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FuncUnit.py
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sim: Include object header files in SWIG interfaces
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2012-11-02 11:32:01 -05:00 |
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inst_seq.hh
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build: fix compile problems pointed out by gcc 4.4
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2009-11-04 16:57:01 -08:00 |
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inteltrace.cc
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gcc: Clean-up of non-C++0x compliant code, first steps
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2012-03-19 06:36:09 -04:00 |
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inteltrace.hh
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sim: Include object header files in SWIG interfaces
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2012-11-02 11:32:01 -05:00 |
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IntelTrace.py
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sim: Include object header files in SWIG interfaces
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2012-11-02 11:32:01 -05:00 |
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intr_control.cc
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SE/FS: Get rid of FULL_SYSTEM in the CPU directory.
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2011-11-18 01:33:28 -08:00 |
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intr_control.hh
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arch: Header clean up for NOISA resurrection
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2013-09-04 13:22:55 -04:00 |
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intr_control_noisa.cc
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arch: Resurrect the NOISA build target and rename it NULL
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2013-09-04 13:22:57 -04:00 |
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IntrControl.py
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sim: Include object header files in SWIG interfaces
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2012-11-02 11:32:01 -05:00 |
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legiontrace.cc
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Decoder: Remove the thread context get/set from the decoder.
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2013-01-04 19:00:45 -06:00 |
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legiontrace.hh
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scons: Add warning for missing declarations
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2013-02-19 05:56:07 -05:00 |
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LegionTrace.py
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sim: Include object header files in SWIG interfaces
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2012-11-02 11:32:01 -05:00 |
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m5legion_interface.h
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add fsr to the list of registers we are interested in
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2007-01-30 18:27:04 -05:00 |
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nativetrace.cc
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trace: reimplement the DTRACE function so it doesn't use a vector
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2011-04-15 10:44:32 -07:00 |
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nativetrace.hh
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clang: Enable compiling gem5 using clang 2.9 and 3.0
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2012-01-31 12:05:52 -05:00 |
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NativeTrace.py
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sim: Include object header files in SWIG interfaces
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2012-11-02 11:32:01 -05:00 |
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op_class.hh
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CPU/ARM: Add SIMD op classes to CPU models and ARM ISA.
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2010-11-15 14:04:04 -06:00 |
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pc_event.cc
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arm: Enable support for triggering a sim panic on kernel panics
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2013-04-22 13:20:31 -04:00 |
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pc_event.hh
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arm: Enable support for triggering a sim panic on kernel panics
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2013-04-22 13:20:31 -04:00 |
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profile.cc
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includes: sort all includes
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2011-04-15 10:44:06 -07:00 |
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profile.hh
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includes: sort all includes
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2011-04-15 10:44:06 -07:00 |
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quiesce_event.cc
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trace: reimplement the DTRACE function so it doesn't use a vector
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2011-04-15 10:44:32 -07:00 |
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quiesce_event.hh
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clang: Enable compiling gem5 using clang 2.9 and 3.0
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2012-01-31 12:05:52 -05:00 |
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reg_class.cc
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cpu: add a condition-code register class
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2013-10-15 14:22:44 -04:00 |
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reg_class.hh
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cpu: add a condition-code register class
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2013-10-15 14:22:44 -04:00 |
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SConscript
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arch, cpu: Factor out the ExecContext into a proper base class
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2014-09-03 07:42:22 -04:00 |
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simple_thread.cc
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arch, cpu: Factor out the ExecContext into a proper base class
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2014-09-03 07:42:22 -04:00 |
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simple_thread.hh
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arm: use condition code registers for ARM ISA
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2014-04-29 16:05:02 -05:00 |
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smt.hh
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includes: fix up code after sorting
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2011-04-15 10:44:14 -07:00 |
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static_inst.cc
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cpu: Add flag name printing to StaticInst
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2014-05-09 18:58:47 -04:00 |
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static_inst.hh
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arch, cpu: Factor out the ExecContext into a proper base class
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2014-09-03 07:42:22 -04:00 |
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static_inst_fwd.hh
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cpu: Don't forward declare RefCountingPtr
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2014-08-13 06:57:26 -04:00 |
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StaticInstFlags.py
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cpu: Add flag name printing to StaticInst
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2014-05-09 18:58:47 -04:00 |
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thread_context.cc
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cpu: add a condition-code register class
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2013-10-15 14:22:44 -04:00 |
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thread_context.hh
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cpu, arm: Allow the specification of a socket field
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2014-05-09 18:58:46 -04:00 |
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thread_state.cc
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mem: Set the cache line size on a system level
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2013-07-18 08:31:16 -04:00 |
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thread_state.hh
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cpu, arm: Allow the specification of a socket field
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2014-05-09 18:58:46 -04:00 |
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timebuf.hh
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cpu: Timebuf const accessors
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2014-05-09 18:58:47 -04:00 |
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timing_expr.cc
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cpu: `Minor' in-order CPU model
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2014-07-23 16:09:04 -05:00 |
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timing_expr.hh
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cpu: `Minor' in-order CPU model
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2014-07-23 16:09:04 -05:00 |
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TimingExpr.py
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cpu: `Minor' in-order CPU model
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2014-07-23 16:09:04 -05:00 |
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translation.hh
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cpu: Fix setTranslateLatency() bug for squashed instructions
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2014-04-23 05:18:26 -04:00 |
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