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mem: Refactor assignment of Packet types

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Put the packet type swizzling (that is currently done in a lot of places)
into a refineCommand() member function.
This commit is contained in:
Curtis Dunham 2014-05-13 12:20:48 -05:00
parent afbae1ec95
commit e3b19cb294
9 changed files with 54 additions and 52 deletions
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5
src/cpu/checker/cpu.cc
View file

@ -170,10 +170,7 @@ CheckerCPU::readMem(Addr addr, uint8_t *data, unsigned size, unsigned flags)
// Now do the access
if (fault == NoFault &&
!memReq->getFlags().isSet(Request::NO_ACCESS)) {
PacketPtr pkt = new Packet(memReq,
memReq->isLLSC() ?
MemCmd::LoadLockedReq :
MemCmd::ReadReq);
PacketPtr pkt = Packet::createRead(memReq);
pkt->dataStatic(data);

14
src/cpu/inorder/resources/cache_unit.cc
View file

@ -812,21 +812,11 @@ CacheUnit::finishCacheUnitReq(DynInstPtr inst, CacheRequest *cache_req)
void
CacheUnit::buildDataPacket(CacheRequest *cache_req)
{
// Check for LL/SC and if so change command
if (cache_req->memReq->isLLSC() && cache_req->pktCmd == MemCmd::ReadReq) {
cache_req->pktCmd = MemCmd::LoadLockedReq;
}
if (cache_req->pktCmd == MemCmd::WriteReq) {
cache_req->pktCmd =
cache_req->memReq->isSwap() ? MemCmd::SwapReq :
(cache_req->memReq->isLLSC() ? MemCmd::StoreCondReq
: MemCmd::WriteReq);
}
cache_req->dataPkt = new CacheReqPacket(cache_req,
cache_req->pktCmd,
cache_req->instIdx);
cache_req->dataPkt->refineCommand(); // handle LL/SC, etc.
DPRINTF(InOrderCachePort, "[slot:%i]: Slot marked for %x\n",
cache_req->getSlot(),
cache_req->dataPkt->getAddr());

7
src/cpu/o3/lsq_unit.hh
View file

@ -776,8 +776,7 @@ LSQUnit<Impl>::read(Request *req, Request *sreqLow, Request *sreqHigh,
// if we the cache is not blocked, do cache access
bool completedFirst = false;
MemCmd command = req->isLLSC() ? MemCmd::LoadLockedReq : MemCmd::ReadReq;
PacketPtr data_pkt = new Packet(req, command);
PacketPtr data_pkt = Packet::createRead(req);
PacketPtr fst_data_pkt = NULL;
PacketPtr snd_data_pkt = NULL;
@ -794,8 +793,8 @@ LSQUnit<Impl>::read(Request *req, Request *sreqLow, Request *sreqHigh,
fst_data_pkt = data_pkt;
} else {
// Create the split packets.
fst_data_pkt = new Packet(sreqLow, command);
snd_data_pkt = new Packet(sreqHigh, command);
fst_data_pkt = Packet::createRead(sreqLow);
snd_data_pkt = Packet::createRead(sreqHigh);
fst_data_pkt->dataStatic(load_inst->memData);
snd_data_pkt->dataStatic(load_inst->memData + sreqLow->getSize());

9
src/cpu/o3/lsq_unit_impl.hh
View file

@ -839,9 +839,6 @@ LSQUnit<Impl>::writebackStores()
else
memcpy(inst->memData, storeQueue[storeWBIdx].data, req->getSize());
MemCmd command =
req->isSwap() ? MemCmd::SwapReq :
(req->isLLSC() ? MemCmd::StoreCondReq : MemCmd::WriteReq);
PacketPtr data_pkt;
PacketPtr snd_data_pkt = NULL;
@ -853,13 +850,13 @@ LSQUnit<Impl>::writebackStores()
if (!TheISA::HasUnalignedMemAcc || !storeQueue[storeWBIdx].isSplit) {
// Build a single data packet if the store isn't split.
data_pkt = new Packet(req, command);
data_pkt = Packet::createWrite(req);
data_pkt->dataStatic(inst->memData);
data_pkt->senderState = state;
} else {
// Create two packets if the store is split in two.
data_pkt = new Packet(sreqLow, command);
snd_data_pkt = new Packet(sreqHigh, command);
data_pkt = Packet::createWrite(sreqLow);
snd_data_pkt = Packet::createWrite(sreqHigh);
data_pkt->dataStatic(inst->memData);
snd_data_pkt->dataStatic(inst->memData + sreqLow->getSize());

5
src/cpu/ozone/lw_lsq.hh
View file

@ -631,10 +631,7 @@ OzoneLWLSQ<Impl>::read(RequestPtr req, T &data, int load_idx)
DPRINTF(OzoneLSQ, "Doing timing access for inst PC %#x\n",
inst->readPC());
PacketPtr data_pkt =
new Packet(req,
(req->isLLSC() ?
MemCmd::LoadLockedReq : Packet::ReadReq));
PacketPtr data_pkt = Packet::createRead(req);
data_pkt->dataStatic(inst->memData);
LSQSenderState *state = new LSQSenderState;

5
src/cpu/ozone/lw_lsq_impl.hh
View file

@ -577,10 +577,7 @@ OzoneLWLSQ<Impl>::writebackStores()
memcpy(inst->memData, (uint8_t *)&(*sq_it).data,
req->getSize());
MemCmd command =
req->isSwap() ? MemCmd::SwapReq :
(req->isLLSC() ? MemCmd::WriteReq : MemCmd::StoreCondReq);
PacketPtr data_pkt = new Packet(req, command);
PacketPtr data_pkt = Packet::createWrite(req);
data_pkt->dataStatic(inst->memData);
LSQSenderState *state = new LSQSenderState;

5
src/cpu/simple/atomic.cc
View file

@ -340,9 +340,8 @@ AtomicSimpleCPU::readMem(Addr addr, uint8_t * data,
// Now do the access.
if (fault == NoFault && !req->getFlags().isSet(Request::NO_ACCESS)) {
Packet pkt = Packet(req,
req->isLLSC() ? MemCmd::LoadLockedReq :
MemCmd::ReadReq);
Packet pkt(req, MemCmd::ReadReq);
pkt.refineCommand();
pkt.dataStatic(data);
if (req->isMmappedIpr())

15
src/cpu/simple/timing.cc
View file

@ -349,20 +349,7 @@ TimingSimpleCPU::translationFault(Fault fault)
void
TimingSimpleCPU::buildPacket(PacketPtr &pkt, RequestPtr req, bool read)
{
MemCmd cmd;
if (read) {
cmd = MemCmd::ReadReq;
if (req->isLLSC())
cmd = MemCmd::LoadLockedReq;
} else {
cmd = MemCmd::WriteReq;
if (req->isLLSC()) {
cmd = MemCmd::StoreCondReq;
} else if (req->isSwap()) {
cmd = MemCmd::SwapReq;
}
}
pkt = new Packet(req, cmd);
pkt = read ? Packet::createRead(req) : Packet::createWrite(req);
}
void

41
src/mem/packet.hh
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2012-2013 ARM Limited
* Copyright (c) 2012-2014 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@ -666,7 +666,46 @@ class Packet : public Printable
flags.set(pkt->flags & (VALID_ADDR|VALID_SIZE));
flags.set(pkt->flags & STATIC_DATA);
}
/**
* Change the packet type based on request type.
*/
void
refineCommand()
{
if (cmd == MemCmd::ReadReq) {
if (req->isLLSC()) {
cmd = MemCmd::LoadLockedReq;
}
} else if (cmd == MemCmd::WriteReq) {
if (req->isLLSC()) {
cmd = MemCmd::StoreCondReq;
} else if (req->isSwap()) {
cmd = MemCmd::SwapReq;
}
}
}
/**
* Constructor-like methods that return Packets based on Request objects.
* Will call refineCommand() to fine-tune the Packet type if it's not a
* vanilla read or write.
*/
static PacketPtr
createRead(Request *req)
{
PacketPtr pkt = new Packet(req, MemCmd::ReadReq);
pkt->refineCommand();
return pkt;
}
static PacketPtr
createWrite(Request *req)
{
PacketPtr pkt = new Packet(req, MemCmd::WriteReq);
pkt->refineCommand();
return pkt;
}
/**