Commit graph

284 commits

Author SHA1 Message Date
Nathan Binkert
39a055645f includes: sort all includes 2011-04-15 10:44:06 -07:00
Ali Saidi
a432d8e085 Mem: Fix issue with dirty block being lost when entire block transferred to non-cache.
This change fixes the problem for all the cases we actively use. If you want to try
more creative I/O device attachments (E.g. sharing an L2), this won't work. You
would need another level of caching between the I/O device and the cache
(which you actually need anyway with our current code to make sure writes
propagate). This is required so that you can mark the cache in between as
top level and it won't try to send ownership of a block to the I/O device.
Asserts have been added that should catch any issues.
2011-03-17 19:20:19 -05:00
Ali Saidi
f05f35df99 Includes: Don't include isa_traits.hh and use the TheISA namespace unless really needed. 2011-02-23 15:10:49 -06:00
Steve Reinhardt
6f1187943c Replace curTick global variable with accessor functions.
This step makes it easy to replace the accessor functions
(which still access a global variable) with ones that access
per-thread curTick values.
2011-01-07 21:50:29 -08:00
Ali Saidi
e1b9a815dd SCons: Support building without an ISA 2010-11-19 18:00:39 -06:00
Steve Reinhardt
45aebaccde cache: minor SC assertion fix
Thanks to Joe Gross for finding/testing this.
2010-10-18 13:05:15 -07:00
Gabe Black
930c653270 Mem: Change the CLREX flag to CLEAR_LL.
CLREX is the name of an ARM instruction, not a name for this generic flag.
2010-10-13 01:57:31 -07:00
Steve Reinhardt
e918536380 cache: improve coherence handling of writebacks
If we write back an exclusive copy, we now mark it
as such, so the cache receiving the writeback can
mark its copy as exclusive.  This avoids some
unnecessary upgrade requests when a cache later
tries to re-acquire exclusive access to the block.
2010-09-21 23:07:34 -07:00
Nathan Binkert
afafaf1dcb style: fix sorting of includes and whitespace in some files 2010-09-10 14:58:04 -07:00
Steve Reinhardt
1249728494 cache: fail SC when invalidated while waiting for bus
Corrects an oversight in cset f97b62be544f.  The fix there only
failed queued SCUpgradeReq packets that encountered an
invalidation, which meant that the upgrade had to reach the L2
cache.  To handle pending requests in the L1 we must similarly
fail StoreCondReq packets too.
2010-09-09 14:40:19 -04:00
Steve Reinhardt
6dc599ea9b mem: fix functional accesses to deal with coherence change
We can't just obliviously return the first valid cache block
we find any more... see comments for details.
2010-09-09 14:40:19 -04:00
Steve Reinhardt
71aca6d29e cache: coherence protocol enhancements & bug fixes
Allow lower-level caches (e.g., L2 or L3) to pass exclusive
copies to higher levels (e.g., L1).  This eliminates a lot
of unnecessary upgrade transactions on read-write sequences
to non-shared data.

Also some cleanup of MSHR coherence handling and multiple
bug fixes.
2010-09-09 14:40:18 -04:00
Steve Reinhardt
3ffc4505f7 mem: fix m5.fast compile bug in previous cset 2010-08-26 08:03:20 -07:00
Steve Reinhardt
1bf944be62 cache: fix a bug in atomic multilevel snoops 2010-08-25 21:55:55 -07:00
Steve Reinhardt
62c06c1403 mem: fix dumb typo in copyrights 2010-08-25 14:08:27 -07:00
Gene Wu
d6736384b2 MEM: Make CLREX a first class request operation and clear locks in caches when it in received 2010-08-23 11:18:41 -05:00
Gene Wu
23626d99af ARM: Make sure that software prefetch instructions can't change the state of the TLB 2010-08-23 11:18:41 -05:00
Ali Saidi
ac575a9d82 Compiler: Fixes for GCC 4.5. 2010-08-23 11:18:39 -05:00
Timothy M. Jones
28a5ea3f99 Port: Only indicate that a SimpleTimingPort is drained if its send event is
not scheduled, as well as the transmit list being empty.
2010-07-22 18:54:37 +01:00
Steve Reinhardt
897247d63b cache: fix bug in SC upgrade handling
This bug was introduced with the recent rework of SC
failure handling in cset f97b62be544f.
2010-07-08 17:56:13 -07:00
Steve Reinhardt
de2321de81 cache: fix longstanding prefetcher bug
Thanks to Joe Gross for pointing this out (again?).
Apologies to anyone who pointed it out earlier and
we didn't listen.
2010-06-22 21:29:43 -07:00
Steve Reinhardt
f24ae2ec2a cache: fail store conditionals when upgrade loses race
Requires new "SCUpgradeReq" message that marks upgrades
for store conditionals, so downstream caches can fail
these when they run into invalidations.
See http://www.m5sim.org/flyspray/task/197
2010-06-16 15:25:57 -07:00
Steve Reinhardt
57f2b7db11 cache: fix dirty bit setting
Only set the dirty bit when we actually write to a block
(not if we thought we might but didn't, as in a failed
SC or CAS).  This requires makeing sure the dirty bit
stays set when we get an exclusive (writable) copy
in a cache-to-cache transfer from another owner, which
n turn requires copying the mem-inhibit flag from
timing-mode requests to their associated responses.
2010-06-16 15:25:57 -07:00
Nathan Binkert
86a93fe7b9 stats: only consider a formula initialized if there is a formula 2010-06-15 01:18:36 -07:00
Lisa Hsu
7f3cd9a9fd cache stats: account for writebacks and/or device occupancy in the cache.
Plus, a minor bugfix that neglects to update blk->contextSrc in certain cases on a cache insert.
2010-02-24 13:46:55 -08:00
Lisa Hsu
1d3228481f cache: Make caches sharing aware and add occupancy stats.
On the config end, if a shared L2 is created for the system, it is
parameterized to have n sharers as defined by option.num_cpus. In addition to
making the cache sharing aware so that discriminating tag policies can make use
of context_ids to make decisions, I added an occupancy AverageStat and an occ %
stat to each cache so that you could know which contexts are occupying how much
cache on average, both in terms of blocks and percentage. Note that since
devices have context_id -1, having an array of occ stats that correspond to
each context_id will break here, so in FS mode I add an extra bucket for device
blocks. This bucket is explicitly not added in SE mode in order to not only
avoid ugliness in the stats.txt file, but to avoid broken stats (some formulas
break when a bucket is 0).
2010-02-23 09:34:22 -08:00
Lisa Hsu
2ad386f104 cache: pull CacheSet out of LRU so that other tags can use associative sets. 2010-02-23 09:33:09 -08:00
Lisa Hsu
8b4e8690b7 cache: make tags->insertBlock() and tags->accessBlock() context aware so that the cache can make context-specific decisions within their various tag policy implementations. 2010-01-12 10:53:02 -08:00
Steve Reinhardt
f679630788 Minor cleanup: Use the blockAlign() method where it applies in the cache. 2009-09-26 10:50:50 -07:00
Steve Reinhardt
72cfed4164 Force prefetches to check cache and MSHRs immediately prior to issue.
This prevents redundant prefetches from being issued, solving the
occasional 'needsExclusive && !blk->isWritable()' assertion failure
in cache_impl.hh that several people have run into.
Eliminates "prefetch_cache_check_push" flag, neither setting of
which really solved the problem.
2009-09-26 10:50:50 -07:00
Nathan Binkert
d9f39c8ce7 arch: nuke arch/isa_specific.hh and move stuff to generated config/the_isa.hh 2009-09-23 08:34:21 -07:00
Steve Reinhardt
a13a706a20 Fix setting of INST_FETCH flag for O3 CPU.
It's still broken in inorder.
Also enhance DPRINTFs in cache and physical memory so we
can see more easily whether it's getting set or not.
2009-08-01 22:50:14 -07:00
Nathan Binkert
6faf377b53 types: clean up types, especially signed vs unsigned 2009-06-04 23:21:12 -07:00
Nathan Binkert
47877cf2db types: add a type for thread IDs and try to use it everywhere 2009-05-26 09:23:13 -07:00
Nathan Binkert
8d2e51c7f5 includes: sort includes again 2009-05-17 14:34:52 -07:00
Nathan Binkert
709d859530 includes: use base/types.hh not inttypes.h or stdint.h 2009-05-17 14:34:51 -07:00
Nathan Binkert
eef3a2e142 types: Move stuff for global types into src/base/types.hh
--HG--
rename : src/sim/host.hh => src/base/types.hh
2009-05-17 14:34:50 -07:00
Steve Reinhardt
6629d9b2bc mem: use single BadAddr responder per system.
Previously there was one per bus, which caused some coherence problems
when more than one decided to respond.  Now there is just one on
the main memory bus.  The default bus responder on all other buses
is now the downstream cache's cpu_side port.  Caches no longer need
to do address range filtering; instead, we just have a simple flag
to prevent snoops from propagating to the I/O bus.
2008-07-16 11:10:33 -07:00
Steve Reinhardt
3083268d60 request: rename INST_READ to INST_FETCH. 2009-04-20 18:54:02 -07:00
Gabe Black
bd6f2bb538 Mem: Change isLlsc to isLLSC. 2009-04-19 21:44:15 -07:00
Gabe Black
3e5f487663 Memory: Rename LOCKED for load locked store conditional to LLSC. 2009-04-19 04:25:01 -07:00
Steve Reinhardt
758bfe4eb5 cache: set dirty bit on swaps (oops!) 2009-03-11 23:05:26 -07:00
Steve Reinhardt
a94c68228a prefetch: don't panic on requests w/o contextID (e.g., writebacks). 2009-03-10 17:37:15 -07:00
Nathan Binkert
cc95b57390 stats: Fix all stats usages to deal with template fixes 2009-03-05 19:09:53 -08:00
Steve Reinhardt
89a7fb0393 Fixes to get prefetching working again.
Apparently we broke it with the cache rewrite and never noticed.
Thanks to Bao Yungang <baoyungang@gmail.com> for a significant part
of these changes (and for inspiring me to work on the rest).
Some other overdue cleanup on the prefetch code too.
2009-02-16 08:56:40 -08:00
Steve Reinhardt
640b415688 Cache: get rid of obsolete Tag methods.
I think readData() and writeData() were used for Erik's compression
work, but that code is gone, these aren't called anymore, and they
don't even really do what their names imply.
2008-11-14 14:14:35 -08:00
Steve Reinhardt
42bd460d7f Cache: Refactor packet forwarding a bit.
Makes adding write-through operations easier.
2008-11-10 14:10:28 -08:00
Lisa Hsu
c68032ddcb decouple eviction from insertion in the cache. 2008-11-04 11:35:58 -05:00
Lisa Hsu
4ab52cb986 Change the findBlock(addr, lat) to accessBlock, which I think has better connotations for what is really happening and how it should be used. 2008-11-04 11:35:57 -05:00
Lisa Hsu
dd99ff23c6 get rid of all instances of readTid() and getThreadNum(). Unify and eliminate
redundancies with threadId() as their replacement.
2008-11-04 11:35:42 -05:00