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Mem: Change the CLREX flag to CLEAR_LL.

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CLREX is the name of an ARM instruction, not a name for this generic flag.
This commit is contained in:
Gabe Black 2010-10-13 01:57:31 -07:00
parent b273e0be33
commit 930c653270
5 changed files with 10 additions and 8 deletions
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3
src/arch/arm/isa/insts/misc.isa
View file

@ -671,7 +671,8 @@ let {{
exec_output += PredOpExecute.subst(setendIop)
clrexCode = '''
unsigned memAccessFlags = Request::CLREX|3|Request::LLSC;
unsigned memAccessFlags = Request::CLEAR_LL |
ArmISA::TLB::AlignWord | Request::LLSC;
fault = xc->read(0, (uint32_t&)Mem, memAccessFlags);
'''
clrexIop = InstObjParams("clrex", "Clrex","PredOp",

3
src/arch/arm/isa/templates/misc.isa
View file

@ -367,7 +367,8 @@ def template ClrexInitiateAcc {{
if (%(predicate_test)s)
{
if (fault == NoFault) {
unsigned memAccessFlags = Request::CLREX|3|Request::LLSC;
unsigned memAccessFlags = Request::CLEAR_LL |
ArmISA::TLB::AlignWord | Request::LLSC;
fault = xc->read(0, (uint32_t&)Mem, memAccessFlags);
}
} else {

4
src/arch/arm/tlb.cc
View file

@ -376,10 +376,10 @@ TLB::translateFs(RequestPtr req, ThreadContext *tc, Mode mode,
// If this is a clrex instruction, provide a PA of 0 with no fault
// This will force the monitor to set the tracked address to 0
// a bit of a hack but this effectively clrears this processors monitor
if (flags & Request::CLREX){
if (flags & Request::CLEAR_LL){
req->setPaddr(0);
req->setFlags(Request::UNCACHEABLE);
req->setFlags(Request::CLREX);
req->setFlags(Request::CLEAR_LL);
return NoFault;
}
if ((req->isInstFetch() && (!sctlr.i)) ||

4
src/mem/cache/cache_impl.hh vendored
View file

@ -306,7 +306,7 @@ Cache<TagStore>::access(PacketPtr pkt, BlkType *&blk,
int &lat, PacketList &writebacks)
{
if (pkt->req->isUncacheable()) {
if (pkt->req->isClrex()) {
if (pkt->req->isClearLL()) {
tags->clearLocks();
} else {
blk = tags->findBlock(pkt->getAddr());
@ -449,7 +449,7 @@ Cache<TagStore>::timingAccess(PacketPtr pkt)
}
if (pkt->req->isUncacheable()) {
if (pkt->req->isClrex()) {
if (pkt->req->isClearLL()) {
tags->clearLocks();
} else {
BlkType *blk = tags->findBlock(pkt->getAddr());

4
src/mem/request.hh
View file

@ -72,7 +72,7 @@ class Request : public FastAlloc
/** This request is to a memory mapped register. */
static const FlagsType MMAPED_IPR = 0x00002000;
/** This request is a clear exclusive. */
static const FlagsType CLREX = 0x00004000;
static const FlagsType CLEAR_LL = 0x00004000;
/** The request should ignore unaligned access faults */
static const FlagsType NO_ALIGN_FAULT = 0x00020000;
@ -458,7 +458,7 @@ class Request : public FastAlloc
bool isSwap() const { return _flags.isSet(MEM_SWAP|MEM_SWAP_COND); }
bool isCondSwap() const { return _flags.isSet(MEM_SWAP_COND); }
bool isMmapedIpr() const { return _flags.isSet(MMAPED_IPR); }
bool isClrex() const { return _flags.isSet(CLREX); }
bool isClearLL() const { return _flags.isSet(CLEAR_LL); }
bool
isMisaligned() const