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Author SHA1 Message Date
Steve Reinhardt
ac32645c27 Change detault regression build from opt to fast. 
--HG--
extra : convert_revision : b6db0254b73a97ab6e3685c90cc9cd30ea274d4f
 2006-12-07 14:41:56 -05:00
Ali Saidi
03be92f23b Handle access to ASI_QUEUE 
Add function for interrupt ASIs
add all the new MISCREGs to the copyMiscRegs() file

src/arch/sparc/asi.cc:
src/arch/sparc/asi.hh:
    Add function for interrupt ASIs
src/arch/sparc/miscregfile.cc:
src/arch/sparc/miscregfile.hh:
    Add QUEUE asi/misc registers
src/arch/sparc/regfile.cc:
    add all the new MISCREGs to the copyMiscRegs() file
src/arch/sparc/tlb.cc:
    Handle access to ASI_QUEUE

--HG--
extra : convert_revision : 7a14450485816e6ee3bc8c80b462a13e1edf0ba0
 2006-12-06 19:25:53 -05:00
Ali Saidi
ecbb8debf6 Many more fixes for SPARC_FS. Gets us to the point where SOFTINT starts 
getting touched.

configs/common/FSConfig.py:
    Physical memory on the T1 starts at 1MB, The first megabyte is unmapped to catch bugs
src/arch/isa_parser.py:
    we should readmiscregwitheffect not readmiscreg
src/arch/sparc/asi.cc:
    Fix AsiIsNucleus spelling with respect to header file
    Add ASI_LSU_CONTROL_REG to AsiSiMmu
src/arch/sparc/asi.hh:
    Fix spelling of two ASIs
src/arch/sparc/isa/decoder.isa:
    switch back to defaults letting the isa_parser insert readMiscRegWithEffect
src/arch/sparc/isa/formats/mem/util.isa:
    Flesh out priviledgedString with hypervisor checks
    Make load alternate set the flags correctly
src/arch/sparc/miscregfile.cc:
    insert some forgotten break statements
src/arch/sparc/miscregfile.hh:
    Add some comments to make it easier to find which misc register is which number
src/arch/sparc/tlb.cc:
    flesh out the tlb memory mapped registers a lot more
src/base/traceflags.py:
    add an IPR traceflag
src/mem/request.hh:
    Fix a bad assert() in request

--HG--
extra : convert_revision : 1e11aa004e8f42c156e224c1d30d49479ebeed28
 2006-12-06 14:29:10 -05:00
Kevin Lim
b618e733bd Fix for MIPS_SE/m5.fast compile. 
--HG--
extra : convert_revision : dbb893250974ac6db7b6c1ba67263fd35098ca43
 2006-12-06 14:23:31 -05:00
Gabe Black
50b8cce355 Use the renamed register index, rather than the flattened one. 
--HG--
extra : convert_revision : 599650c408667bb1b8db20a6847b9e697f7b49e4
 2006-12-06 11:40:41 -05:00
Gabe Black
f04fcf58f1 Got rid of some typedefs and moved the tlbs into the base o3 cpu. 
--HG--
extra : convert_revision : dcd1d2a64fd91aded15c8c763a78b4eebf421870
 2006-12-06 11:39:49 -05:00
Gabe Black
07a4e2cd36 Use the setSyscallReturn defined in arch rather than duplicating it here. 
--HG--
extra : convert_revision : 862ece59aa253b52b6744a0a76738d5ee19561b3
 2006-12-06 11:38:39 -05:00
Gabe Black
ef942ceecb Moved the RegIdx arrays to the base dyninst. 
--HG--
extra : convert_revision : d705cde25c2cf1add20669e99d086add49141518
 2006-12-06 11:37:39 -05:00
Gabe Black
6826ee53db Got rid of some typedefs, moved the tlbs to the base o3 cpu, and called the architecture defined setSyscallReturn function instead of a duplicate copy. 
src/cpu/o3/alpha/cpu.hh:
    Got rid of some typedefs, and moved the tlbs to the base o3 cpu.
src/cpu/o3/alpha/thread_context.hh:
src/cpu/o3/cpu.cc:
    Moved the tlbs to the base o3 cpu.

--HG--
extra : convert_revision : 1805613aa230b8974a226ee3d2584c85f7a578aa
 2006-12-06 11:36:40 -05:00
Gabe Black
0ed6c52c1e Made the alpha setSyscallReturn take a ThreadContext pointer instead of a RegFile *. 
--HG--
extra : convert_revision : 021a1fe6760df1daf6299d46060371a5310f008a
 2006-12-06 11:33:37 -05:00
Gabe Black
b3cfa6ec42 Added a flattenIntIndex function for Alpha. 
--HG--
extra : convert_revision : 5ed79ed18e443118a28d6890327c55a6a3fcd325
 2006-12-06 11:30:41 -05:00
Gabe Black
2dcf00bc8b Merge zizzer:/bk/newmem 
into  zower.eecs.umich.edu:/eecshome/m5/newmem

src/cpu/o3/commit_impl.hh:
    Hand Merge

--HG--
extra : convert_revision : 6984db90d5b5ec71c31f1c345f5a77eed540059e
 2006-12-06 06:05:28 -05:00
Gabe Black
be29adf51c Added a DPRINTF to print out the actual value pulled from memory. 
--HG--
extra : convert_revision : 18780f753a7e98f8de3047dd6781b944b0826b4e
 2006-12-06 06:02:13 -05:00
Gabe Black
75b93179ab Flattening and syscallReturn fixes 
src/cpu/o3/thread_context_impl.hh:
    Use flattened indices
src/cpu/simple_thread.hh:
    Use flattened indices, and pass a thread context to setSyscallReturn rather than a register file.
src/cpu/thread_context.hh:
    The SyscallReturn class is no longer in arch/syscallreturn.hh

--HG--
extra : convert_revision : ed84bb8ac5ef0774526ecd0d7270b0c60cd3708e
 2006-12-06 06:00:04 -05:00
Gabe Black
1886795368 Don't panic, but this needs to be fixed. 
--HG--
extra : convert_revision : 7a4aed238d437dbb2cc5946b3045d53697070a27
 2006-12-06 05:58:07 -05:00
Gabe Black
1d7d7df315 Make syscalls flatten their register indices, and also call into the ISA's setSyscallReturn function rather than having a duplicated one. 
--HG--
extra : convert_revision : 1e83ef629a7fd143f2e35e68abaa56f81d6b9d9e
 2006-12-06 05:56:34 -05:00
Gabe Black
156cf0db51 Change rename to rename the flattened register index instead of the architectural one. 
--HG--
extra : convert_revision : 757866ad7a3c8be7382e1ffa71c60bc00c861f6f
 2006-12-06 05:55:23 -05:00
Gabe Black
6456cb535c Added in endianness conversion on memory accesses as the data goes out. This will break the checker! 
--HG--
extra : convert_revision : b8191cab09ab8f3ced05693293f058382319ed8e
 2006-12-06 05:54:16 -05:00
Gabe Black
20340b5e26 Change how optional delay slot instructions are detected and squashed. 
--HG--
extra : convert_revision : ffd019d4adc2fbbc0a663d8dc6ef73edce12511b
 2006-12-06 05:51:18 -05:00
Gabe Black
8a21635eff Get rid of some typedefs which were hardly used, and move some stuff back here that shouldn't be in the architecture specific DynInst classes. 
--HG--
extra : convert_revision : dad0d7191acf773c16dc3ed9dd911f5e8bfc08b3
 2006-12-06 05:48:59 -05:00
Gabe Black
dc105934f3 Change to use -return_value.value like other implementations. 
--HG--
extra : convert_revision : 513422c1c8c24f3662e6a423d13ee033424aa44b
 2006-12-06 05:47:19 -05:00
Gabe Black
bf5f6c6430 Some changes for misc regs which were changed into unofficial integer registers, and moved the flattenIndex function into the register file. 
--HG--
extra : convert_revision : 6b797c793a6c12c61a23f0f78a1ea1c88609553e
 2006-12-06 05:46:44 -05:00
Gabe Black
5ad1731a12 Reorganize the includes and add an include for misc.hh. 
--HG--
extra : convert_revision : 484b2d07a1e8b3879c35d80bf16b73fd0cc9be1f
 2006-12-06 05:45:18 -05:00
Gabe Black
643cb6dd81 Added some debug output, and made sure not to accidentally ask for the result of a store conditional. 
--HG--
extra : convert_revision : d36ff9e2343fdf78a3bc16a1348975fdba5c55e2
 2006-12-06 05:44:31 -05:00
Gabe Black
a36a59e8d7 Some basic fix ups, and CWP is no longer set explicitly. 
--HG--
extra : convert_revision : 1dde5594a2bcfd9fb5ad974360b3dc035f1624e5
 2006-12-06 05:43:25 -05:00
Gabe Black
c541be3a48 Changed the integer register file to work with flattened indices. 
--HG--
extra : convert_revision : c5153c3c712e5d18b5233e1fd205806adcb30654
 2006-12-06 05:42:09 -05:00
Gabe Black
4d8a0541dd Change MIPS's setSyscallReturn to use a thread context. 
--HG--
extra : convert_revision : 618f8404ec5380615e28170d761b2fcdf9c07d96
 2006-12-06 05:41:08 -05:00
Gabe Black
a3f351ab59 Added basic flatten function for mips. 
--HG--
extra : convert_revision : 2c32851584001734d139f36c4d58c5e61067fcfc
 2006-12-06 05:40:11 -05:00
Kevin Lim
54a946604b Override default SConscript options and only build the SimpleCPUs. 
--HG--
extra : convert_revision : cfcfb787d8442cb76ed766aa5bc947636f067209
 2006-12-05 11:12:18 -05:00
Steve Reinhardt
2e1200e57f Merge zizzer.eecs.umich.edu:bk/newmem-cache2 
into  vm1.(none):/home/stever/bk/newmem-cache2

--HG--
extra : convert_revision : 0a7d17460f17c96fe869124f54f9c92409495003
 2006-12-05 07:24:13 -08:00
Steve Reinhardt
c50965042f Merge zizzer.eecs.umich.edu:/z/stever/bk/newmem-head 
into  zizzer.eecs.umich.edu:/z/stever/bk/newmem-cache2

--HG--
extra : convert_revision : a5569cef10ab22da1865e368f0bb5e7532772227
 2006-12-05 10:23:20 -05:00
Steve Reinhardt
51b3d7f4de Merge zizzer.eecs.umich.edu:/z/stever/bk/newmem-head 
into  zizzer.eecs.umich.edu:/z/stever/bk/newmem-cache2

--HG--
extra : convert_revision : ca78bf2fc1ddefd56b98a90eaffab57d93026626
 2006-12-05 10:18:35 -05:00
Steve Reinhardt
1c28682cea Don't compress data on writebacks unless it's actually necessary. 
--HG--
extra : convert_revision : 7a068e28f9ea2f6aab57be7133b47bda72d10302
 2006-12-05 07:16:36 -08:00
Gabe Black
12c5bd2305 Move the SyscallReturn class into sim/syscallreturn.hh. Also move some miscregs into the integer register file so they get renamed. 
src/arch/alpha/syscallreturn.hh:
src/arch/mips/syscallreturn.hh:
src/sim/syscallreturn.hh:
    Move the SyscallReturn class into sim/syscallreturn.hh
src/arch/sparc/faults.cc:
src/arch/sparc/isa/operands.isa:
src/arch/sparc/isa_traits.hh:
src/arch/sparc/miscregfile.cc:
src/arch/sparc/miscregfile.hh:
src/arch/sparc/process.cc:
src/arch/sparc/sparc_traits.hh:
    Move some miscregs into the integer register file so they get renamed.

--HG--
extra : convert_revision : df5b94fa1e7fdca34816084e0a423d6fdf86c79b
 2006-12-05 01:55:02 -05:00
Steve Reinhardt
a2c315b85f Merge vm1.(none):/home/stever/bk/newmem-head 
into  vm1.(none):/home/stever/bk/newmem-cache2

--HG--
extra : convert_revision : e456687d940c833d8255a88633555778480f7825
 2006-12-04 21:35:48 -08:00
Ali Saidi
4d57cab49a forgot to commit miscreg file 
--HG--
extra : convert_revision : c2ede9efbf7b264c32d5565d3f0fc0601c4cd63b
 2006-12-04 20:29:55 -05:00
Gabe Black
8b1bcc3f52 Merge zizzer:/bk/sparcfs 
into  zower.eecs.umich.edu:/eecshome/m5/newmemmid

--HG--
extra : convert_revision : 45d9599dd883e10c283812c1c241c20323f44cec
 2006-12-04 19:56:04 -05:00
Gabe Black
251f4e1134 Add in code to pass the ASI to translation. 
--HG--
extra : convert_revision : 4a985635cda7680abcddaf0bc9579fa03d5bc7c6
 2006-12-04 19:55:52 -05:00
Lisa Hsu
2de685cc21 Merge zizzer:/bk/sparcfs 
into  zed.eecs.umich.edu:/z/hsul/work/sparc/m5

--HG--
extra : convert_revision : 3186d6055794b41c26eb8d2411903869b5b39329
 2006-12-04 19:39:58 -05:00
Ali Saidi
8e75b6e2a5 reogranize code to split off FS only misc regs with effect into their own file (reducing the number of if FULL_SYSTEM defines and includes) 
Protect other pieces of code so that sparc compiles SE again

src/arch/sparc/SConscript:
    Add ua2005.cc back into SConscript
src/arch/sparc/miscregfile.hh:
    add functions that deal with priv registers so we don't have to have a bunch of if defs and other ugliness
src/arch/sparc/mmaped_ipr.hh:
    wrap handleIpr* with if full_system so it compiles under se
src/arch/sparc/ua2005.cc:
    reorganize edit fs only miscreg functions
src/cpu/exetrace.cc:
    protect legion code so it doesn't try to compile under se

--HG--
extra : convert_revision : 6b3c9f6f95b4da8544525f4f82e92861383ede76
 2006-12-04 19:39:57 -05:00
Lisa Hsu
e86832bed8 automatically build sparc system or alpha system. 
configs/example/fs.py:
    make it an automatic system build for alpha vs. sparc.

--HG--
extra : convert_revision : 4c217cf9309c6209be7f80e358f6640857a785e8
 2006-12-04 19:37:50 -05:00
Steve Reinhardt
6c1b311faf Merge zizzer.eecs.umich.edu:/bk/newmem 
into  vm1.(none):/home/stever/bk/newmem-head

--HG--
extra : convert_revision : df2b33a629ae4298c4da33383b491e3cbefab92d
 2006-12-04 16:10:50 -08:00
Steve Reinhardt
9d39407500 Update SPEC CPU2000 tests with actual benchmark output. 
tests/long/00.gzip/ref/alpha/linux/o3-timing/config.ini:
tests/long/00.gzip/ref/alpha/linux/o3-timing/config.out:
tests/long/00.gzip/ref/alpha/linux/o3-timing/m5stats.txt:
tests/long/00.gzip/ref/alpha/linux/o3-timing/stderr:
tests/long/00.gzip/ref/alpha/linux/o3-timing/stdout:
tests/long/00.gzip/ref/alpha/linux/simple-atomic/config.ini:
tests/long/00.gzip/ref/alpha/linux/simple-atomic/config.out:
tests/long/00.gzip/ref/alpha/linux/simple-atomic/m5stats.txt:
tests/long/00.gzip/ref/alpha/linux/simple-atomic/stderr:
tests/long/00.gzip/ref/alpha/linux/simple-atomic/stdout:
tests/long/00.gzip/ref/alpha/linux/simple-timing/config.ini:
tests/long/00.gzip/ref/alpha/linux/simple-timing/config.out:
tests/long/00.gzip/ref/alpha/linux/simple-timing/m5stats.txt:
tests/long/00.gzip/ref/alpha/linux/simple-timing/stderr:
tests/long/00.gzip/ref/alpha/linux/simple-timing/stdout:
tests/long/30.eon/ref/alpha/linux/simple-atomic/config.ini:
tests/long/30.eon/ref/alpha/linux/simple-atomic/config.out:
tests/long/30.eon/ref/alpha/linux/simple-atomic/m5stats.txt:
tests/long/30.eon/ref/alpha/linux/simple-atomic/stderr:
tests/long/30.eon/ref/alpha/linux/simple-atomic/stdout:
tests/long/30.eon/ref/alpha/linux/simple-timing/config.ini:
tests/long/30.eon/ref/alpha/linux/simple-timing/config.out:
tests/long/30.eon/ref/alpha/linux/simple-timing/m5stats.txt:
tests/long/30.eon/ref/alpha/linux/simple-timing/stderr:
tests/long/30.eon/ref/alpha/linux/simple-timing/stdout:
tests/long/40.perlbmk/ref/alpha/linux/simple-atomic/config.ini:
tests/long/40.perlbmk/ref/alpha/linux/simple-atomic/config.out:
tests/long/40.perlbmk/ref/alpha/linux/simple-atomic/m5stats.txt:
tests/long/40.perlbmk/ref/alpha/linux/simple-atomic/stderr:
tests/long/40.perlbmk/ref/alpha/linux/simple-atomic/stdout:
tests/long/40.perlbmk/ref/alpha/linux/simple-timing/config.ini:
tests/long/40.perlbmk/ref/alpha/linux/simple-timing/config.out:
tests/long/40.perlbmk/ref/alpha/linux/simple-timing/m5stats.txt:
tests/long/40.perlbmk/ref/alpha/linux/simple-timing/stderr:
tests/long/40.perlbmk/ref/alpha/linux/simple-timing/stdout:
tests/long/50.vortex/ref/alpha/linux/o3-timing/config.ini:
tests/long/50.vortex/ref/alpha/linux/o3-timing/config.out:
tests/long/50.vortex/ref/alpha/linux/o3-timing/m5stats.txt:
tests/long/50.vortex/ref/alpha/linux/o3-timing/stderr:
tests/long/50.vortex/ref/alpha/linux/o3-timing/stdout:
tests/long/50.vortex/ref/alpha/linux/simple-atomic/config.ini:
tests/long/50.vortex/ref/alpha/linux/simple-atomic/config.out:
tests/long/50.vortex/ref/alpha/linux/simple-atomic/m5stats.txt:
tests/long/50.vortex/ref/alpha/linux/simple-atomic/stderr:
tests/long/50.vortex/ref/alpha/linux/simple-atomic/stdout:
tests/long/50.vortex/ref/alpha/linux/simple-timing/config.ini:
tests/long/50.vortex/ref/alpha/linux/simple-timing/config.out:
tests/long/50.vortex/ref/alpha/linux/simple-timing/m5stats.txt:
tests/long/50.vortex/ref/alpha/linux/simple-timing/stderr:
tests/long/50.vortex/ref/alpha/linux/simple-timing/stdout:
tests/long/60.bzip2/ref/alpha/linux/o3-timing/config.ini:
tests/long/60.bzip2/ref/alpha/linux/o3-timing/config.out:
tests/long/60.bzip2/ref/alpha/linux/o3-timing/m5stats.txt:
tests/long/60.bzip2/ref/alpha/linux/o3-timing/stderr:
tests/long/60.bzip2/ref/alpha/linux/o3-timing/stdout:
tests/long/60.bzip2/ref/alpha/linux/simple-atomic/config.ini:
tests/long/60.bzip2/ref/alpha/linux/simple-atomic/config.out:
tests/long/60.bzip2/ref/alpha/linux/simple-atomic/m5stats.txt:
tests/long/60.bzip2/ref/alpha/linux/simple-atomic/stderr:
tests/long/60.bzip2/ref/alpha/linux/simple-atomic/stdout:
tests/long/60.bzip2/ref/alpha/linux/simple-timing/config.ini:
tests/long/60.bzip2/ref/alpha/linux/simple-timing/config.out:
tests/long/60.bzip2/ref/alpha/linux/simple-timing/m5stats.txt:
tests/long/60.bzip2/ref/alpha/linux/simple-timing/stderr:
tests/long/60.bzip2/ref/alpha/linux/simple-timing/stdout:
tests/long/70.twolf/ref/alpha/linux/o3-timing/config.ini:
tests/long/70.twolf/ref/alpha/linux/o3-timing/config.out:
tests/long/70.twolf/ref/alpha/linux/o3-timing/m5stats.txt:
tests/long/70.twolf/ref/alpha/linux/o3-timing/stderr:
tests/long/70.twolf/ref/alpha/linux/o3-timing/stdout:
tests/long/70.twolf/ref/alpha/linux/simple-atomic/config.ini:
tests/long/70.twolf/ref/alpha/linux/simple-atomic/config.out:
tests/long/70.twolf/ref/alpha/linux/simple-atomic/m5stats.txt:
tests/long/70.twolf/ref/alpha/linux/simple-atomic/stderr:
tests/long/70.twolf/ref/alpha/linux/simple-atomic/stdout:
tests/long/70.twolf/ref/alpha/linux/simple-timing/config.ini:
tests/long/70.twolf/ref/alpha/linux/simple-timing/config.out:
tests/long/70.twolf/ref/alpha/linux/simple-timing/m5stats.txt:
tests/long/70.twolf/ref/alpha/linux/simple-timing/stderr:
tests/long/70.twolf/ref/alpha/linux/simple-timing/stdout:
    Update with actual benchmark output.

--HG--
extra : convert_revision : 12e8de58172dd717d9cc8c5c27dd926a7257153c
 2006-12-04 19:07:00 -05:00
Steve Reinhardt
34a1f9e14e Only update stderr, stdout, m5stats.txt, and config.* on update_ref, 
since we don't know which of the other files are outputs and which
are inputs.

--HG--
extra : convert_revision : b038bd15930721ab9fceb0a18ab5c895aacb5309
 2006-12-04 19:05:09 -05:00
Steve Reinhardt
66a9697c49 Clean up SPEC CPU2000 reference files. 
Get rid of reference files for o3-atomic (non-existent configuration)
and mcf (doesn't seem to be working).
Left in empty refs for parser/simple-timing... this appears to be
dying because it's running out of memory, so maybe it will be OK
once we get the memory leak fixed.

--HG--
extra : convert_revision : ae3bc8dfec44d09a2a084da5041ec386fe16be8b
 2006-12-04 18:57:17 -05:00
Ali Saidi
db427bb3a9 delete m5stats which shouldn't have been commited 
--HG--
extra : convert_revision : cc9f65c94145e957ea96e0b765ae2ea0ae093029
 2006-12-04 18:25:21 -05:00
Ali Saidi
153e02a435 Legion actually writes to tl-1 in the data structure, so we need to compare correctly 
--HG--
extra : convert_revision : 60fef1bd5dc03d7b107150dba922dd4a3f51626f
 2006-12-04 18:22:55 -05:00
Lisa Hsu
0d62558d55 Merge zizzer:/bk/sparcfs 
into  zed.eecs.umich.edu:/z/hsul/work/sparc/m5

--HG--
extra : convert_revision : 3bce43982689e9bda3a12e21a24b5ea390f347b8
 2006-12-04 17:51:07 -05:00
Steve Reinhardt
5fbf3aa471 Turn cache MissQueue/BlockingBuffer into virtual object 
instead of template parameter.

--HG--
extra : convert_revision : fce0fbd041149b9c781eb23f480ba84fddbfd4a0
 2006-12-04 09:10:53 -08:00
Steve Reinhardt
51e3688701 Better handling of scons -u targets. 
--HG--
extra : convert_revision : 7bf0688a1c83d8385b77a59a1c75040e9624c0ae
 2006-12-04 09:09:36 -08:00