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Ali Saidi ecbb8debf6 Many more fixes for SPARC_FS. Gets us to the point where SOFTINT starts 
getting touched.

configs/common/FSConfig.py:
    Physical memory on the T1 starts at 1MB, The first megabyte is unmapped to catch bugs
src/arch/isa_parser.py:
    we should readmiscregwitheffect not readmiscreg
src/arch/sparc/asi.cc:
    Fix AsiIsNucleus spelling with respect to header file
    Add ASI_LSU_CONTROL_REG to AsiSiMmu
src/arch/sparc/asi.hh:
    Fix spelling of two ASIs
src/arch/sparc/isa/decoder.isa:
    switch back to defaults letting the isa_parser insert readMiscRegWithEffect
src/arch/sparc/isa/formats/mem/util.isa:
    Flesh out priviledgedString with hypervisor checks
    Make load alternate set the flags correctly
src/arch/sparc/miscregfile.cc:
    insert some forgotten break statements
src/arch/sparc/miscregfile.hh:
    Add some comments to make it easier to find which misc register is which number
src/arch/sparc/tlb.cc:
    flesh out the tlb memory mapped registers a lot more
src/base/traceflags.py:
    add an IPR traceflag
src/mem/request.hh:
    Fix a bad assert() in request

--HG--
extra : convert_revision : 1e11aa004e8f42c156e224c1d30d49479ebeed28
2006-12-06 14:29:10 -05:00
build_opts Add o3-timing configuration for ALPHA_SE "Hello world" tests. 2006-09-01 17:59:36 -04:00
configs Many more fixes for SPARC_FS. Gets us to the point where SOFTINT starts 2006-12-06 14:29:10 -05:00
ext New directory structure: 2006-05-22 14:29:33 -04:00
src Many more fixes for SPARC_FS. Gets us to the point where SOFTINT starts 2006-12-06 14:29:10 -05:00
tests change this to be a quick one so that it's in the regressions every night - it's only maybe 15 min. long. 2006-12-01 13:51:49 -05:00
util Get rid of the old release-edits script and create make_release.py 2006-11-30 20:50:47 -08:00
AUTHORS AUTHORS: 2006-08-17 00:44:54 -04:00
LICENSE Remove authors from copyright. 2006-05-28 23:26:15 -04:00
README Update for 2.0 beta 1 patch 1 2006-08-25 15:17:25 -04:00
RELEASE_NOTES add 2.0b2 release notes 2006-11-28 16:02:13 -05:00
SConstruct Add in O3CPU to default CPU list. 2006-11-29 11:50:03 -05:00

README 

This is release 2.0_beta (patch 1) of the M5 simulator.

For detailed information about building the simulator and getting
started please refer to http://www.m5sim.org.

Specific pages of interest are:
http://www.m5sim.org/wiki/index.php/Compiling_M5
http://www.m5sim.org/wiki/index.php/Running_M5

Short version:

1. If you don't have SCons version 0.96.91 or newer, get it from
http://wwww.scons.org.

2. If you don't have SWIG version 1.3.28 or newer, get it from
http://wwww.swig.org.

3. In this directory, type 'scons build/ALPHA_SE/tests/debug/quick'.  This
will build the debug version of the m5 binary (m5.debug) for the Alpha
syscall emulation target, and run the quick regression tests on it.

If you have questions, please send mail to m5-users@m5sim.org

WHAT'S INCLUDED (AND NOT)
-------------------------

The basic source release includes these subdirectories:
 - m5: 
   - src: source code of the m5 simulator
   - tests: regression tests
   - ext: less-common external packages needed to build m5
   - system/alpha: source for Alpha console and PALcode

To run full-system simulations, you will need compiled console,
PALcode, and kernel binaries and one or more disk images.  These files
are collected in a separate archive, m5_system.tar.bz2.  This file
can he downloaded separately.

M5 supports Linux 2.4/2.6, FreeBSD, and the proprietary Compaq/HP
Tru64 version of Unix. We are able to distribute Linux and FreeBSD
bootdisks, but we are unable to distribute bootable disk images of
Tru64 Unix. If you have a Tru64 license and are interested in
obtaining disk images, contact us at m5-dev@eecs.umich.edu.