Merge zizzer.eecs.umich.edu:/bk/newmem
into vm1.(none):/home/stever/bk/newmem-head --HG-- extra : convert_revision : df2b33a629ae4298c4da33383b491e3cbefab92d
This commit is contained in:
Steve Reinhardt
commit
6c1b311faf
108 changed files with 8545 additions and 37550 deletions
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@ -114,11 +114,7 @@ def update_test(target, source, env):
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src_dir = str(source[1].get_dir())
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dest_files = os.listdir(dest_dir)
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src_files = os.listdir(src_dir)
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# Exclude status & diff outputs
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for f in ('outdiff', 'statsdiff', 'status'):
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if f in src_files:
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src_files.remove(f)
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for f in src_files:
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for f in ('stdout', 'stderr', 'm5stats.txt', 'config.ini', 'config.out'):
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if f in dest_files:
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print " Replacing file", f
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dest_files.remove(f)
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@ -7,11 +7,9 @@ max_tick=0
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output_file=cout
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progress_interval=0
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[debug]
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break_cycles=
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[exetrace]
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intel_format=false
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legion_lockstep=false
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pc_symbol=true
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print_cpseq=false
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print_cycle=true
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@ -102,14 +100,15 @@ max_insts_all_threads=0
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max_insts_any_thread=0
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max_loads_all_threads=0
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max_loads_any_thread=0
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mem=system.cpu.dcache
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numIQEntries=64
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numPhysFloatRegs=256
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numPhysIntRegs=256
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numROBEntries=192
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numRobs=1
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numThreads=1
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phase=0
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predType=tournament
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progress_interval=0
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renameToDecodeDelay=1
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renameToFetchDelay=1
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renameToIEWDelay=2
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@ -131,7 +130,6 @@ assoc=2
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block_size=64
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compressed_bus=false
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compression_latency=0
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do_copy=false
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hash_delay=1
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hit_latency=1
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latency=1
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@ -308,7 +306,6 @@ assoc=2
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block_size=64
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compressed_bus=false
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compression_latency=0
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do_copy=false
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hash_delay=1
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hit_latency=1
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latency=1
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@ -348,7 +345,6 @@ assoc=2
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block_size=64
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compressed_bus=false
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compression_latency=0
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do_copy=false
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hash_delay=1
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hit_latency=1
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latency=1
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@ -384,20 +380,33 @@ mem_side=system.membus.port[1]
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[system.cpu.toL2Bus]
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type=Bus
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bus_id=0
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clock=1000
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responder_set=false
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width=64
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port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
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[system.cpu.workload]
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type=LiveProcess
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cmd=hello
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cmd=gzip input.log 1
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cwd=build/ALPHA_SE/tests/opt/long/00.gzip/alpha/linux/o3-timing
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egid=100
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env=
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executable=tests/test-progs/hello/bin/alpha/linux/hello
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euid=100
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executable=/dist/m5/cpu2000/binaries/alpha/tru64/gzip
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gid=100
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input=cin
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output=cout
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pid=100
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ppid=99
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system=system
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uid=100
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[system.membus]
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type=Bus
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bus_id=0
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clock=1000
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responder_set=false
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width=64
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port=system.physmem.port system.cpu.l2cache.mem_side
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[system.physmem]
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@ -409,6 +418,7 @@ port=system.membus.port[0]
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[trace]
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bufsize=0
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cycle=0
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dump_on_exit=false
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file=cout
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flags=
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@ -19,54 +19,25 @@ mem_mode=atomic
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[system.membus]
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type=Bus
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bus_id=0
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clock=1000
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width=64
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responder_set=false
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[system.cpu.workload]
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type=LiveProcess
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cmd=hello
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executable=tests/test-progs/hello/bin/alpha/linux/hello
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cmd=gzip input.log 1
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executable=/dist/m5/cpu2000/binaries/alpha/tru64/gzip
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input=cin
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output=cout
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env=
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cwd=build/ALPHA_SE/tests/opt/long/00.gzip/alpha/linux/o3-timing
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system=system
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[system.cpu.dcache]
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type=BaseCache
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size=262144
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assoc=2
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block_size=64
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latency=1
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mshrs=10
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tgts_per_mshr=5
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write_buffers=8
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prioritizeRequests=false
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do_copy=false
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protocol=null
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trace_addr=0
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hash_delay=1
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repl=null
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compressed_bus=false
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store_compressed=false
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adaptive_compression=false
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compression_latency=0
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block_size=64
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max_miss_count=0
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addr_range=[0,18446744073709551615]
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split=false
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split_size=0
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lifo=false
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two_queue=false
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prefetch_miss=false
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prefetch_access=false
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prefetcher_size=100
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prefetch_past_page=false
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prefetch_serial_squash=false
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prefetch_latency=10
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prefetch_degree=1
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prefetch_policy=none
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prefetch_cache_check_push=true
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prefetch_use_cpu_id=true
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prefetch_data_accesses_only=false
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hit_latency=1
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uid=100
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euid=100
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gid=100
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egid=100
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pid=100
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ppid=99
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[system.cpu.fuPool.FUList0.opList0]
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type=OpDesc
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@ -199,15 +170,16 @@ FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUL
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[system.cpu]
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type=DerivO3CPU
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clock=1
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phase=0
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numThreads=1
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activity=0
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workload=system.cpu.workload
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mem=system.cpu.dcache
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checker=null
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max_insts_any_thread=0
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max_insts_all_threads=0
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max_loads_any_thread=0
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max_loads_all_threads=0
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progress_interval=0
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cachePorts=200
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decodeToFetchDelay=1
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renameToFetchDelay=1
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@ -283,7 +255,44 @@ mshrs=10
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tgts_per_mshr=5
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write_buffers=8
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prioritizeRequests=false
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do_copy=false
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protocol=null
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trace_addr=0
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hash_delay=1
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repl=null
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compressed_bus=false
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store_compressed=false
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adaptive_compression=false
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compression_latency=0
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block_size=64
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max_miss_count=0
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addr_range=[0,18446744073709551615]
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split=false
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split_size=0
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lifo=false
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two_queue=false
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prefetch_miss=false
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prefetch_access=false
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prefetcher_size=100
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prefetch_past_page=false
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prefetch_serial_squash=false
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prefetch_latency=10
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prefetch_degree=1
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prefetch_policy=none
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prefetch_cache_check_push=true
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prefetch_use_cpu_id=true
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prefetch_data_accesses_only=false
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hit_latency=1
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[system.cpu.dcache]
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type=BaseCache
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size=262144
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assoc=2
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block_size=64
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latency=1
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mshrs=10
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tgts_per_mshr=5
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write_buffers=8
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prioritizeRequests=false
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protocol=null
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trace_addr=0
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hash_delay=1
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@ -322,7 +331,6 @@ mshrs=10
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tgts_per_mshr=5
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write_buffers=8
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prioritizeRequests=false
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do_copy=false
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protocol=null
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trace_addr=0
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hash_delay=1
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@ -354,10 +362,14 @@ hit_latency=1
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[system.cpu.toL2Bus]
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type=Bus
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bus_id=0
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clock=1000
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width=64
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responder_set=false
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[trace]
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flags=
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start=0
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cycle=0
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bufsize=0
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file=cout
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dump_on_exit=false
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@ -396,8 +408,9 @@ print_cpseq=false
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print_reg_delta=false
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pc_symbol=true
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intel_format=false
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legion_lockstep=false
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trace_system=client
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[debug]
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break_cycles=
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[statsreset]
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reset_cycle=0
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File diff suppressed because it is too large
Load diff
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@ -1,3 +1 @@
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warn: Entering event queue @ 0. Starting simulation...
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warn: cycle 0: fault (page_table_fault) detected @ PC 0x000000
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warn: Increasing stack 0x11ff92000:0x11ff9b000 to 0x11ff90000:0x11ff9b000 because of access to 0x11ff91ff0
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@ -1,13 +1,31 @@
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Hello world!
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M5 Simulator System
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Copyright (c) 2001-2006
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The Regents of The University of Michigan
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All Rights Reserved
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M5 compiled Sep 5 2006 15:28:48
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M5 started Tue Sep 5 15:42:12 2006
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M5 executing on zizzer.eecs.umich.edu
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command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/o3-timing tests/run.py quick/00.hello/alpha/linux/o3-timing
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Exiting @ tick 6870 because target called exit()
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spec_init
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Loading Input Data
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Duplicating 262144 bytes
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Duplicating 524288 bytes
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Input data 1048576 bytes in length
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Compressing Input Data, level 1
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Compressed data 108074 bytes in length
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Uncompressing Data
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Uncompressed data 1048576 bytes in length
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Uncompressed data compared correctly
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Compressing Input Data, level 3
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Compressed data 97831 bytes in length
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Uncompressing Data
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Uncompressed data 1048576 bytes in length
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Uncompressed data compared correctly
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Compressing Input Data, level 5
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Compressed data 83382 bytes in length
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Uncompressing Data
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Uncompressed data 1048576 bytes in length
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Uncompressed data compared correctly
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Compressing Input Data, level 7
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Compressed data 76606 bytes in length
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Uncompressing Data
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Uncompressed data 1048576 bytes in length
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Uncompressed data compared correctly
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Compressing Input Data, level 9
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Compressed data 73189 bytes in length
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Uncompressing Data
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Uncompressed data 1048576 bytes in length
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Uncompressed data compared correctly
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Tested 1MB buffer: OK!
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|
|
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@ -7,11 +7,9 @@ max_tick=0
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output_file=cout
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progress_interval=0
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[debug]
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break_cycles=
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|
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[exetrace]
|
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intel_format=false
|
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legion_lockstep=false
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pc_symbol=true
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print_cpseq=false
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print_cycle=true
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|
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@ -53,352 +51,49 @@ mem_mode=atomic
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physmem=system.physmem
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[system.cpu]
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type=DerivO3CPU
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children=dcache fuPool icache l2cache toL2Bus workload
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BTBEntries=4096
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BTBTagSize=16
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LFSTSize=1024
|
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LQEntries=32
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RASSize=16
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SQEntries=32
|
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SSITSize=1024
|
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activity=0
|
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backComSize=5
|
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choiceCtrBits=2
|
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choicePredictorSize=8192
|
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type=AtomicSimpleCPU
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children=workload
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clock=1
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commitToDecodeDelay=1
|
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commitToFetchDelay=1
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commitToIEWDelay=1
|
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commitToRenameDelay=1
|
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commitWidth=8
|
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decodeToFetchDelay=1
|
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decodeToRenameDelay=1
|
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decodeWidth=8
|
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cpu_id=0
|
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defer_registration=false
|
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dispatchWidth=8
|
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fetchToDecodeDelay=1
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fetchTrapLatency=1
|
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fetchWidth=8
|
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forwardComSize=5
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fuPool=system.cpu.fuPool
|
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function_trace=false
|
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function_trace_start=0
|
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globalCtrBits=2
|
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globalHistoryBits=13
|
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globalPredictorSize=8192
|
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iewToCommitDelay=1
|
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iewToDecodeDelay=1
|
||||
iewToFetchDelay=1
|
||||
iewToRenameDelay=1
|
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instShiftAmt=2
|
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issueToExecuteDelay=1
|
||||
issueWidth=8
|
||||
localCtrBits=2
|
||||
localHistoryBits=11
|
||||
localHistoryTableSize=2048
|
||||
localPredictorSize=2048
|
||||
max_insts_all_threads=0
|
||||
max_insts_any_thread=0
|
||||
max_loads_all_threads=0
|
||||
max_loads_any_thread=0
|
||||
mem=system.cpu.dcache
|
||||
numIQEntries=64
|
||||
numPhysFloatRegs=256
|
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numPhysIntRegs=256
|
||||
numROBEntries=192
|
||||
numRobs=1
|
||||
numThreads=1
|
||||
predType=tournament
|
||||
renameToDecodeDelay=1
|
||||
renameToFetchDelay=1
|
||||
renameToIEWDelay=2
|
||||
renameToROBDelay=1
|
||||
renameWidth=8
|
||||
squashWidth=8
|
||||
phase=0
|
||||
progress_interval=0
|
||||
simulate_stalls=false
|
||||
system=system
|
||||
trapLatency=13
|
||||
wbDepth=1
|
||||
wbWidth=8
|
||||
width=1
|
||||
workload=system.cpu.workload
|
||||
dcache_port=system.cpu.dcache.cpu_side
|
||||
icache_port=system.cpu.icache.cpu_side
|
||||
|
||||
[system.cpu.dcache]
|
||||
type=BaseCache
|
||||
adaptive_compression=false
|
||||
assoc=2
|
||||
block_size=64
|
||||
compressed_bus=false
|
||||
compression_latency=0
|
||||
do_copy=false
|
||||
hash_delay=1
|
||||
hit_latency=1
|
||||
latency=1
|
||||
lifo=false
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
prefetch_access=false
|
||||
prefetch_cache_check_push=true
|
||||
prefetch_data_accesses_only=false
|
||||
prefetch_degree=1
|
||||
prefetch_latency=10
|
||||
prefetch_miss=false
|
||||
prefetch_past_page=false
|
||||
prefetch_policy=none
|
||||
prefetch_serial_squash=false
|
||||
prefetch_use_cpu_id=true
|
||||
prefetcher_size=100
|
||||
prioritizeRequests=false
|
||||
protocol=Null
|
||||
repl=Null
|
||||
size=262144
|
||||
split=false
|
||||
split_size=0
|
||||
store_compressed=false
|
||||
subblock_size=0
|
||||
tgts_per_mshr=5
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu.dcache_port
|
||||
mem_side=system.cpu.toL2Bus.port[1]
|
||||
|
||||
[system.cpu.fuPool]
|
||||
type=FUPool
|
||||
children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7
|
||||
FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7
|
||||
|
||||
[system.cpu.fuPool.FUList0]
|
||||
type=FUDesc
|
||||
children=opList0
|
||||
count=6
|
||||
opList=system.cpu.fuPool.FUList0.opList0
|
||||
|
||||
[system.cpu.fuPool.FUList0.opList0]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=IntAlu
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList1]
|
||||
type=FUDesc
|
||||
children=opList0 opList1
|
||||
count=2
|
||||
opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
|
||||
|
||||
[system.cpu.fuPool.FUList1.opList0]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=IntMult
|
||||
opLat=3
|
||||
|
||||
[system.cpu.fuPool.FUList1.opList1]
|
||||
type=OpDesc
|
||||
issueLat=19
|
||||
opClass=IntDiv
|
||||
opLat=20
|
||||
|
||||
[system.cpu.fuPool.FUList2]
|
||||
type=FUDesc
|
||||
children=opList0 opList1 opList2
|
||||
count=4
|
||||
opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
|
||||
|
||||
[system.cpu.fuPool.FUList2.opList0]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=FloatAdd
|
||||
opLat=2
|
||||
|
||||
[system.cpu.fuPool.FUList2.opList1]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=FloatCmp
|
||||
opLat=2
|
||||
|
||||
[system.cpu.fuPool.FUList2.opList2]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=FloatCvt
|
||||
opLat=2
|
||||
|
||||
[system.cpu.fuPool.FUList3]
|
||||
type=FUDesc
|
||||
children=opList0 opList1 opList2
|
||||
count=2
|
||||
opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
|
||||
|
||||
[system.cpu.fuPool.FUList3.opList0]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=FloatMult
|
||||
opLat=4
|
||||
|
||||
[system.cpu.fuPool.FUList3.opList1]
|
||||
type=OpDesc
|
||||
issueLat=12
|
||||
opClass=FloatDiv
|
||||
opLat=12
|
||||
|
||||
[system.cpu.fuPool.FUList3.opList2]
|
||||
type=OpDesc
|
||||
issueLat=24
|
||||
opClass=FloatSqrt
|
||||
opLat=24
|
||||
|
||||
[system.cpu.fuPool.FUList4]
|
||||
type=FUDesc
|
||||
children=opList0
|
||||
count=0
|
||||
opList=system.cpu.fuPool.FUList4.opList0
|
||||
|
||||
[system.cpu.fuPool.FUList4.opList0]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=MemRead
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5]
|
||||
type=FUDesc
|
||||
children=opList0
|
||||
count=0
|
||||
opList=system.cpu.fuPool.FUList5.opList0
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList0]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=MemWrite
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList6]
|
||||
type=FUDesc
|
||||
children=opList0 opList1
|
||||
count=4
|
||||
opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1
|
||||
|
||||
[system.cpu.fuPool.FUList6.opList0]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=MemRead
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList6.opList1]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=MemWrite
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList7]
|
||||
type=FUDesc
|
||||
children=opList0
|
||||
count=1
|
||||
opList=system.cpu.fuPool.FUList7.opList0
|
||||
|
||||
[system.cpu.fuPool.FUList7.opList0]
|
||||
type=OpDesc
|
||||
issueLat=3
|
||||
opClass=IprAccess
|
||||
opLat=3
|
||||
|
||||
[system.cpu.icache]
|
||||
type=BaseCache
|
||||
adaptive_compression=false
|
||||
assoc=2
|
||||
block_size=64
|
||||
compressed_bus=false
|
||||
compression_latency=0
|
||||
do_copy=false
|
||||
hash_delay=1
|
||||
hit_latency=1
|
||||
latency=1
|
||||
lifo=false
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
prefetch_access=false
|
||||
prefetch_cache_check_push=true
|
||||
prefetch_data_accesses_only=false
|
||||
prefetch_degree=1
|
||||
prefetch_latency=10
|
||||
prefetch_miss=false
|
||||
prefetch_past_page=false
|
||||
prefetch_policy=none
|
||||
prefetch_serial_squash=false
|
||||
prefetch_use_cpu_id=true
|
||||
prefetcher_size=100
|
||||
prioritizeRequests=false
|
||||
protocol=Null
|
||||
repl=Null
|
||||
size=131072
|
||||
split=false
|
||||
split_size=0
|
||||
store_compressed=false
|
||||
subblock_size=0
|
||||
tgts_per_mshr=5
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu.icache_port
|
||||
mem_side=system.cpu.toL2Bus.port[0]
|
||||
|
||||
[system.cpu.l2cache]
|
||||
type=BaseCache
|
||||
adaptive_compression=false
|
||||
assoc=2
|
||||
block_size=64
|
||||
compressed_bus=false
|
||||
compression_latency=0
|
||||
do_copy=false
|
||||
hash_delay=1
|
||||
hit_latency=1
|
||||
latency=1
|
||||
lifo=false
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
prefetch_access=false
|
||||
prefetch_cache_check_push=true
|
||||
prefetch_data_accesses_only=false
|
||||
prefetch_degree=1
|
||||
prefetch_latency=10
|
||||
prefetch_miss=false
|
||||
prefetch_past_page=false
|
||||
prefetch_policy=none
|
||||
prefetch_serial_squash=false
|
||||
prefetch_use_cpu_id=true
|
||||
prefetcher_size=100
|
||||
prioritizeRequests=false
|
||||
protocol=Null
|
||||
repl=Null
|
||||
size=2097152
|
||||
split=false
|
||||
split_size=0
|
||||
store_compressed=false
|
||||
subblock_size=0
|
||||
tgts_per_mshr=5
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu.toL2Bus.port[2]
|
||||
mem_side=system.membus.port[1]
|
||||
|
||||
[system.cpu.toL2Bus]
|
||||
type=Bus
|
||||
bus_id=0
|
||||
port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
|
||||
dcache_port=system.membus.port[2]
|
||||
icache_port=system.membus.port[1]
|
||||
|
||||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
cmd=hello
|
||||
cmd=gzip input.log 1
|
||||
cwd=build/ALPHA_SE/tests/opt/long/00.gzip/alpha/linux/simple-atomic
|
||||
egid=100
|
||||
env=
|
||||
executable=tests/test-progs/hello/bin/alpha/linux/hello
|
||||
euid=100
|
||||
executable=/dist/m5/cpu2000/binaries/alpha/tru64/gzip
|
||||
gid=100
|
||||
input=cin
|
||||
output=cout
|
||||
pid=100
|
||||
ppid=99
|
||||
system=system
|
||||
uid=100
|
||||
|
||||
[system.membus]
|
||||
type=Bus
|
||||
bus_id=0
|
||||
port=system.physmem.port system.cpu.l2cache.mem_side
|
||||
clock=1000
|
||||
responder_set=false
|
||||
width=64
|
||||
port=system.physmem.port system.cpu.icache_port system.cpu.dcache_port
|
||||
|
||||
[system.physmem]
|
||||
type=PhysicalMemory
|
||||
|
|
@ -409,6 +104,7 @@ port=system.membus.port[0]
|
|||
|
||||
[trace]
|
||||
bufsize=0
|
||||
cycle=0
|
||||
dump_on_exit=false
|
||||
file=cout
|
||||
flags=
|
||||
|
|
|
|||
|
|
@ -19,345 +19,48 @@ mem_mode=atomic
|
|||
[system.membus]
|
||||
type=Bus
|
||||
bus_id=0
|
||||
clock=1000
|
||||
width=64
|
||||
responder_set=false
|
||||
|
||||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
cmd=hello
|
||||
executable=tests/test-progs/hello/bin/alpha/linux/hello
|
||||
cmd=gzip input.log 1
|
||||
executable=/dist/m5/cpu2000/binaries/alpha/tru64/gzip
|
||||
input=cin
|
||||
output=cout
|
||||
env=
|
||||
cwd=build/ALPHA_SE/tests/opt/long/00.gzip/alpha/linux/simple-atomic
|
||||
system=system
|
||||
|
||||
[system.cpu.dcache]
|
||||
type=BaseCache
|
||||
size=262144
|
||||
assoc=2
|
||||
block_size=64
|
||||
latency=1
|
||||
mshrs=10
|
||||
tgts_per_mshr=5
|
||||
write_buffers=8
|
||||
prioritizeRequests=false
|
||||
do_copy=false
|
||||
protocol=null
|
||||
trace_addr=0
|
||||
hash_delay=1
|
||||
repl=null
|
||||
compressed_bus=false
|
||||
store_compressed=false
|
||||
adaptive_compression=false
|
||||
compression_latency=0
|
||||
block_size=64
|
||||
max_miss_count=0
|
||||
addr_range=[0,18446744073709551615]
|
||||
split=false
|
||||
split_size=0
|
||||
lifo=false
|
||||
two_queue=false
|
||||
prefetch_miss=false
|
||||
prefetch_access=false
|
||||
prefetcher_size=100
|
||||
prefetch_past_page=false
|
||||
prefetch_serial_squash=false
|
||||
prefetch_latency=10
|
||||
prefetch_degree=1
|
||||
prefetch_policy=none
|
||||
prefetch_cache_check_push=true
|
||||
prefetch_use_cpu_id=true
|
||||
prefetch_data_accesses_only=false
|
||||
hit_latency=1
|
||||
|
||||
[system.cpu.fuPool.FUList0.opList0]
|
||||
type=OpDesc
|
||||
opClass=IntAlu
|
||||
opLat=1
|
||||
issueLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList0]
|
||||
type=FUDesc
|
||||
opList=system.cpu.fuPool.FUList0.opList0
|
||||
count=6
|
||||
|
||||
[system.cpu.fuPool.FUList1.opList0]
|
||||
type=OpDesc
|
||||
opClass=IntMult
|
||||
opLat=3
|
||||
issueLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList1.opList1]
|
||||
type=OpDesc
|
||||
opClass=IntDiv
|
||||
opLat=20
|
||||
issueLat=19
|
||||
|
||||
[system.cpu.fuPool.FUList1]
|
||||
type=FUDesc
|
||||
opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
|
||||
count=2
|
||||
|
||||
[system.cpu.fuPool.FUList2.opList0]
|
||||
type=OpDesc
|
||||
opClass=FloatAdd
|
||||
opLat=2
|
||||
issueLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList2.opList1]
|
||||
type=OpDesc
|
||||
opClass=FloatCmp
|
||||
opLat=2
|
||||
issueLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList2.opList2]
|
||||
type=OpDesc
|
||||
opClass=FloatCvt
|
||||
opLat=2
|
||||
issueLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList2]
|
||||
type=FUDesc
|
||||
opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
|
||||
count=4
|
||||
|
||||
[system.cpu.fuPool.FUList3.opList0]
|
||||
type=OpDesc
|
||||
opClass=FloatMult
|
||||
opLat=4
|
||||
issueLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList3.opList1]
|
||||
type=OpDesc
|
||||
opClass=FloatDiv
|
||||
opLat=12
|
||||
issueLat=12
|
||||
|
||||
[system.cpu.fuPool.FUList3.opList2]
|
||||
type=OpDesc
|
||||
opClass=FloatSqrt
|
||||
opLat=24
|
||||
issueLat=24
|
||||
|
||||
[system.cpu.fuPool.FUList3]
|
||||
type=FUDesc
|
||||
opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
|
||||
count=2
|
||||
|
||||
[system.cpu.fuPool.FUList4.opList0]
|
||||
type=OpDesc
|
||||
opClass=MemRead
|
||||
opLat=1
|
||||
issueLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList4]
|
||||
type=FUDesc
|
||||
opList=system.cpu.fuPool.FUList4.opList0
|
||||
count=0
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList0]
|
||||
type=OpDesc
|
||||
opClass=MemWrite
|
||||
opLat=1
|
||||
issueLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5]
|
||||
type=FUDesc
|
||||
opList=system.cpu.fuPool.FUList5.opList0
|
||||
count=0
|
||||
|
||||
[system.cpu.fuPool.FUList6.opList0]
|
||||
type=OpDesc
|
||||
opClass=MemRead
|
||||
opLat=1
|
||||
issueLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList6.opList1]
|
||||
type=OpDesc
|
||||
opClass=MemWrite
|
||||
opLat=1
|
||||
issueLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList6]
|
||||
type=FUDesc
|
||||
opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1
|
||||
count=4
|
||||
|
||||
[system.cpu.fuPool.FUList7.opList0]
|
||||
type=OpDesc
|
||||
opClass=IprAccess
|
||||
opLat=3
|
||||
issueLat=3
|
||||
|
||||
[system.cpu.fuPool.FUList7]
|
||||
type=FUDesc
|
||||
opList=system.cpu.fuPool.FUList7.opList0
|
||||
count=1
|
||||
|
||||
[system.cpu.fuPool]
|
||||
type=FUPool
|
||||
FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7
|
||||
uid=100
|
||||
euid=100
|
||||
gid=100
|
||||
egid=100
|
||||
pid=100
|
||||
ppid=99
|
||||
|
||||
[system.cpu]
|
||||
type=DerivO3CPU
|
||||
clock=1
|
||||
numThreads=1
|
||||
activity=0
|
||||
workload=system.cpu.workload
|
||||
mem=system.cpu.dcache
|
||||
checker=null
|
||||
type=AtomicSimpleCPU
|
||||
max_insts_any_thread=0
|
||||
max_insts_all_threads=0
|
||||
max_loads_any_thread=0
|
||||
max_loads_all_threads=0
|
||||
cachePorts=200
|
||||
decodeToFetchDelay=1
|
||||
renameToFetchDelay=1
|
||||
iewToFetchDelay=1
|
||||
commitToFetchDelay=1
|
||||
fetchWidth=8
|
||||
renameToDecodeDelay=1
|
||||
iewToDecodeDelay=1
|
||||
commitToDecodeDelay=1
|
||||
fetchToDecodeDelay=1
|
||||
decodeWidth=8
|
||||
iewToRenameDelay=1
|
||||
commitToRenameDelay=1
|
||||
decodeToRenameDelay=1
|
||||
renameWidth=8
|
||||
commitToIEWDelay=1
|
||||
renameToIEWDelay=2
|
||||
issueToExecuteDelay=1
|
||||
dispatchWidth=8
|
||||
issueWidth=8
|
||||
wbWidth=8
|
||||
wbDepth=1
|
||||
fuPool=system.cpu.fuPool
|
||||
iewToCommitDelay=1
|
||||
renameToROBDelay=1
|
||||
commitWidth=8
|
||||
squashWidth=8
|
||||
trapLatency=13
|
||||
backComSize=5
|
||||
forwardComSize=5
|
||||
predType=tournament
|
||||
localPredictorSize=2048
|
||||
localCtrBits=2
|
||||
localHistoryTableSize=2048
|
||||
localHistoryBits=11
|
||||
globalPredictorSize=8192
|
||||
globalCtrBits=2
|
||||
globalHistoryBits=13
|
||||
choicePredictorSize=8192
|
||||
choiceCtrBits=2
|
||||
BTBEntries=4096
|
||||
BTBTagSize=16
|
||||
RASSize=16
|
||||
LQEntries=32
|
||||
SQEntries=32
|
||||
LFSTSize=1024
|
||||
SSITSize=1024
|
||||
numPhysIntRegs=256
|
||||
numPhysFloatRegs=256
|
||||
numIQEntries=64
|
||||
numROBEntries=192
|
||||
smtNumFetchingThreads=1
|
||||
smtFetchPolicy=SingleThread
|
||||
smtLSQPolicy=Partitioned
|
||||
smtLSQThreshold=100
|
||||
smtIQPolicy=Partitioned
|
||||
smtIQThreshold=100
|
||||
smtROBPolicy=Partitioned
|
||||
smtROBThreshold=100
|
||||
smtCommitPolicy=RoundRobin
|
||||
instShiftAmt=2
|
||||
progress_interval=0
|
||||
system=system
|
||||
cpu_id=0
|
||||
workload=system.cpu.workload
|
||||
clock=1
|
||||
phase=0
|
||||
defer_registration=false
|
||||
width=1
|
||||
function_trace=false
|
||||
function_trace_start=0
|
||||
|
||||
[system.cpu.icache]
|
||||
type=BaseCache
|
||||
size=131072
|
||||
assoc=2
|
||||
block_size=64
|
||||
latency=1
|
||||
mshrs=10
|
||||
tgts_per_mshr=5
|
||||
write_buffers=8
|
||||
prioritizeRequests=false
|
||||
do_copy=false
|
||||
protocol=null
|
||||
trace_addr=0
|
||||
hash_delay=1
|
||||
repl=null
|
||||
compressed_bus=false
|
||||
store_compressed=false
|
||||
adaptive_compression=false
|
||||
compression_latency=0
|
||||
block_size=64
|
||||
max_miss_count=0
|
||||
addr_range=[0,18446744073709551615]
|
||||
split=false
|
||||
split_size=0
|
||||
lifo=false
|
||||
two_queue=false
|
||||
prefetch_miss=false
|
||||
prefetch_access=false
|
||||
prefetcher_size=100
|
||||
prefetch_past_page=false
|
||||
prefetch_serial_squash=false
|
||||
prefetch_latency=10
|
||||
prefetch_degree=1
|
||||
prefetch_policy=none
|
||||
prefetch_cache_check_push=true
|
||||
prefetch_use_cpu_id=true
|
||||
prefetch_data_accesses_only=false
|
||||
hit_latency=1
|
||||
|
||||
[system.cpu.l2cache]
|
||||
type=BaseCache
|
||||
size=2097152
|
||||
assoc=2
|
||||
block_size=64
|
||||
latency=1
|
||||
mshrs=10
|
||||
tgts_per_mshr=5
|
||||
write_buffers=8
|
||||
prioritizeRequests=false
|
||||
do_copy=false
|
||||
protocol=null
|
||||
trace_addr=0
|
||||
hash_delay=1
|
||||
repl=null
|
||||
compressed_bus=false
|
||||
store_compressed=false
|
||||
adaptive_compression=false
|
||||
compression_latency=0
|
||||
block_size=64
|
||||
max_miss_count=0
|
||||
addr_range=[0,18446744073709551615]
|
||||
split=false
|
||||
split_size=0
|
||||
lifo=false
|
||||
two_queue=false
|
||||
prefetch_miss=false
|
||||
prefetch_access=false
|
||||
prefetcher_size=100
|
||||
prefetch_past_page=false
|
||||
prefetch_serial_squash=false
|
||||
prefetch_latency=10
|
||||
prefetch_degree=1
|
||||
prefetch_policy=none
|
||||
prefetch_cache_check_push=true
|
||||
prefetch_use_cpu_id=true
|
||||
prefetch_data_accesses_only=false
|
||||
hit_latency=1
|
||||
|
||||
[system.cpu.toL2Bus]
|
||||
type=Bus
|
||||
bus_id=0
|
||||
simulate_stalls=false
|
||||
|
||||
[trace]
|
||||
flags=
|
||||
start=0
|
||||
cycle=0
|
||||
bufsize=0
|
||||
file=cout
|
||||
dump_on_exit=false
|
||||
|
|
@ -396,8 +99,9 @@ print_cpseq=false
|
|||
print_reg_delta=false
|
||||
pc_symbol=true
|
||||
intel_format=false
|
||||
legion_lockstep=false
|
||||
trace_system=client
|
||||
|
||||
[debug]
|
||||
break_cycles=
|
||||
[statsreset]
|
||||
reset_cycle=0
|
||||
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -1,3 +1 @@
|
|||
warn: Entering event queue @ 0. Starting simulation...
|
||||
warn: cycle 0: fault (page_table_fault) detected @ PC 0x000000
|
||||
warn: Increasing stack 0x11ff92000:0x11ff9b000 to 0x11ff90000:0x11ff9b000 because of access to 0x11ff91ff0
|
||||
|
|
|
|||
|
|
@ -1,13 +1,31 @@
|
|||
Hello world!
|
||||
M5 Simulator System
|
||||
|
||||
Copyright (c) 2001-2006
|
||||
The Regents of The University of Michigan
|
||||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Sep 5 2006 15:28:48
|
||||
M5 started Tue Sep 5 15:42:12 2006
|
||||
M5 executing on zizzer.eecs.umich.edu
|
||||
command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/o3-timing tests/run.py quick/00.hello/alpha/linux/o3-timing
|
||||
Exiting @ tick 6870 because target called exit()
|
||||
spec_init
|
||||
Loading Input Data
|
||||
Duplicating 262144 bytes
|
||||
Duplicating 524288 bytes
|
||||
Input data 1048576 bytes in length
|
||||
Compressing Input Data, level 1
|
||||
Compressed data 108074 bytes in length
|
||||
Uncompressing Data
|
||||
Uncompressed data 1048576 bytes in length
|
||||
Uncompressed data compared correctly
|
||||
Compressing Input Data, level 3
|
||||
Compressed data 97831 bytes in length
|
||||
Uncompressing Data
|
||||
Uncompressed data 1048576 bytes in length
|
||||
Uncompressed data compared correctly
|
||||
Compressing Input Data, level 5
|
||||
Compressed data 83382 bytes in length
|
||||
Uncompressing Data
|
||||
Uncompressed data 1048576 bytes in length
|
||||
Uncompressed data compared correctly
|
||||
Compressing Input Data, level 7
|
||||
Compressed data 76606 bytes in length
|
||||
Uncompressing Data
|
||||
Uncompressed data 1048576 bytes in length
|
||||
Uncompressed data compared correctly
|
||||
Compressing Input Data, level 9
|
||||
Compressed data 73189 bytes in length
|
||||
Uncompressing Data
|
||||
Uncompressed data 1048576 bytes in length
|
||||
Uncompressed data compared correctly
|
||||
Tested 1MB buffer: OK!
|
||||
|
|
|
|||
|
|
@ -7,11 +7,9 @@ max_tick=0
|
|||
output_file=cout
|
||||
progress_interval=0
|
||||
|
||||
[debug]
|
||||
break_cycles=
|
||||
|
||||
[exetrace]
|
||||
intel_format=false
|
||||
legion_lockstep=false
|
||||
pc_symbol=true
|
||||
print_cpseq=false
|
||||
print_cycle=true
|
||||
|
|
@ -53,73 +51,20 @@ mem_mode=atomic
|
|||
physmem=system.physmem
|
||||
|
||||
[system.cpu]
|
||||
type=DerivO3CPU
|
||||
children=dcache fuPool icache l2cache toL2Bus workload
|
||||
BTBEntries=4096
|
||||
BTBTagSize=16
|
||||
LFSTSize=1024
|
||||
LQEntries=32
|
||||
RASSize=16
|
||||
SQEntries=32
|
||||
SSITSize=1024
|
||||
activity=0
|
||||
backComSize=5
|
||||
choiceCtrBits=2
|
||||
choicePredictorSize=8192
|
||||
type=TimingSimpleCPU
|
||||
children=dcache icache l2cache toL2Bus workload
|
||||
clock=1
|
||||
commitToDecodeDelay=1
|
||||
commitToFetchDelay=1
|
||||
commitToIEWDelay=1
|
||||
commitToRenameDelay=1
|
||||
commitWidth=8
|
||||
decodeToFetchDelay=1
|
||||
decodeToRenameDelay=1
|
||||
decodeWidth=8
|
||||
cpu_id=0
|
||||
defer_registration=false
|
||||
dispatchWidth=8
|
||||
fetchToDecodeDelay=1
|
||||
fetchTrapLatency=1
|
||||
fetchWidth=8
|
||||
forwardComSize=5
|
||||
fuPool=system.cpu.fuPool
|
||||
function_trace=false
|
||||
function_trace_start=0
|
||||
globalCtrBits=2
|
||||
globalHistoryBits=13
|
||||
globalPredictorSize=8192
|
||||
iewToCommitDelay=1
|
||||
iewToDecodeDelay=1
|
||||
iewToFetchDelay=1
|
||||
iewToRenameDelay=1
|
||||
instShiftAmt=2
|
||||
issueToExecuteDelay=1
|
||||
issueWidth=8
|
||||
localCtrBits=2
|
||||
localHistoryBits=11
|
||||
localHistoryTableSize=2048
|
||||
localPredictorSize=2048
|
||||
max_insts_all_threads=0
|
||||
max_insts_any_thread=0
|
||||
max_loads_all_threads=0
|
||||
max_loads_any_thread=0
|
||||
mem=system.cpu.dcache
|
||||
numIQEntries=64
|
||||
numPhysFloatRegs=256
|
||||
numPhysIntRegs=256
|
||||
numROBEntries=192
|
||||
numRobs=1
|
||||
numThreads=1
|
||||
predType=tournament
|
||||
renameToDecodeDelay=1
|
||||
renameToFetchDelay=1
|
||||
renameToIEWDelay=2
|
||||
renameToROBDelay=1
|
||||
renameWidth=8
|
||||
squashWidth=8
|
||||
phase=0
|
||||
progress_interval=0
|
||||
system=system
|
||||
trapLatency=13
|
||||
wbDepth=1
|
||||
wbWidth=8
|
||||
workload=system.cpu.workload
|
||||
dcache_port=system.cpu.dcache.cpu_side
|
||||
icache_port=system.cpu.icache.cpu_side
|
||||
|
|
@ -131,7 +76,6 @@ assoc=2
|
|||
block_size=64
|
||||
compressed_bus=false
|
||||
compression_latency=0
|
||||
do_copy=false
|
||||
hash_delay=1
|
||||
hit_latency=1
|
||||
latency=1
|
||||
|
|
@ -164,143 +108,6 @@ write_buffers=8
|
|||
cpu_side=system.cpu.dcache_port
|
||||
mem_side=system.cpu.toL2Bus.port[1]
|
||||
|
||||
[system.cpu.fuPool]
|
||||
type=FUPool
|
||||
children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7
|
||||
FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7
|
||||
|
||||
[system.cpu.fuPool.FUList0]
|
||||
type=FUDesc
|
||||
children=opList0
|
||||
count=6
|
||||
opList=system.cpu.fuPool.FUList0.opList0
|
||||
|
||||
[system.cpu.fuPool.FUList0.opList0]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=IntAlu
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList1]
|
||||
type=FUDesc
|
||||
children=opList0 opList1
|
||||
count=2
|
||||
opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
|
||||
|
||||
[system.cpu.fuPool.FUList1.opList0]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=IntMult
|
||||
opLat=3
|
||||
|
||||
[system.cpu.fuPool.FUList1.opList1]
|
||||
type=OpDesc
|
||||
issueLat=19
|
||||
opClass=IntDiv
|
||||
opLat=20
|
||||
|
||||
[system.cpu.fuPool.FUList2]
|
||||
type=FUDesc
|
||||
children=opList0 opList1 opList2
|
||||
count=4
|
||||
opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
|
||||
|
||||
[system.cpu.fuPool.FUList2.opList0]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=FloatAdd
|
||||
opLat=2
|
||||
|
||||
[system.cpu.fuPool.FUList2.opList1]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=FloatCmp
|
||||
opLat=2
|
||||
|
||||
[system.cpu.fuPool.FUList2.opList2]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=FloatCvt
|
||||
opLat=2
|
||||
|
||||
[system.cpu.fuPool.FUList3]
|
||||
type=FUDesc
|
||||
children=opList0 opList1 opList2
|
||||
count=2
|
||||
opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
|
||||
|
||||
[system.cpu.fuPool.FUList3.opList0]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=FloatMult
|
||||
opLat=4
|
||||
|
||||
[system.cpu.fuPool.FUList3.opList1]
|
||||
type=OpDesc
|
||||
issueLat=12
|
||||
opClass=FloatDiv
|
||||
opLat=12
|
||||
|
||||
[system.cpu.fuPool.FUList3.opList2]
|
||||
type=OpDesc
|
||||
issueLat=24
|
||||
opClass=FloatSqrt
|
||||
opLat=24
|
||||
|
||||
[system.cpu.fuPool.FUList4]
|
||||
type=FUDesc
|
||||
children=opList0
|
||||
count=0
|
||||
opList=system.cpu.fuPool.FUList4.opList0
|
||||
|
||||
[system.cpu.fuPool.FUList4.opList0]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=MemRead
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5]
|
||||
type=FUDesc
|
||||
children=opList0
|
||||
count=0
|
||||
opList=system.cpu.fuPool.FUList5.opList0
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList0]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=MemWrite
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList6]
|
||||
type=FUDesc
|
||||
children=opList0 opList1
|
||||
count=4
|
||||
opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1
|
||||
|
||||
[system.cpu.fuPool.FUList6.opList0]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=MemRead
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList6.opList1]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=MemWrite
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList7]
|
||||
type=FUDesc
|
||||
children=opList0
|
||||
count=1
|
||||
opList=system.cpu.fuPool.FUList7.opList0
|
||||
|
||||
[system.cpu.fuPool.FUList7.opList0]
|
||||
type=OpDesc
|
||||
issueLat=3
|
||||
opClass=IprAccess
|
||||
opLat=3
|
||||
|
||||
[system.cpu.icache]
|
||||
type=BaseCache
|
||||
adaptive_compression=false
|
||||
|
|
@ -308,7 +115,6 @@ assoc=2
|
|||
block_size=64
|
||||
compressed_bus=false
|
||||
compression_latency=0
|
||||
do_copy=false
|
||||
hash_delay=1
|
||||
hit_latency=1
|
||||
latency=1
|
||||
|
|
@ -348,7 +154,6 @@ assoc=2
|
|||
block_size=64
|
||||
compressed_bus=false
|
||||
compression_latency=0
|
||||
do_copy=false
|
||||
hash_delay=1
|
||||
hit_latency=1
|
||||
latency=1
|
||||
|
|
@ -384,20 +189,33 @@ mem_side=system.membus.port[1]
|
|||
[system.cpu.toL2Bus]
|
||||
type=Bus
|
||||
bus_id=0
|
||||
clock=1000
|
||||
responder_set=false
|
||||
width=64
|
||||
port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
|
||||
|
||||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
cmd=hello
|
||||
cmd=gzip input.log 1
|
||||
cwd=build/ALPHA_SE/tests/opt/long/00.gzip/alpha/linux/simple-timing
|
||||
egid=100
|
||||
env=
|
||||
executable=tests/test-progs/hello/bin/alpha/linux/hello
|
||||
euid=100
|
||||
executable=/dist/m5/cpu2000/binaries/alpha/tru64/gzip
|
||||
gid=100
|
||||
input=cin
|
||||
output=cout
|
||||
pid=100
|
||||
ppid=99
|
||||
system=system
|
||||
uid=100
|
||||
|
||||
[system.membus]
|
||||
type=Bus
|
||||
bus_id=0
|
||||
clock=1000
|
||||
responder_set=false
|
||||
width=64
|
||||
port=system.physmem.port system.cpu.l2cache.mem_side
|
||||
|
||||
[system.physmem]
|
||||
|
|
@ -409,6 +227,7 @@ port=system.membus.port[0]
|
|||
|
||||
[trace]
|
||||
bufsize=0
|
||||
cycle=0
|
||||
dump_on_exit=false
|
||||
file=cout
|
||||
flags=
|
||||
|
|
|
|||
|
|
@ -19,19 +19,54 @@ mem_mode=atomic
|
|||
[system.membus]
|
||||
type=Bus
|
||||
bus_id=0
|
||||
clock=1000
|
||||
width=64
|
||||
responder_set=false
|
||||
|
||||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
cmd=hello
|
||||
executable=tests/test-progs/hello/bin/alpha/linux/hello
|
||||
cmd=gzip input.log 1
|
||||
executable=/dist/m5/cpu2000/binaries/alpha/tru64/gzip
|
||||
input=cin
|
||||
output=cout
|
||||
env=
|
||||
cwd=build/ALPHA_SE/tests/opt/long/00.gzip/alpha/linux/simple-timing
|
||||
system=system
|
||||
uid=100
|
||||
euid=100
|
||||
gid=100
|
||||
egid=100
|
||||
pid=100
|
||||
ppid=99
|
||||
|
||||
[system.cpu.dcache]
|
||||
[system.cpu]
|
||||
type=TimingSimpleCPU
|
||||
max_insts_any_thread=0
|
||||
max_insts_all_threads=0
|
||||
max_loads_any_thread=0
|
||||
max_loads_all_threads=0
|
||||
progress_interval=0
|
||||
system=system
|
||||
cpu_id=0
|
||||
workload=system.cpu.workload
|
||||
clock=1
|
||||
phase=0
|
||||
defer_registration=false
|
||||
// width not specified
|
||||
function_trace=false
|
||||
function_trace_start=0
|
||||
// simulate_stalls not specified
|
||||
|
||||
[system.cpu.toL2Bus]
|
||||
type=Bus
|
||||
bus_id=0
|
||||
clock=1000
|
||||
width=64
|
||||
responder_set=false
|
||||
|
||||
[system.cpu.icache]
|
||||
type=BaseCache
|
||||
size=262144
|
||||
size=131072
|
||||
assoc=2
|
||||
block_size=64
|
||||
latency=1
|
||||
|
|
@ -39,7 +74,6 @@ mshrs=10
|
|||
tgts_per_mshr=5
|
||||
write_buffers=8
|
||||
prioritizeRequests=false
|
||||
do_copy=false
|
||||
protocol=null
|
||||
trace_addr=0
|
||||
hash_delay=1
|
||||
|
|
@ -68,214 +102,9 @@ prefetch_use_cpu_id=true
|
|||
prefetch_data_accesses_only=false
|
||||
hit_latency=1
|
||||
|
||||
[system.cpu.fuPool.FUList0.opList0]
|
||||
type=OpDesc
|
||||
opClass=IntAlu
|
||||
opLat=1
|
||||
issueLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList0]
|
||||
type=FUDesc
|
||||
opList=system.cpu.fuPool.FUList0.opList0
|
||||
count=6
|
||||
|
||||
[system.cpu.fuPool.FUList1.opList0]
|
||||
type=OpDesc
|
||||
opClass=IntMult
|
||||
opLat=3
|
||||
issueLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList1.opList1]
|
||||
type=OpDesc
|
||||
opClass=IntDiv
|
||||
opLat=20
|
||||
issueLat=19
|
||||
|
||||
[system.cpu.fuPool.FUList1]
|
||||
type=FUDesc
|
||||
opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
|
||||
count=2
|
||||
|
||||
[system.cpu.fuPool.FUList2.opList0]
|
||||
type=OpDesc
|
||||
opClass=FloatAdd
|
||||
opLat=2
|
||||
issueLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList2.opList1]
|
||||
type=OpDesc
|
||||
opClass=FloatCmp
|
||||
opLat=2
|
||||
issueLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList2.opList2]
|
||||
type=OpDesc
|
||||
opClass=FloatCvt
|
||||
opLat=2
|
||||
issueLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList2]
|
||||
type=FUDesc
|
||||
opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
|
||||
count=4
|
||||
|
||||
[system.cpu.fuPool.FUList3.opList0]
|
||||
type=OpDesc
|
||||
opClass=FloatMult
|
||||
opLat=4
|
||||
issueLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList3.opList1]
|
||||
type=OpDesc
|
||||
opClass=FloatDiv
|
||||
opLat=12
|
||||
issueLat=12
|
||||
|
||||
[system.cpu.fuPool.FUList3.opList2]
|
||||
type=OpDesc
|
||||
opClass=FloatSqrt
|
||||
opLat=24
|
||||
issueLat=24
|
||||
|
||||
[system.cpu.fuPool.FUList3]
|
||||
type=FUDesc
|
||||
opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
|
||||
count=2
|
||||
|
||||
[system.cpu.fuPool.FUList4.opList0]
|
||||
type=OpDesc
|
||||
opClass=MemRead
|
||||
opLat=1
|
||||
issueLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList4]
|
||||
type=FUDesc
|
||||
opList=system.cpu.fuPool.FUList4.opList0
|
||||
count=0
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList0]
|
||||
type=OpDesc
|
||||
opClass=MemWrite
|
||||
opLat=1
|
||||
issueLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5]
|
||||
type=FUDesc
|
||||
opList=system.cpu.fuPool.FUList5.opList0
|
||||
count=0
|
||||
|
||||
[system.cpu.fuPool.FUList6.opList0]
|
||||
type=OpDesc
|
||||
opClass=MemRead
|
||||
opLat=1
|
||||
issueLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList6.opList1]
|
||||
type=OpDesc
|
||||
opClass=MemWrite
|
||||
opLat=1
|
||||
issueLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList6]
|
||||
type=FUDesc
|
||||
opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1
|
||||
count=4
|
||||
|
||||
[system.cpu.fuPool.FUList7.opList0]
|
||||
type=OpDesc
|
||||
opClass=IprAccess
|
||||
opLat=3
|
||||
issueLat=3
|
||||
|
||||
[system.cpu.fuPool.FUList7]
|
||||
type=FUDesc
|
||||
opList=system.cpu.fuPool.FUList7.opList0
|
||||
count=1
|
||||
|
||||
[system.cpu.fuPool]
|
||||
type=FUPool
|
||||
FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7
|
||||
|
||||
[system.cpu]
|
||||
type=DerivO3CPU
|
||||
clock=1
|
||||
numThreads=1
|
||||
activity=0
|
||||
workload=system.cpu.workload
|
||||
mem=system.cpu.dcache
|
||||
checker=null
|
||||
max_insts_any_thread=0
|
||||
max_insts_all_threads=0
|
||||
max_loads_any_thread=0
|
||||
max_loads_all_threads=0
|
||||
cachePorts=200
|
||||
decodeToFetchDelay=1
|
||||
renameToFetchDelay=1
|
||||
iewToFetchDelay=1
|
||||
commitToFetchDelay=1
|
||||
fetchWidth=8
|
||||
renameToDecodeDelay=1
|
||||
iewToDecodeDelay=1
|
||||
commitToDecodeDelay=1
|
||||
fetchToDecodeDelay=1
|
||||
decodeWidth=8
|
||||
iewToRenameDelay=1
|
||||
commitToRenameDelay=1
|
||||
decodeToRenameDelay=1
|
||||
renameWidth=8
|
||||
commitToIEWDelay=1
|
||||
renameToIEWDelay=2
|
||||
issueToExecuteDelay=1
|
||||
dispatchWidth=8
|
||||
issueWidth=8
|
||||
wbWidth=8
|
||||
wbDepth=1
|
||||
fuPool=system.cpu.fuPool
|
||||
iewToCommitDelay=1
|
||||
renameToROBDelay=1
|
||||
commitWidth=8
|
||||
squashWidth=8
|
||||
trapLatency=13
|
||||
backComSize=5
|
||||
forwardComSize=5
|
||||
predType=tournament
|
||||
localPredictorSize=2048
|
||||
localCtrBits=2
|
||||
localHistoryTableSize=2048
|
||||
localHistoryBits=11
|
||||
globalPredictorSize=8192
|
||||
globalCtrBits=2
|
||||
globalHistoryBits=13
|
||||
choicePredictorSize=8192
|
||||
choiceCtrBits=2
|
||||
BTBEntries=4096
|
||||
BTBTagSize=16
|
||||
RASSize=16
|
||||
LQEntries=32
|
||||
SQEntries=32
|
||||
LFSTSize=1024
|
||||
SSITSize=1024
|
||||
numPhysIntRegs=256
|
||||
numPhysFloatRegs=256
|
||||
numIQEntries=64
|
||||
numROBEntries=192
|
||||
smtNumFetchingThreads=1
|
||||
smtFetchPolicy=SingleThread
|
||||
smtLSQPolicy=Partitioned
|
||||
smtLSQThreshold=100
|
||||
smtIQPolicy=Partitioned
|
||||
smtIQThreshold=100
|
||||
smtROBPolicy=Partitioned
|
||||
smtROBThreshold=100
|
||||
smtCommitPolicy=RoundRobin
|
||||
instShiftAmt=2
|
||||
defer_registration=false
|
||||
function_trace=false
|
||||
function_trace_start=0
|
||||
|
||||
[system.cpu.icache]
|
||||
[system.cpu.dcache]
|
||||
type=BaseCache
|
||||
size=131072
|
||||
size=262144
|
||||
assoc=2
|
||||
block_size=64
|
||||
latency=1
|
||||
|
|
@ -283,7 +112,6 @@ mshrs=10
|
|||
tgts_per_mshr=5
|
||||
write_buffers=8
|
||||
prioritizeRequests=false
|
||||
do_copy=false
|
||||
protocol=null
|
||||
trace_addr=0
|
||||
hash_delay=1
|
||||
|
|
@ -322,7 +150,6 @@ mshrs=10
|
|||
tgts_per_mshr=5
|
||||
write_buffers=8
|
||||
prioritizeRequests=false
|
||||
do_copy=false
|
||||
protocol=null
|
||||
trace_addr=0
|
||||
hash_delay=1
|
||||
|
|
@ -351,13 +178,10 @@ prefetch_use_cpu_id=true
|
|||
prefetch_data_accesses_only=false
|
||||
hit_latency=1
|
||||
|
||||
[system.cpu.toL2Bus]
|
||||
type=Bus
|
||||
bus_id=0
|
||||
|
||||
[trace]
|
||||
flags=
|
||||
start=0
|
||||
cycle=0
|
||||
bufsize=0
|
||||
file=cout
|
||||
dump_on_exit=false
|
||||
|
|
@ -396,8 +220,9 @@ print_cpseq=false
|
|||
print_reg_delta=false
|
||||
pc_symbol=true
|
||||
intel_format=false
|
||||
legion_lockstep=false
|
||||
trace_system=client
|
||||
|
||||
[debug]
|
||||
break_cycles=
|
||||
[statsreset]
|
||||
reset_cycle=0
|
||||
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -1,3 +1 @@
|
|||
warn: Entering event queue @ 0. Starting simulation...
|
||||
warn: cycle 0: fault (page_table_fault) detected @ PC 0x000000
|
||||
warn: Increasing stack 0x11ff92000:0x11ff9b000 to 0x11ff90000:0x11ff9b000 because of access to 0x11ff91ff0
|
||||
|
|
|
|||
|
|
@ -1,13 +1,31 @@
|
|||
Hello world!
|
||||
M5 Simulator System
|
||||
|
||||
Copyright (c) 2001-2006
|
||||
The Regents of The University of Michigan
|
||||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Sep 5 2006 15:28:48
|
||||
M5 started Tue Sep 5 15:42:12 2006
|
||||
M5 executing on zizzer.eecs.umich.edu
|
||||
command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/o3-timing tests/run.py quick/00.hello/alpha/linux/o3-timing
|
||||
Exiting @ tick 6870 because target called exit()
|
||||
spec_init
|
||||
Loading Input Data
|
||||
Duplicating 262144 bytes
|
||||
Duplicating 524288 bytes
|
||||
Input data 1048576 bytes in length
|
||||
Compressing Input Data, level 1
|
||||
Compressed data 108074 bytes in length
|
||||
Uncompressing Data
|
||||
Uncompressed data 1048576 bytes in length
|
||||
Uncompressed data compared correctly
|
||||
Compressing Input Data, level 3
|
||||
Compressed data 97831 bytes in length
|
||||
Uncompressing Data
|
||||
Uncompressed data 1048576 bytes in length
|
||||
Uncompressed data compared correctly
|
||||
Compressing Input Data, level 5
|
||||
Compressed data 83382 bytes in length
|
||||
Uncompressing Data
|
||||
Uncompressed data 1048576 bytes in length
|
||||
Uncompressed data compared correctly
|
||||
Compressing Input Data, level 7
|
||||
Compressed data 76606 bytes in length
|
||||
Uncompressing Data
|
||||
Uncompressed data 1048576 bytes in length
|
||||
Uncompressed data compared correctly
|
||||
Compressing Input Data, level 9
|
||||
Compressed data 73189 bytes in length
|
||||
Uncompressing Data
|
||||
Uncompressed data 1048576 bytes in length
|
||||
Uncompressed data compared correctly
|
||||
Tested 1MB buffer: OK!
|
||||
|
|
|
|||
|
|
@ -7,11 +7,9 @@ max_tick=0
|
|||
output_file=cout
|
||||
progress_interval=0
|
||||
|
||||
[debug]
|
||||
break_cycles=
|
||||
|
||||
[exetrace]
|
||||
intel_format=false
|
||||
legion_lockstep=false
|
||||
pc_symbol=true
|
||||
print_cpseq=false
|
||||
print_cycle=true
|
||||
|
|
@ -53,352 +51,49 @@ mem_mode=atomic
|
|||
physmem=system.physmem
|
||||
|
||||
[system.cpu]
|
||||
type=DerivO3CPU
|
||||
children=dcache fuPool icache l2cache toL2Bus workload
|
||||
BTBEntries=4096
|
||||
BTBTagSize=16
|
||||
LFSTSize=1024
|
||||
LQEntries=32
|
||||
RASSize=16
|
||||
SQEntries=32
|
||||
SSITSize=1024
|
||||
activity=0
|
||||
backComSize=5
|
||||
choiceCtrBits=2
|
||||
choicePredictorSize=8192
|
||||
type=AtomicSimpleCPU
|
||||
children=workload
|
||||
clock=1
|
||||
commitToDecodeDelay=1
|
||||
commitToFetchDelay=1
|
||||
commitToIEWDelay=1
|
||||
commitToRenameDelay=1
|
||||
commitWidth=8
|
||||
decodeToFetchDelay=1
|
||||
decodeToRenameDelay=1
|
||||
decodeWidth=8
|
||||
cpu_id=0
|
||||
defer_registration=false
|
||||
dispatchWidth=8
|
||||
fetchToDecodeDelay=1
|
||||
fetchTrapLatency=1
|
||||
fetchWidth=8
|
||||
forwardComSize=5
|
||||
fuPool=system.cpu.fuPool
|
||||
function_trace=false
|
||||
function_trace_start=0
|
||||
globalCtrBits=2
|
||||
globalHistoryBits=13
|
||||
globalPredictorSize=8192
|
||||
iewToCommitDelay=1
|
||||
iewToDecodeDelay=1
|
||||
iewToFetchDelay=1
|
||||
iewToRenameDelay=1
|
||||
instShiftAmt=2
|
||||
issueToExecuteDelay=1
|
||||
issueWidth=8
|
||||
localCtrBits=2
|
||||
localHistoryBits=11
|
||||
localHistoryTableSize=2048
|
||||
localPredictorSize=2048
|
||||
max_insts_all_threads=0
|
||||
max_insts_any_thread=0
|
||||
max_loads_all_threads=0
|
||||
max_loads_any_thread=0
|
||||
mem=system.cpu.dcache
|
||||
numIQEntries=64
|
||||
numPhysFloatRegs=256
|
||||
numPhysIntRegs=256
|
||||
numROBEntries=192
|
||||
numRobs=1
|
||||
numThreads=1
|
||||
predType=tournament
|
||||
renameToDecodeDelay=1
|
||||
renameToFetchDelay=1
|
||||
renameToIEWDelay=2
|
||||
renameToROBDelay=1
|
||||
renameWidth=8
|
||||
squashWidth=8
|
||||
phase=0
|
||||
progress_interval=0
|
||||
simulate_stalls=false
|
||||
system=system
|
||||
trapLatency=13
|
||||
wbDepth=1
|
||||
wbWidth=8
|
||||
width=1
|
||||
workload=system.cpu.workload
|
||||
dcache_port=system.cpu.dcache.cpu_side
|
||||
icache_port=system.cpu.icache.cpu_side
|
||||
|
||||
[system.cpu.dcache]
|
||||
type=BaseCache
|
||||
adaptive_compression=false
|
||||
assoc=2
|
||||
block_size=64
|
||||
compressed_bus=false
|
||||
compression_latency=0
|
||||
do_copy=false
|
||||
hash_delay=1
|
||||
hit_latency=1
|
||||
latency=1
|
||||
lifo=false
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
prefetch_access=false
|
||||
prefetch_cache_check_push=true
|
||||
prefetch_data_accesses_only=false
|
||||
prefetch_degree=1
|
||||
prefetch_latency=10
|
||||
prefetch_miss=false
|
||||
prefetch_past_page=false
|
||||
prefetch_policy=none
|
||||
prefetch_serial_squash=false
|
||||
prefetch_use_cpu_id=true
|
||||
prefetcher_size=100
|
||||
prioritizeRequests=false
|
||||
protocol=Null
|
||||
repl=Null
|
||||
size=262144
|
||||
split=false
|
||||
split_size=0
|
||||
store_compressed=false
|
||||
subblock_size=0
|
||||
tgts_per_mshr=5
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu.dcache_port
|
||||
mem_side=system.cpu.toL2Bus.port[1]
|
||||
|
||||
[system.cpu.fuPool]
|
||||
type=FUPool
|
||||
children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7
|
||||
FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7
|
||||
|
||||
[system.cpu.fuPool.FUList0]
|
||||
type=FUDesc
|
||||
children=opList0
|
||||
count=6
|
||||
opList=system.cpu.fuPool.FUList0.opList0
|
||||
|
||||
[system.cpu.fuPool.FUList0.opList0]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=IntAlu
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList1]
|
||||
type=FUDesc
|
||||
children=opList0 opList1
|
||||
count=2
|
||||
opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
|
||||
|
||||
[system.cpu.fuPool.FUList1.opList0]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=IntMult
|
||||
opLat=3
|
||||
|
||||
[system.cpu.fuPool.FUList1.opList1]
|
||||
type=OpDesc
|
||||
issueLat=19
|
||||
opClass=IntDiv
|
||||
opLat=20
|
||||
|
||||
[system.cpu.fuPool.FUList2]
|
||||
type=FUDesc
|
||||
children=opList0 opList1 opList2
|
||||
count=4
|
||||
opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
|
||||
|
||||
[system.cpu.fuPool.FUList2.opList0]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=FloatAdd
|
||||
opLat=2
|
||||
|
||||
[system.cpu.fuPool.FUList2.opList1]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=FloatCmp
|
||||
opLat=2
|
||||
|
||||
[system.cpu.fuPool.FUList2.opList2]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=FloatCvt
|
||||
opLat=2
|
||||
|
||||
[system.cpu.fuPool.FUList3]
|
||||
type=FUDesc
|
||||
children=opList0 opList1 opList2
|
||||
count=2
|
||||
opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
|
||||
|
||||
[system.cpu.fuPool.FUList3.opList0]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=FloatMult
|
||||
opLat=4
|
||||
|
||||
[system.cpu.fuPool.FUList3.opList1]
|
||||
type=OpDesc
|
||||
issueLat=12
|
||||
opClass=FloatDiv
|
||||
opLat=12
|
||||
|
||||
[system.cpu.fuPool.FUList3.opList2]
|
||||
type=OpDesc
|
||||
issueLat=24
|
||||
opClass=FloatSqrt
|
||||
opLat=24
|
||||
|
||||
[system.cpu.fuPool.FUList4]
|
||||
type=FUDesc
|
||||
children=opList0
|
||||
count=0
|
||||
opList=system.cpu.fuPool.FUList4.opList0
|
||||
|
||||
[system.cpu.fuPool.FUList4.opList0]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=MemRead
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5]
|
||||
type=FUDesc
|
||||
children=opList0
|
||||
count=0
|
||||
opList=system.cpu.fuPool.FUList5.opList0
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList0]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=MemWrite
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList6]
|
||||
type=FUDesc
|
||||
children=opList0 opList1
|
||||
count=4
|
||||
opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1
|
||||
|
||||
[system.cpu.fuPool.FUList6.opList0]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=MemRead
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList6.opList1]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=MemWrite
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList7]
|
||||
type=FUDesc
|
||||
children=opList0
|
||||
count=1
|
||||
opList=system.cpu.fuPool.FUList7.opList0
|
||||
|
||||
[system.cpu.fuPool.FUList7.opList0]
|
||||
type=OpDesc
|
||||
issueLat=3
|
||||
opClass=IprAccess
|
||||
opLat=3
|
||||
|
||||
[system.cpu.icache]
|
||||
type=BaseCache
|
||||
adaptive_compression=false
|
||||
assoc=2
|
||||
block_size=64
|
||||
compressed_bus=false
|
||||
compression_latency=0
|
||||
do_copy=false
|
||||
hash_delay=1
|
||||
hit_latency=1
|
||||
latency=1
|
||||
lifo=false
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
prefetch_access=false
|
||||
prefetch_cache_check_push=true
|
||||
prefetch_data_accesses_only=false
|
||||
prefetch_degree=1
|
||||
prefetch_latency=10
|
||||
prefetch_miss=false
|
||||
prefetch_past_page=false
|
||||
prefetch_policy=none
|
||||
prefetch_serial_squash=false
|
||||
prefetch_use_cpu_id=true
|
||||
prefetcher_size=100
|
||||
prioritizeRequests=false
|
||||
protocol=Null
|
||||
repl=Null
|
||||
size=131072
|
||||
split=false
|
||||
split_size=0
|
||||
store_compressed=false
|
||||
subblock_size=0
|
||||
tgts_per_mshr=5
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu.icache_port
|
||||
mem_side=system.cpu.toL2Bus.port[0]
|
||||
|
||||
[system.cpu.l2cache]
|
||||
type=BaseCache
|
||||
adaptive_compression=false
|
||||
assoc=2
|
||||
block_size=64
|
||||
compressed_bus=false
|
||||
compression_latency=0
|
||||
do_copy=false
|
||||
hash_delay=1
|
||||
hit_latency=1
|
||||
latency=1
|
||||
lifo=false
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
prefetch_access=false
|
||||
prefetch_cache_check_push=true
|
||||
prefetch_data_accesses_only=false
|
||||
prefetch_degree=1
|
||||
prefetch_latency=10
|
||||
prefetch_miss=false
|
||||
prefetch_past_page=false
|
||||
prefetch_policy=none
|
||||
prefetch_serial_squash=false
|
||||
prefetch_use_cpu_id=true
|
||||
prefetcher_size=100
|
||||
prioritizeRequests=false
|
||||
protocol=Null
|
||||
repl=Null
|
||||
size=2097152
|
||||
split=false
|
||||
split_size=0
|
||||
store_compressed=false
|
||||
subblock_size=0
|
||||
tgts_per_mshr=5
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu.toL2Bus.port[2]
|
||||
mem_side=system.membus.port[1]
|
||||
|
||||
[system.cpu.toL2Bus]
|
||||
type=Bus
|
||||
bus_id=0
|
||||
port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
|
||||
dcache_port=system.membus.port[2]
|
||||
icache_port=system.membus.port[1]
|
||||
|
||||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
cmd=hello
|
||||
cmd=eon chair.control.cook chair.camera chair.surfaces chair.cook.ppm ppm pixels_out.cook
|
||||
cwd=build/ALPHA_SE/tests/opt/long/30.eon/alpha/linux/simple-atomic
|
||||
egid=100
|
||||
env=
|
||||
executable=tests/test-progs/hello/bin/alpha/linux/hello
|
||||
euid=100
|
||||
executable=/dist/m5/cpu2000/binaries/alpha/tru64/eon
|
||||
gid=100
|
||||
input=cin
|
||||
output=cout
|
||||
pid=100
|
||||
ppid=99
|
||||
system=system
|
||||
uid=100
|
||||
|
||||
[system.membus]
|
||||
type=Bus
|
||||
bus_id=0
|
||||
port=system.physmem.port system.cpu.l2cache.mem_side
|
||||
clock=1000
|
||||
responder_set=false
|
||||
width=64
|
||||
port=system.physmem.port system.cpu.icache_port system.cpu.dcache_port
|
||||
|
||||
[system.physmem]
|
||||
type=PhysicalMemory
|
||||
|
|
@ -409,6 +104,7 @@ port=system.membus.port[0]
|
|||
|
||||
[trace]
|
||||
bufsize=0
|
||||
cycle=0
|
||||
dump_on_exit=false
|
||||
file=cout
|
||||
flags=
|
||||
|
|
|
|||
|
|
@ -19,345 +19,48 @@ mem_mode=atomic
|
|||
[system.membus]
|
||||
type=Bus
|
||||
bus_id=0
|
||||
clock=1000
|
||||
width=64
|
||||
responder_set=false
|
||||
|
||||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
cmd=hello
|
||||
executable=tests/test-progs/hello/bin/alpha/linux/hello
|
||||
cmd=eon chair.control.cook chair.camera chair.surfaces chair.cook.ppm ppm pixels_out.cook
|
||||
executable=/dist/m5/cpu2000/binaries/alpha/tru64/eon
|
||||
input=cin
|
||||
output=cout
|
||||
env=
|
||||
cwd=build/ALPHA_SE/tests/opt/long/30.eon/alpha/linux/simple-atomic
|
||||
system=system
|
||||
|
||||
[system.cpu.dcache]
|
||||
type=BaseCache
|
||||
size=262144
|
||||
assoc=2
|
||||
block_size=64
|
||||
latency=1
|
||||
mshrs=10
|
||||
tgts_per_mshr=5
|
||||
write_buffers=8
|
||||
prioritizeRequests=false
|
||||
do_copy=false
|
||||
protocol=null
|
||||
trace_addr=0
|
||||
hash_delay=1
|
||||
repl=null
|
||||
compressed_bus=false
|
||||
store_compressed=false
|
||||
adaptive_compression=false
|
||||
compression_latency=0
|
||||
block_size=64
|
||||
max_miss_count=0
|
||||
addr_range=[0,18446744073709551615]
|
||||
split=false
|
||||
split_size=0
|
||||
lifo=false
|
||||
two_queue=false
|
||||
prefetch_miss=false
|
||||
prefetch_access=false
|
||||
prefetcher_size=100
|
||||
prefetch_past_page=false
|
||||
prefetch_serial_squash=false
|
||||
prefetch_latency=10
|
||||
prefetch_degree=1
|
||||
prefetch_policy=none
|
||||
prefetch_cache_check_push=true
|
||||
prefetch_use_cpu_id=true
|
||||
prefetch_data_accesses_only=false
|
||||
hit_latency=1
|
||||
|
||||
[system.cpu.fuPool.FUList0.opList0]
|
||||
type=OpDesc
|
||||
opClass=IntAlu
|
||||
opLat=1
|
||||
issueLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList0]
|
||||
type=FUDesc
|
||||
opList=system.cpu.fuPool.FUList0.opList0
|
||||
count=6
|
||||
|
||||
[system.cpu.fuPool.FUList1.opList0]
|
||||
type=OpDesc
|
||||
opClass=IntMult
|
||||
opLat=3
|
||||
issueLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList1.opList1]
|
||||
type=OpDesc
|
||||
opClass=IntDiv
|
||||
opLat=20
|
||||
issueLat=19
|
||||
|
||||
[system.cpu.fuPool.FUList1]
|
||||
type=FUDesc
|
||||
opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
|
||||
count=2
|
||||
|
||||
[system.cpu.fuPool.FUList2.opList0]
|
||||
type=OpDesc
|
||||
opClass=FloatAdd
|
||||
opLat=2
|
||||
issueLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList2.opList1]
|
||||
type=OpDesc
|
||||
opClass=FloatCmp
|
||||
opLat=2
|
||||
issueLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList2.opList2]
|
||||
type=OpDesc
|
||||
opClass=FloatCvt
|
||||
opLat=2
|
||||
issueLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList2]
|
||||
type=FUDesc
|
||||
opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
|
||||
count=4
|
||||
|
||||
[system.cpu.fuPool.FUList3.opList0]
|
||||
type=OpDesc
|
||||
opClass=FloatMult
|
||||
opLat=4
|
||||
issueLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList3.opList1]
|
||||
type=OpDesc
|
||||
opClass=FloatDiv
|
||||
opLat=12
|
||||
issueLat=12
|
||||
|
||||
[system.cpu.fuPool.FUList3.opList2]
|
||||
type=OpDesc
|
||||
opClass=FloatSqrt
|
||||
opLat=24
|
||||
issueLat=24
|
||||
|
||||
[system.cpu.fuPool.FUList3]
|
||||
type=FUDesc
|
||||
opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
|
||||
count=2
|
||||
|
||||
[system.cpu.fuPool.FUList4.opList0]
|
||||
type=OpDesc
|
||||
opClass=MemRead
|
||||
opLat=1
|
||||
issueLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList4]
|
||||
type=FUDesc
|
||||
opList=system.cpu.fuPool.FUList4.opList0
|
||||
count=0
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList0]
|
||||
type=OpDesc
|
||||
opClass=MemWrite
|
||||
opLat=1
|
||||
issueLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5]
|
||||
type=FUDesc
|
||||
opList=system.cpu.fuPool.FUList5.opList0
|
||||
count=0
|
||||
|
||||
[system.cpu.fuPool.FUList6.opList0]
|
||||
type=OpDesc
|
||||
opClass=MemRead
|
||||
opLat=1
|
||||
issueLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList6.opList1]
|
||||
type=OpDesc
|
||||
opClass=MemWrite
|
||||
opLat=1
|
||||
issueLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList6]
|
||||
type=FUDesc
|
||||
opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1
|
||||
count=4
|
||||
|
||||
[system.cpu.fuPool.FUList7.opList0]
|
||||
type=OpDesc
|
||||
opClass=IprAccess
|
||||
opLat=3
|
||||
issueLat=3
|
||||
|
||||
[system.cpu.fuPool.FUList7]
|
||||
type=FUDesc
|
||||
opList=system.cpu.fuPool.FUList7.opList0
|
||||
count=1
|
||||
|
||||
[system.cpu.fuPool]
|
||||
type=FUPool
|
||||
FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7
|
||||
uid=100
|
||||
euid=100
|
||||
gid=100
|
||||
egid=100
|
||||
pid=100
|
||||
ppid=99
|
||||
|
||||
[system.cpu]
|
||||
type=DerivO3CPU
|
||||
clock=1
|
||||
numThreads=1
|
||||
activity=0
|
||||
workload=system.cpu.workload
|
||||
mem=system.cpu.dcache
|
||||
checker=null
|
||||
type=AtomicSimpleCPU
|
||||
max_insts_any_thread=0
|
||||
max_insts_all_threads=0
|
||||
max_loads_any_thread=0
|
||||
max_loads_all_threads=0
|
||||
cachePorts=200
|
||||
decodeToFetchDelay=1
|
||||
renameToFetchDelay=1
|
||||
iewToFetchDelay=1
|
||||
commitToFetchDelay=1
|
||||
fetchWidth=8
|
||||
renameToDecodeDelay=1
|
||||
iewToDecodeDelay=1
|
||||
commitToDecodeDelay=1
|
||||
fetchToDecodeDelay=1
|
||||
decodeWidth=8
|
||||
iewToRenameDelay=1
|
||||
commitToRenameDelay=1
|
||||
decodeToRenameDelay=1
|
||||
renameWidth=8
|
||||
commitToIEWDelay=1
|
||||
renameToIEWDelay=2
|
||||
issueToExecuteDelay=1
|
||||
dispatchWidth=8
|
||||
issueWidth=8
|
||||
wbWidth=8
|
||||
wbDepth=1
|
||||
fuPool=system.cpu.fuPool
|
||||
iewToCommitDelay=1
|
||||
renameToROBDelay=1
|
||||
commitWidth=8
|
||||
squashWidth=8
|
||||
trapLatency=13
|
||||
backComSize=5
|
||||
forwardComSize=5
|
||||
predType=tournament
|
||||
localPredictorSize=2048
|
||||
localCtrBits=2
|
||||
localHistoryTableSize=2048
|
||||
localHistoryBits=11
|
||||
globalPredictorSize=8192
|
||||
globalCtrBits=2
|
||||
globalHistoryBits=13
|
||||
choicePredictorSize=8192
|
||||
choiceCtrBits=2
|
||||
BTBEntries=4096
|
||||
BTBTagSize=16
|
||||
RASSize=16
|
||||
LQEntries=32
|
||||
SQEntries=32
|
||||
LFSTSize=1024
|
||||
SSITSize=1024
|
||||
numPhysIntRegs=256
|
||||
numPhysFloatRegs=256
|
||||
numIQEntries=64
|
||||
numROBEntries=192
|
||||
smtNumFetchingThreads=1
|
||||
smtFetchPolicy=SingleThread
|
||||
smtLSQPolicy=Partitioned
|
||||
smtLSQThreshold=100
|
||||
smtIQPolicy=Partitioned
|
||||
smtIQThreshold=100
|
||||
smtROBPolicy=Partitioned
|
||||
smtROBThreshold=100
|
||||
smtCommitPolicy=RoundRobin
|
||||
instShiftAmt=2
|
||||
progress_interval=0
|
||||
system=system
|
||||
cpu_id=0
|
||||
workload=system.cpu.workload
|
||||
clock=1
|
||||
phase=0
|
||||
defer_registration=false
|
||||
width=1
|
||||
function_trace=false
|
||||
function_trace_start=0
|
||||
|
||||
[system.cpu.icache]
|
||||
type=BaseCache
|
||||
size=131072
|
||||
assoc=2
|
||||
block_size=64
|
||||
latency=1
|
||||
mshrs=10
|
||||
tgts_per_mshr=5
|
||||
write_buffers=8
|
||||
prioritizeRequests=false
|
||||
do_copy=false
|
||||
protocol=null
|
||||
trace_addr=0
|
||||
hash_delay=1
|
||||
repl=null
|
||||
compressed_bus=false
|
||||
store_compressed=false
|
||||
adaptive_compression=false
|
||||
compression_latency=0
|
||||
block_size=64
|
||||
max_miss_count=0
|
||||
addr_range=[0,18446744073709551615]
|
||||
split=false
|
||||
split_size=0
|
||||
lifo=false
|
||||
two_queue=false
|
||||
prefetch_miss=false
|
||||
prefetch_access=false
|
||||
prefetcher_size=100
|
||||
prefetch_past_page=false
|
||||
prefetch_serial_squash=false
|
||||
prefetch_latency=10
|
||||
prefetch_degree=1
|
||||
prefetch_policy=none
|
||||
prefetch_cache_check_push=true
|
||||
prefetch_use_cpu_id=true
|
||||
prefetch_data_accesses_only=false
|
||||
hit_latency=1
|
||||
|
||||
[system.cpu.l2cache]
|
||||
type=BaseCache
|
||||
size=2097152
|
||||
assoc=2
|
||||
block_size=64
|
||||
latency=1
|
||||
mshrs=10
|
||||
tgts_per_mshr=5
|
||||
write_buffers=8
|
||||
prioritizeRequests=false
|
||||
do_copy=false
|
||||
protocol=null
|
||||
trace_addr=0
|
||||
hash_delay=1
|
||||
repl=null
|
||||
compressed_bus=false
|
||||
store_compressed=false
|
||||
adaptive_compression=false
|
||||
compression_latency=0
|
||||
block_size=64
|
||||
max_miss_count=0
|
||||
addr_range=[0,18446744073709551615]
|
||||
split=false
|
||||
split_size=0
|
||||
lifo=false
|
||||
two_queue=false
|
||||
prefetch_miss=false
|
||||
prefetch_access=false
|
||||
prefetcher_size=100
|
||||
prefetch_past_page=false
|
||||
prefetch_serial_squash=false
|
||||
prefetch_latency=10
|
||||
prefetch_degree=1
|
||||
prefetch_policy=none
|
||||
prefetch_cache_check_push=true
|
||||
prefetch_use_cpu_id=true
|
||||
prefetch_data_accesses_only=false
|
||||
hit_latency=1
|
||||
|
||||
[system.cpu.toL2Bus]
|
||||
type=Bus
|
||||
bus_id=0
|
||||
simulate_stalls=false
|
||||
|
||||
[trace]
|
||||
flags=
|
||||
start=0
|
||||
cycle=0
|
||||
bufsize=0
|
||||
file=cout
|
||||
dump_on_exit=false
|
||||
|
|
@ -396,8 +99,9 @@ print_cpseq=false
|
|||
print_reg_delta=false
|
||||
pc_symbol=true
|
||||
intel_format=false
|
||||
legion_lockstep=false
|
||||
trace_system=client
|
||||
|
||||
[debug]
|
||||
break_cycles=
|
||||
[statsreset]
|
||||
reset_cycle=0
|
||||
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -1,3 +1,47 @@
|
|||
warn: Entering event queue @ 0. Starting simulation...
|
||||
warn: cycle 0: fault (page_table_fault) detected @ PC 0x000000
|
||||
warn: Increasing stack 0x11ff92000:0x11ff9b000 to 0x11ff90000:0x11ff9b000 because of access to 0x11ff91ff0
|
||||
getting pixel output filename pixels_out.cook
|
||||
opening control file chair.control.cook
|
||||
opening camera file chair.camera
|
||||
opening surfaces file chair.surfaces
|
||||
reading data
|
||||
processing 8parts
|
||||
Grid measure is 6 by 3.0001 by 6
|
||||
cell dimension is 0.863065
|
||||
Creating grid for list of length 21
|
||||
Grid size = 7 by 4 by 7
|
||||
Total occupancy = 236
|
||||
reading control stream
|
||||
reading camera stream
|
||||
Writing to chair.cook.ppm
|
||||
calculating 15 by 15 image with 196 samples
|
||||
col 0. . .
|
||||
col 1. . .
|
||||
col 2. . .
|
||||
col 3. . .
|
||||
col 4. . .
|
||||
col 5. . .
|
||||
col 6. . .
|
||||
col 7. . .
|
||||
col 8. . .
|
||||
col 9. . .
|
||||
col 10. . .
|
||||
col 11. . .
|
||||
col 12. . .
|
||||
col 13. . .
|
||||
col 14. . .
|
||||
Writing to chair.cook.ppm
|
||||
0 8 14
|
||||
1 8 14
|
||||
2 8 14
|
||||
3 8 14
|
||||
4 8 14
|
||||
5 8 14
|
||||
6 8 14
|
||||
7 8 14
|
||||
8 8 14
|
||||
9 8 14
|
||||
10 8 14
|
||||
11 8 14
|
||||
12 8 14
|
||||
13 8 14
|
||||
14 8 14
|
||||
|
|
|
|||
|
|
@ -1,13 +1,2 @@
|
|||
Hello world!
|
||||
M5 Simulator System
|
||||
|
||||
Copyright (c) 2001-2006
|
||||
The Regents of The University of Michigan
|
||||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Sep 5 2006 15:28:48
|
||||
M5 started Tue Sep 5 15:42:12 2006
|
||||
M5 executing on zizzer.eecs.umich.edu
|
||||
command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/o3-timing tests/run.py quick/00.hello/alpha/linux/o3-timing
|
||||
Exiting @ tick 6870 because target called exit()
|
||||
Eon, Version 1.1
|
||||
OO-style eon Time= 0.000000
|
||||
|
|
|
|||
|
|
@ -7,11 +7,9 @@ max_tick=0
|
|||
output_file=cout
|
||||
progress_interval=0
|
||||
|
||||
[debug]
|
||||
break_cycles=
|
||||
|
||||
[exetrace]
|
||||
intel_format=false
|
||||
legion_lockstep=false
|
||||
pc_symbol=true
|
||||
print_cpseq=false
|
||||
print_cycle=true
|
||||
|
|
@ -53,73 +51,20 @@ mem_mode=atomic
|
|||
physmem=system.physmem
|
||||
|
||||
[system.cpu]
|
||||
type=DerivO3CPU
|
||||
children=dcache fuPool icache l2cache toL2Bus workload
|
||||
BTBEntries=4096
|
||||
BTBTagSize=16
|
||||
LFSTSize=1024
|
||||
LQEntries=32
|
||||
RASSize=16
|
||||
SQEntries=32
|
||||
SSITSize=1024
|
||||
activity=0
|
||||
backComSize=5
|
||||
choiceCtrBits=2
|
||||
choicePredictorSize=8192
|
||||
type=TimingSimpleCPU
|
||||
children=dcache icache l2cache toL2Bus workload
|
||||
clock=1
|
||||
commitToDecodeDelay=1
|
||||
commitToFetchDelay=1
|
||||
commitToIEWDelay=1
|
||||
commitToRenameDelay=1
|
||||
commitWidth=8
|
||||
decodeToFetchDelay=1
|
||||
decodeToRenameDelay=1
|
||||
decodeWidth=8
|
||||
cpu_id=0
|
||||
defer_registration=false
|
||||
dispatchWidth=8
|
||||
fetchToDecodeDelay=1
|
||||
fetchTrapLatency=1
|
||||
fetchWidth=8
|
||||
forwardComSize=5
|
||||
fuPool=system.cpu.fuPool
|
||||
function_trace=false
|
||||
function_trace_start=0
|
||||
globalCtrBits=2
|
||||
globalHistoryBits=13
|
||||
globalPredictorSize=8192
|
||||
iewToCommitDelay=1
|
||||
iewToDecodeDelay=1
|
||||
iewToFetchDelay=1
|
||||
iewToRenameDelay=1
|
||||
instShiftAmt=2
|
||||
issueToExecuteDelay=1
|
||||
issueWidth=8
|
||||
localCtrBits=2
|
||||
localHistoryBits=11
|
||||
localHistoryTableSize=2048
|
||||
localPredictorSize=2048
|
||||
max_insts_all_threads=0
|
||||
max_insts_any_thread=0
|
||||
max_loads_all_threads=0
|
||||
max_loads_any_thread=0
|
||||
mem=system.cpu.dcache
|
||||
numIQEntries=64
|
||||
numPhysFloatRegs=256
|
||||
numPhysIntRegs=256
|
||||
numROBEntries=192
|
||||
numRobs=1
|
||||
numThreads=1
|
||||
predType=tournament
|
||||
renameToDecodeDelay=1
|
||||
renameToFetchDelay=1
|
||||
renameToIEWDelay=2
|
||||
renameToROBDelay=1
|
||||
renameWidth=8
|
||||
squashWidth=8
|
||||
phase=0
|
||||
progress_interval=0
|
||||
system=system
|
||||
trapLatency=13
|
||||
wbDepth=1
|
||||
wbWidth=8
|
||||
workload=system.cpu.workload
|
||||
dcache_port=system.cpu.dcache.cpu_side
|
||||
icache_port=system.cpu.icache.cpu_side
|
||||
|
|
@ -131,7 +76,6 @@ assoc=2
|
|||
block_size=64
|
||||
compressed_bus=false
|
||||
compression_latency=0
|
||||
do_copy=false
|
||||
hash_delay=1
|
||||
hit_latency=1
|
||||
latency=1
|
||||
|
|
@ -164,143 +108,6 @@ write_buffers=8
|
|||
cpu_side=system.cpu.dcache_port
|
||||
mem_side=system.cpu.toL2Bus.port[1]
|
||||
|
||||
[system.cpu.fuPool]
|
||||
type=FUPool
|
||||
children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7
|
||||
FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7
|
||||
|
||||
[system.cpu.fuPool.FUList0]
|
||||
type=FUDesc
|
||||
children=opList0
|
||||
count=6
|
||||
opList=system.cpu.fuPool.FUList0.opList0
|
||||
|
||||
[system.cpu.fuPool.FUList0.opList0]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=IntAlu
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList1]
|
||||
type=FUDesc
|
||||
children=opList0 opList1
|
||||
count=2
|
||||
opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
|
||||
|
||||
[system.cpu.fuPool.FUList1.opList0]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=IntMult
|
||||
opLat=3
|
||||
|
||||
[system.cpu.fuPool.FUList1.opList1]
|
||||
type=OpDesc
|
||||
issueLat=19
|
||||
opClass=IntDiv
|
||||
opLat=20
|
||||
|
||||
[system.cpu.fuPool.FUList2]
|
||||
type=FUDesc
|
||||
children=opList0 opList1 opList2
|
||||
count=4
|
||||
opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
|
||||
|
||||
[system.cpu.fuPool.FUList2.opList0]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=FloatAdd
|
||||
opLat=2
|
||||
|
||||
[system.cpu.fuPool.FUList2.opList1]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=FloatCmp
|
||||
opLat=2
|
||||
|
||||
[system.cpu.fuPool.FUList2.opList2]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=FloatCvt
|
||||
opLat=2
|
||||
|
||||
[system.cpu.fuPool.FUList3]
|
||||
type=FUDesc
|
||||
children=opList0 opList1 opList2
|
||||
count=2
|
||||
opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
|
||||
|
||||
[system.cpu.fuPool.FUList3.opList0]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=FloatMult
|
||||
opLat=4
|
||||
|
||||
[system.cpu.fuPool.FUList3.opList1]
|
||||
type=OpDesc
|
||||
issueLat=12
|
||||
opClass=FloatDiv
|
||||
opLat=12
|
||||
|
||||
[system.cpu.fuPool.FUList3.opList2]
|
||||
type=OpDesc
|
||||
issueLat=24
|
||||
opClass=FloatSqrt
|
||||
opLat=24
|
||||
|
||||
[system.cpu.fuPool.FUList4]
|
||||
type=FUDesc
|
||||
children=opList0
|
||||
count=0
|
||||
opList=system.cpu.fuPool.FUList4.opList0
|
||||
|
||||
[system.cpu.fuPool.FUList4.opList0]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=MemRead
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5]
|
||||
type=FUDesc
|
||||
children=opList0
|
||||
count=0
|
||||
opList=system.cpu.fuPool.FUList5.opList0
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList0]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=MemWrite
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList6]
|
||||
type=FUDesc
|
||||
children=opList0 opList1
|
||||
count=4
|
||||
opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1
|
||||
|
||||
[system.cpu.fuPool.FUList6.opList0]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=MemRead
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList6.opList1]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=MemWrite
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList7]
|
||||
type=FUDesc
|
||||
children=opList0
|
||||
count=1
|
||||
opList=system.cpu.fuPool.FUList7.opList0
|
||||
|
||||
[system.cpu.fuPool.FUList7.opList0]
|
||||
type=OpDesc
|
||||
issueLat=3
|
||||
opClass=IprAccess
|
||||
opLat=3
|
||||
|
||||
[system.cpu.icache]
|
||||
type=BaseCache
|
||||
adaptive_compression=false
|
||||
|
|
@ -308,7 +115,6 @@ assoc=2
|
|||
block_size=64
|
||||
compressed_bus=false
|
||||
compression_latency=0
|
||||
do_copy=false
|
||||
hash_delay=1
|
||||
hit_latency=1
|
||||
latency=1
|
||||
|
|
@ -348,7 +154,6 @@ assoc=2
|
|||
block_size=64
|
||||
compressed_bus=false
|
||||
compression_latency=0
|
||||
do_copy=false
|
||||
hash_delay=1
|
||||
hit_latency=1
|
||||
latency=1
|
||||
|
|
@ -384,20 +189,33 @@ mem_side=system.membus.port[1]
|
|||
[system.cpu.toL2Bus]
|
||||
type=Bus
|
||||
bus_id=0
|
||||
clock=1000
|
||||
responder_set=false
|
||||
width=64
|
||||
port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
|
||||
|
||||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
cmd=hello
|
||||
cmd=eon chair.control.cook chair.camera chair.surfaces chair.cook.ppm ppm pixels_out.cook
|
||||
cwd=build/ALPHA_SE/tests/opt/long/30.eon/alpha/linux/simple-timing
|
||||
egid=100
|
||||
env=
|
||||
executable=tests/test-progs/hello/bin/alpha/linux/hello
|
||||
euid=100
|
||||
executable=/dist/m5/cpu2000/binaries/alpha/tru64/eon
|
||||
gid=100
|
||||
input=cin
|
||||
output=cout
|
||||
pid=100
|
||||
ppid=99
|
||||
system=system
|
||||
uid=100
|
||||
|
||||
[system.membus]
|
||||
type=Bus
|
||||
bus_id=0
|
||||
clock=1000
|
||||
responder_set=false
|
||||
width=64
|
||||
port=system.physmem.port system.cpu.l2cache.mem_side
|
||||
|
||||
[system.physmem]
|
||||
|
|
@ -409,6 +227,7 @@ port=system.membus.port[0]
|
|||
|
||||
[trace]
|
||||
bufsize=0
|
||||
cycle=0
|
||||
dump_on_exit=false
|
||||
file=cout
|
||||
flags=
|
||||
|
|
|
|||
|
|
@ -19,19 +19,54 @@ mem_mode=atomic
|
|||
[system.membus]
|
||||
type=Bus
|
||||
bus_id=0
|
||||
clock=1000
|
||||
width=64
|
||||
responder_set=false
|
||||
|
||||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
cmd=hello
|
||||
executable=tests/test-progs/hello/bin/alpha/linux/hello
|
||||
cmd=eon chair.control.cook chair.camera chair.surfaces chair.cook.ppm ppm pixels_out.cook
|
||||
executable=/dist/m5/cpu2000/binaries/alpha/tru64/eon
|
||||
input=cin
|
||||
output=cout
|
||||
env=
|
||||
cwd=build/ALPHA_SE/tests/opt/long/30.eon/alpha/linux/simple-timing
|
||||
system=system
|
||||
uid=100
|
||||
euid=100
|
||||
gid=100
|
||||
egid=100
|
||||
pid=100
|
||||
ppid=99
|
||||
|
||||
[system.cpu.dcache]
|
||||
[system.cpu]
|
||||
type=TimingSimpleCPU
|
||||
max_insts_any_thread=0
|
||||
max_insts_all_threads=0
|
||||
max_loads_any_thread=0
|
||||
max_loads_all_threads=0
|
||||
progress_interval=0
|
||||
system=system
|
||||
cpu_id=0
|
||||
workload=system.cpu.workload
|
||||
clock=1
|
||||
phase=0
|
||||
defer_registration=false
|
||||
// width not specified
|
||||
function_trace=false
|
||||
function_trace_start=0
|
||||
// simulate_stalls not specified
|
||||
|
||||
[system.cpu.toL2Bus]
|
||||
type=Bus
|
||||
bus_id=0
|
||||
clock=1000
|
||||
width=64
|
||||
responder_set=false
|
||||
|
||||
[system.cpu.icache]
|
||||
type=BaseCache
|
||||
size=262144
|
||||
size=131072
|
||||
assoc=2
|
||||
block_size=64
|
||||
latency=1
|
||||
|
|
@ -39,7 +74,6 @@ mshrs=10
|
|||
tgts_per_mshr=5
|
||||
write_buffers=8
|
||||
prioritizeRequests=false
|
||||
do_copy=false
|
||||
protocol=null
|
||||
trace_addr=0
|
||||
hash_delay=1
|
||||
|
|
@ -68,214 +102,9 @@ prefetch_use_cpu_id=true
|
|||
prefetch_data_accesses_only=false
|
||||
hit_latency=1
|
||||
|
||||
[system.cpu.fuPool.FUList0.opList0]
|
||||
type=OpDesc
|
||||
opClass=IntAlu
|
||||
opLat=1
|
||||
issueLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList0]
|
||||
type=FUDesc
|
||||
opList=system.cpu.fuPool.FUList0.opList0
|
||||
count=6
|
||||
|
||||
[system.cpu.fuPool.FUList1.opList0]
|
||||
type=OpDesc
|
||||
opClass=IntMult
|
||||
opLat=3
|
||||
issueLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList1.opList1]
|
||||
type=OpDesc
|
||||
opClass=IntDiv
|
||||
opLat=20
|
||||
issueLat=19
|
||||
|
||||
[system.cpu.fuPool.FUList1]
|
||||
type=FUDesc
|
||||
opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
|
||||
count=2
|
||||
|
||||
[system.cpu.fuPool.FUList2.opList0]
|
||||
type=OpDesc
|
||||
opClass=FloatAdd
|
||||
opLat=2
|
||||
issueLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList2.opList1]
|
||||
type=OpDesc
|
||||
opClass=FloatCmp
|
||||
opLat=2
|
||||
issueLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList2.opList2]
|
||||
type=OpDesc
|
||||
opClass=FloatCvt
|
||||
opLat=2
|
||||
issueLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList2]
|
||||
type=FUDesc
|
||||
opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
|
||||
count=4
|
||||
|
||||
[system.cpu.fuPool.FUList3.opList0]
|
||||
type=OpDesc
|
||||
opClass=FloatMult
|
||||
opLat=4
|
||||
issueLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList3.opList1]
|
||||
type=OpDesc
|
||||
opClass=FloatDiv
|
||||
opLat=12
|
||||
issueLat=12
|
||||
|
||||
[system.cpu.fuPool.FUList3.opList2]
|
||||
type=OpDesc
|
||||
opClass=FloatSqrt
|
||||
opLat=24
|
||||
issueLat=24
|
||||
|
||||
[system.cpu.fuPool.FUList3]
|
||||
type=FUDesc
|
||||
opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
|
||||
count=2
|
||||
|
||||
[system.cpu.fuPool.FUList4.opList0]
|
||||
type=OpDesc
|
||||
opClass=MemRead
|
||||
opLat=1
|
||||
issueLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList4]
|
||||
type=FUDesc
|
||||
opList=system.cpu.fuPool.FUList4.opList0
|
||||
count=0
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList0]
|
||||
type=OpDesc
|
||||
opClass=MemWrite
|
||||
opLat=1
|
||||
issueLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5]
|
||||
type=FUDesc
|
||||
opList=system.cpu.fuPool.FUList5.opList0
|
||||
count=0
|
||||
|
||||
[system.cpu.fuPool.FUList6.opList0]
|
||||
type=OpDesc
|
||||
opClass=MemRead
|
||||
opLat=1
|
||||
issueLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList6.opList1]
|
||||
type=OpDesc
|
||||
opClass=MemWrite
|
||||
opLat=1
|
||||
issueLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList6]
|
||||
type=FUDesc
|
||||
opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1
|
||||
count=4
|
||||
|
||||
[system.cpu.fuPool.FUList7.opList0]
|
||||
type=OpDesc
|
||||
opClass=IprAccess
|
||||
opLat=3
|
||||
issueLat=3
|
||||
|
||||
[system.cpu.fuPool.FUList7]
|
||||
type=FUDesc
|
||||
opList=system.cpu.fuPool.FUList7.opList0
|
||||
count=1
|
||||
|
||||
[system.cpu.fuPool]
|
||||
type=FUPool
|
||||
FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7
|
||||
|
||||
[system.cpu]
|
||||
type=DerivO3CPU
|
||||
clock=1
|
||||
numThreads=1
|
||||
activity=0
|
||||
workload=system.cpu.workload
|
||||
mem=system.cpu.dcache
|
||||
checker=null
|
||||
max_insts_any_thread=0
|
||||
max_insts_all_threads=0
|
||||
max_loads_any_thread=0
|
||||
max_loads_all_threads=0
|
||||
cachePorts=200
|
||||
decodeToFetchDelay=1
|
||||
renameToFetchDelay=1
|
||||
iewToFetchDelay=1
|
||||
commitToFetchDelay=1
|
||||
fetchWidth=8
|
||||
renameToDecodeDelay=1
|
||||
iewToDecodeDelay=1
|
||||
commitToDecodeDelay=1
|
||||
fetchToDecodeDelay=1
|
||||
decodeWidth=8
|
||||
iewToRenameDelay=1
|
||||
commitToRenameDelay=1
|
||||
decodeToRenameDelay=1
|
||||
renameWidth=8
|
||||
commitToIEWDelay=1
|
||||
renameToIEWDelay=2
|
||||
issueToExecuteDelay=1
|
||||
dispatchWidth=8
|
||||
issueWidth=8
|
||||
wbWidth=8
|
||||
wbDepth=1
|
||||
fuPool=system.cpu.fuPool
|
||||
iewToCommitDelay=1
|
||||
renameToROBDelay=1
|
||||
commitWidth=8
|
||||
squashWidth=8
|
||||
trapLatency=13
|
||||
backComSize=5
|
||||
forwardComSize=5
|
||||
predType=tournament
|
||||
localPredictorSize=2048
|
||||
localCtrBits=2
|
||||
localHistoryTableSize=2048
|
||||
localHistoryBits=11
|
||||
globalPredictorSize=8192
|
||||
globalCtrBits=2
|
||||
globalHistoryBits=13
|
||||
choicePredictorSize=8192
|
||||
choiceCtrBits=2
|
||||
BTBEntries=4096
|
||||
BTBTagSize=16
|
||||
RASSize=16
|
||||
LQEntries=32
|
||||
SQEntries=32
|
||||
LFSTSize=1024
|
||||
SSITSize=1024
|
||||
numPhysIntRegs=256
|
||||
numPhysFloatRegs=256
|
||||
numIQEntries=64
|
||||
numROBEntries=192
|
||||
smtNumFetchingThreads=1
|
||||
smtFetchPolicy=SingleThread
|
||||
smtLSQPolicy=Partitioned
|
||||
smtLSQThreshold=100
|
||||
smtIQPolicy=Partitioned
|
||||
smtIQThreshold=100
|
||||
smtROBPolicy=Partitioned
|
||||
smtROBThreshold=100
|
||||
smtCommitPolicy=RoundRobin
|
||||
instShiftAmt=2
|
||||
defer_registration=false
|
||||
function_trace=false
|
||||
function_trace_start=0
|
||||
|
||||
[system.cpu.icache]
|
||||
[system.cpu.dcache]
|
||||
type=BaseCache
|
||||
size=131072
|
||||
size=262144
|
||||
assoc=2
|
||||
block_size=64
|
||||
latency=1
|
||||
|
|
@ -283,7 +112,6 @@ mshrs=10
|
|||
tgts_per_mshr=5
|
||||
write_buffers=8
|
||||
prioritizeRequests=false
|
||||
do_copy=false
|
||||
protocol=null
|
||||
trace_addr=0
|
||||
hash_delay=1
|
||||
|
|
@ -322,7 +150,6 @@ mshrs=10
|
|||
tgts_per_mshr=5
|
||||
write_buffers=8
|
||||
prioritizeRequests=false
|
||||
do_copy=false
|
||||
protocol=null
|
||||
trace_addr=0
|
||||
hash_delay=1
|
||||
|
|
@ -351,13 +178,10 @@ prefetch_use_cpu_id=true
|
|||
prefetch_data_accesses_only=false
|
||||
hit_latency=1
|
||||
|
||||
[system.cpu.toL2Bus]
|
||||
type=Bus
|
||||
bus_id=0
|
||||
|
||||
[trace]
|
||||
flags=
|
||||
start=0
|
||||
cycle=0
|
||||
bufsize=0
|
||||
file=cout
|
||||
dump_on_exit=false
|
||||
|
|
@ -396,8 +220,9 @@ print_cpseq=false
|
|||
print_reg_delta=false
|
||||
pc_symbol=true
|
||||
intel_format=false
|
||||
legion_lockstep=false
|
||||
trace_system=client
|
||||
|
||||
[debug]
|
||||
break_cycles=
|
||||
[statsreset]
|
||||
reset_cycle=0
|
||||
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -1,3 +1,47 @@
|
|||
warn: Entering event queue @ 0. Starting simulation...
|
||||
warn: cycle 0: fault (page_table_fault) detected @ PC 0x000000
|
||||
warn: Increasing stack 0x11ff92000:0x11ff9b000 to 0x11ff90000:0x11ff9b000 because of access to 0x11ff91ff0
|
||||
getting pixel output filename pixels_out.cook
|
||||
opening control file chair.control.cook
|
||||
opening camera file chair.camera
|
||||
opening surfaces file chair.surfaces
|
||||
reading data
|
||||
processing 8parts
|
||||
Grid measure is 6 by 3.0001 by 6
|
||||
cell dimension is 0.863065
|
||||
Creating grid for list of length 21
|
||||
Grid size = 7 by 4 by 7
|
||||
Total occupancy = 236
|
||||
reading control stream
|
||||
reading camera stream
|
||||
Writing to chair.cook.ppm
|
||||
calculating 15 by 15 image with 196 samples
|
||||
col 0. . .
|
||||
col 1. . .
|
||||
col 2. . .
|
||||
col 3. . .
|
||||
col 4. . .
|
||||
col 5. . .
|
||||
col 6. . .
|
||||
col 7. . .
|
||||
col 8. . .
|
||||
col 9. . .
|
||||
col 10. . .
|
||||
col 11. . .
|
||||
col 12. . .
|
||||
col 13. . .
|
||||
col 14. . .
|
||||
Writing to chair.cook.ppm
|
||||
0 8 14
|
||||
1 8 14
|
||||
2 8 14
|
||||
3 8 14
|
||||
4 8 14
|
||||
5 8 14
|
||||
6 8 14
|
||||
7 8 14
|
||||
8 8 14
|
||||
9 8 14
|
||||
10 8 14
|
||||
11 8 14
|
||||
12 8 14
|
||||
13 8 14
|
||||
14 8 14
|
||||
|
|
|
|||
|
|
@ -1,13 +1,2 @@
|
|||
Hello world!
|
||||
M5 Simulator System
|
||||
|
||||
Copyright (c) 2001-2006
|
||||
The Regents of The University of Michigan
|
||||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Sep 5 2006 15:28:48
|
||||
M5 started Tue Sep 5 15:42:12 2006
|
||||
M5 executing on zizzer.eecs.umich.edu
|
||||
command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/o3-timing tests/run.py quick/00.hello/alpha/linux/o3-timing
|
||||
Exiting @ tick 6870 because target called exit()
|
||||
Eon, Version 1.1
|
||||
OO-style eon Time= 0.000000
|
||||
|
|
|
|||
|
|
@ -7,11 +7,9 @@ max_tick=0
|
|||
output_file=cout
|
||||
progress_interval=0
|
||||
|
||||
[debug]
|
||||
break_cycles=
|
||||
|
||||
[exetrace]
|
||||
intel_format=false
|
||||
legion_lockstep=false
|
||||
pc_symbol=true
|
||||
print_cpseq=false
|
||||
print_cycle=true
|
||||
|
|
@ -53,352 +51,49 @@ mem_mode=atomic
|
|||
physmem=system.physmem
|
||||
|
||||
[system.cpu]
|
||||
type=DerivO3CPU
|
||||
children=dcache fuPool icache l2cache toL2Bus workload
|
||||
BTBEntries=4096
|
||||
BTBTagSize=16
|
||||
LFSTSize=1024
|
||||
LQEntries=32
|
||||
RASSize=16
|
||||
SQEntries=32
|
||||
SSITSize=1024
|
||||
activity=0
|
||||
backComSize=5
|
||||
choiceCtrBits=2
|
||||
choicePredictorSize=8192
|
||||
type=AtomicSimpleCPU
|
||||
children=workload
|
||||
clock=1
|
||||
commitToDecodeDelay=1
|
||||
commitToFetchDelay=1
|
||||
commitToIEWDelay=1
|
||||
commitToRenameDelay=1
|
||||
commitWidth=8
|
||||
decodeToFetchDelay=1
|
||||
decodeToRenameDelay=1
|
||||
decodeWidth=8
|
||||
cpu_id=0
|
||||
defer_registration=false
|
||||
dispatchWidth=8
|
||||
fetchToDecodeDelay=1
|
||||
fetchTrapLatency=1
|
||||
fetchWidth=8
|
||||
forwardComSize=5
|
||||
fuPool=system.cpu.fuPool
|
||||
function_trace=false
|
||||
function_trace_start=0
|
||||
globalCtrBits=2
|
||||
globalHistoryBits=13
|
||||
globalPredictorSize=8192
|
||||
iewToCommitDelay=1
|
||||
iewToDecodeDelay=1
|
||||
iewToFetchDelay=1
|
||||
iewToRenameDelay=1
|
||||
instShiftAmt=2
|
||||
issueToExecuteDelay=1
|
||||
issueWidth=8
|
||||
localCtrBits=2
|
||||
localHistoryBits=11
|
||||
localHistoryTableSize=2048
|
||||
localPredictorSize=2048
|
||||
max_insts_all_threads=0
|
||||
max_insts_any_thread=0
|
||||
max_loads_all_threads=0
|
||||
max_loads_any_thread=0
|
||||
mem=system.cpu.dcache
|
||||
numIQEntries=64
|
||||
numPhysFloatRegs=256
|
||||
numPhysIntRegs=256
|
||||
numROBEntries=192
|
||||
numRobs=1
|
||||
numThreads=1
|
||||
predType=tournament
|
||||
renameToDecodeDelay=1
|
||||
renameToFetchDelay=1
|
||||
renameToIEWDelay=2
|
||||
renameToROBDelay=1
|
||||
renameWidth=8
|
||||
squashWidth=8
|
||||
phase=0
|
||||
progress_interval=0
|
||||
simulate_stalls=false
|
||||
system=system
|
||||
trapLatency=13
|
||||
wbDepth=1
|
||||
wbWidth=8
|
||||
width=1
|
||||
workload=system.cpu.workload
|
||||
dcache_port=system.cpu.dcache.cpu_side
|
||||
icache_port=system.cpu.icache.cpu_side
|
||||
|
||||
[system.cpu.dcache]
|
||||
type=BaseCache
|
||||
adaptive_compression=false
|
||||
assoc=2
|
||||
block_size=64
|
||||
compressed_bus=false
|
||||
compression_latency=0
|
||||
do_copy=false
|
||||
hash_delay=1
|
||||
hit_latency=1
|
||||
latency=1
|
||||
lifo=false
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
prefetch_access=false
|
||||
prefetch_cache_check_push=true
|
||||
prefetch_data_accesses_only=false
|
||||
prefetch_degree=1
|
||||
prefetch_latency=10
|
||||
prefetch_miss=false
|
||||
prefetch_past_page=false
|
||||
prefetch_policy=none
|
||||
prefetch_serial_squash=false
|
||||
prefetch_use_cpu_id=true
|
||||
prefetcher_size=100
|
||||
prioritizeRequests=false
|
||||
protocol=Null
|
||||
repl=Null
|
||||
size=262144
|
||||
split=false
|
||||
split_size=0
|
||||
store_compressed=false
|
||||
subblock_size=0
|
||||
tgts_per_mshr=5
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu.dcache_port
|
||||
mem_side=system.cpu.toL2Bus.port[1]
|
||||
|
||||
[system.cpu.fuPool]
|
||||
type=FUPool
|
||||
children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7
|
||||
FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7
|
||||
|
||||
[system.cpu.fuPool.FUList0]
|
||||
type=FUDesc
|
||||
children=opList0
|
||||
count=6
|
||||
opList=system.cpu.fuPool.FUList0.opList0
|
||||
|
||||
[system.cpu.fuPool.FUList0.opList0]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=IntAlu
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList1]
|
||||
type=FUDesc
|
||||
children=opList0 opList1
|
||||
count=2
|
||||
opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
|
||||
|
||||
[system.cpu.fuPool.FUList1.opList0]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=IntMult
|
||||
opLat=3
|
||||
|
||||
[system.cpu.fuPool.FUList1.opList1]
|
||||
type=OpDesc
|
||||
issueLat=19
|
||||
opClass=IntDiv
|
||||
opLat=20
|
||||
|
||||
[system.cpu.fuPool.FUList2]
|
||||
type=FUDesc
|
||||
children=opList0 opList1 opList2
|
||||
count=4
|
||||
opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
|
||||
|
||||
[system.cpu.fuPool.FUList2.opList0]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=FloatAdd
|
||||
opLat=2
|
||||
|
||||
[system.cpu.fuPool.FUList2.opList1]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=FloatCmp
|
||||
opLat=2
|
||||
|
||||
[system.cpu.fuPool.FUList2.opList2]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=FloatCvt
|
||||
opLat=2
|
||||
|
||||
[system.cpu.fuPool.FUList3]
|
||||
type=FUDesc
|
||||
children=opList0 opList1 opList2
|
||||
count=2
|
||||
opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
|
||||
|
||||
[system.cpu.fuPool.FUList3.opList0]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=FloatMult
|
||||
opLat=4
|
||||
|
||||
[system.cpu.fuPool.FUList3.opList1]
|
||||
type=OpDesc
|
||||
issueLat=12
|
||||
opClass=FloatDiv
|
||||
opLat=12
|
||||
|
||||
[system.cpu.fuPool.FUList3.opList2]
|
||||
type=OpDesc
|
||||
issueLat=24
|
||||
opClass=FloatSqrt
|
||||
opLat=24
|
||||
|
||||
[system.cpu.fuPool.FUList4]
|
||||
type=FUDesc
|
||||
children=opList0
|
||||
count=0
|
||||
opList=system.cpu.fuPool.FUList4.opList0
|
||||
|
||||
[system.cpu.fuPool.FUList4.opList0]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=MemRead
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5]
|
||||
type=FUDesc
|
||||
children=opList0
|
||||
count=0
|
||||
opList=system.cpu.fuPool.FUList5.opList0
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList0]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=MemWrite
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList6]
|
||||
type=FUDesc
|
||||
children=opList0 opList1
|
||||
count=4
|
||||
opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1
|
||||
|
||||
[system.cpu.fuPool.FUList6.opList0]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=MemRead
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList6.opList1]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=MemWrite
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList7]
|
||||
type=FUDesc
|
||||
children=opList0
|
||||
count=1
|
||||
opList=system.cpu.fuPool.FUList7.opList0
|
||||
|
||||
[system.cpu.fuPool.FUList7.opList0]
|
||||
type=OpDesc
|
||||
issueLat=3
|
||||
opClass=IprAccess
|
||||
opLat=3
|
||||
|
||||
[system.cpu.icache]
|
||||
type=BaseCache
|
||||
adaptive_compression=false
|
||||
assoc=2
|
||||
block_size=64
|
||||
compressed_bus=false
|
||||
compression_latency=0
|
||||
do_copy=false
|
||||
hash_delay=1
|
||||
hit_latency=1
|
||||
latency=1
|
||||
lifo=false
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
prefetch_access=false
|
||||
prefetch_cache_check_push=true
|
||||
prefetch_data_accesses_only=false
|
||||
prefetch_degree=1
|
||||
prefetch_latency=10
|
||||
prefetch_miss=false
|
||||
prefetch_past_page=false
|
||||
prefetch_policy=none
|
||||
prefetch_serial_squash=false
|
||||
prefetch_use_cpu_id=true
|
||||
prefetcher_size=100
|
||||
prioritizeRequests=false
|
||||
protocol=Null
|
||||
repl=Null
|
||||
size=131072
|
||||
split=false
|
||||
split_size=0
|
||||
store_compressed=false
|
||||
subblock_size=0
|
||||
tgts_per_mshr=5
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu.icache_port
|
||||
mem_side=system.cpu.toL2Bus.port[0]
|
||||
|
||||
[system.cpu.l2cache]
|
||||
type=BaseCache
|
||||
adaptive_compression=false
|
||||
assoc=2
|
||||
block_size=64
|
||||
compressed_bus=false
|
||||
compression_latency=0
|
||||
do_copy=false
|
||||
hash_delay=1
|
||||
hit_latency=1
|
||||
latency=1
|
||||
lifo=false
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
prefetch_access=false
|
||||
prefetch_cache_check_push=true
|
||||
prefetch_data_accesses_only=false
|
||||
prefetch_degree=1
|
||||
prefetch_latency=10
|
||||
prefetch_miss=false
|
||||
prefetch_past_page=false
|
||||
prefetch_policy=none
|
||||
prefetch_serial_squash=false
|
||||
prefetch_use_cpu_id=true
|
||||
prefetcher_size=100
|
||||
prioritizeRequests=false
|
||||
protocol=Null
|
||||
repl=Null
|
||||
size=2097152
|
||||
split=false
|
||||
split_size=0
|
||||
store_compressed=false
|
||||
subblock_size=0
|
||||
tgts_per_mshr=5
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu.toL2Bus.port[2]
|
||||
mem_side=system.membus.port[1]
|
||||
|
||||
[system.cpu.toL2Bus]
|
||||
type=Bus
|
||||
bus_id=0
|
||||
port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
|
||||
dcache_port=system.membus.port[2]
|
||||
icache_port=system.membus.port[1]
|
||||
|
||||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
cmd=hello
|
||||
cmd=perlbmk -I. -I lib lgred.makerand.pl
|
||||
cwd=build/ALPHA_SE/tests/opt/long/40.perlbmk/alpha/linux/simple-atomic
|
||||
egid=100
|
||||
env=
|
||||
executable=tests/test-progs/hello/bin/alpha/linux/hello
|
||||
euid=100
|
||||
executable=/dist/m5/cpu2000/binaries/alpha/tru64/perlbmk
|
||||
gid=100
|
||||
input=cin
|
||||
output=cout
|
||||
pid=100
|
||||
ppid=99
|
||||
system=system
|
||||
uid=100
|
||||
|
||||
[system.membus]
|
||||
type=Bus
|
||||
bus_id=0
|
||||
port=system.physmem.port system.cpu.l2cache.mem_side
|
||||
clock=1000
|
||||
responder_set=false
|
||||
width=64
|
||||
port=system.physmem.port system.cpu.icache_port system.cpu.dcache_port
|
||||
|
||||
[system.physmem]
|
||||
type=PhysicalMemory
|
||||
|
|
@ -409,6 +104,7 @@ port=system.membus.port[0]
|
|||
|
||||
[trace]
|
||||
bufsize=0
|
||||
cycle=0
|
||||
dump_on_exit=false
|
||||
file=cout
|
||||
flags=
|
||||
|
|
|
|||
|
|
@ -19,345 +19,48 @@ mem_mode=atomic
|
|||
[system.membus]
|
||||
type=Bus
|
||||
bus_id=0
|
||||
clock=1000
|
||||
width=64
|
||||
responder_set=false
|
||||
|
||||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
cmd=hello
|
||||
executable=tests/test-progs/hello/bin/alpha/linux/hello
|
||||
cmd=perlbmk -I. -I lib lgred.makerand.pl
|
||||
executable=/dist/m5/cpu2000/binaries/alpha/tru64/perlbmk
|
||||
input=cin
|
||||
output=cout
|
||||
env=
|
||||
cwd=build/ALPHA_SE/tests/opt/long/40.perlbmk/alpha/linux/simple-atomic
|
||||
system=system
|
||||
|
||||
[system.cpu.dcache]
|
||||
type=BaseCache
|
||||
size=262144
|
||||
assoc=2
|
||||
block_size=64
|
||||
latency=1
|
||||
mshrs=10
|
||||
tgts_per_mshr=5
|
||||
write_buffers=8
|
||||
prioritizeRequests=false
|
||||
do_copy=false
|
||||
protocol=null
|
||||
trace_addr=0
|
||||
hash_delay=1
|
||||
repl=null
|
||||
compressed_bus=false
|
||||
store_compressed=false
|
||||
adaptive_compression=false
|
||||
compression_latency=0
|
||||
block_size=64
|
||||
max_miss_count=0
|
||||
addr_range=[0,18446744073709551615]
|
||||
split=false
|
||||
split_size=0
|
||||
lifo=false
|
||||
two_queue=false
|
||||
prefetch_miss=false
|
||||
prefetch_access=false
|
||||
prefetcher_size=100
|
||||
prefetch_past_page=false
|
||||
prefetch_serial_squash=false
|
||||
prefetch_latency=10
|
||||
prefetch_degree=1
|
||||
prefetch_policy=none
|
||||
prefetch_cache_check_push=true
|
||||
prefetch_use_cpu_id=true
|
||||
prefetch_data_accesses_only=false
|
||||
hit_latency=1
|
||||
|
||||
[system.cpu.fuPool.FUList0.opList0]
|
||||
type=OpDesc
|
||||
opClass=IntAlu
|
||||
opLat=1
|
||||
issueLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList0]
|
||||
type=FUDesc
|
||||
opList=system.cpu.fuPool.FUList0.opList0
|
||||
count=6
|
||||
|
||||
[system.cpu.fuPool.FUList1.opList0]
|
||||
type=OpDesc
|
||||
opClass=IntMult
|
||||
opLat=3
|
||||
issueLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList1.opList1]
|
||||
type=OpDesc
|
||||
opClass=IntDiv
|
||||
opLat=20
|
||||
issueLat=19
|
||||
|
||||
[system.cpu.fuPool.FUList1]
|
||||
type=FUDesc
|
||||
opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
|
||||
count=2
|
||||
|
||||
[system.cpu.fuPool.FUList2.opList0]
|
||||
type=OpDesc
|
||||
opClass=FloatAdd
|
||||
opLat=2
|
||||
issueLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList2.opList1]
|
||||
type=OpDesc
|
||||
opClass=FloatCmp
|
||||
opLat=2
|
||||
issueLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList2.opList2]
|
||||
type=OpDesc
|
||||
opClass=FloatCvt
|
||||
opLat=2
|
||||
issueLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList2]
|
||||
type=FUDesc
|
||||
opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
|
||||
count=4
|
||||
|
||||
[system.cpu.fuPool.FUList3.opList0]
|
||||
type=OpDesc
|
||||
opClass=FloatMult
|
||||
opLat=4
|
||||
issueLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList3.opList1]
|
||||
type=OpDesc
|
||||
opClass=FloatDiv
|
||||
opLat=12
|
||||
issueLat=12
|
||||
|
||||
[system.cpu.fuPool.FUList3.opList2]
|
||||
type=OpDesc
|
||||
opClass=FloatSqrt
|
||||
opLat=24
|
||||
issueLat=24
|
||||
|
||||
[system.cpu.fuPool.FUList3]
|
||||
type=FUDesc
|
||||
opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
|
||||
count=2
|
||||
|
||||
[system.cpu.fuPool.FUList4.opList0]
|
||||
type=OpDesc
|
||||
opClass=MemRead
|
||||
opLat=1
|
||||
issueLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList4]
|
||||
type=FUDesc
|
||||
opList=system.cpu.fuPool.FUList4.opList0
|
||||
count=0
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList0]
|
||||
type=OpDesc
|
||||
opClass=MemWrite
|
||||
opLat=1
|
||||
issueLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5]
|
||||
type=FUDesc
|
||||
opList=system.cpu.fuPool.FUList5.opList0
|
||||
count=0
|
||||
|
||||
[system.cpu.fuPool.FUList6.opList0]
|
||||
type=OpDesc
|
||||
opClass=MemRead
|
||||
opLat=1
|
||||
issueLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList6.opList1]
|
||||
type=OpDesc
|
||||
opClass=MemWrite
|
||||
opLat=1
|
||||
issueLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList6]
|
||||
type=FUDesc
|
||||
opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1
|
||||
count=4
|
||||
|
||||
[system.cpu.fuPool.FUList7.opList0]
|
||||
type=OpDesc
|
||||
opClass=IprAccess
|
||||
opLat=3
|
||||
issueLat=3
|
||||
|
||||
[system.cpu.fuPool.FUList7]
|
||||
type=FUDesc
|
||||
opList=system.cpu.fuPool.FUList7.opList0
|
||||
count=1
|
||||
|
||||
[system.cpu.fuPool]
|
||||
type=FUPool
|
||||
FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7
|
||||
uid=100
|
||||
euid=100
|
||||
gid=100
|
||||
egid=100
|
||||
pid=100
|
||||
ppid=99
|
||||
|
||||
[system.cpu]
|
||||
type=DerivO3CPU
|
||||
clock=1
|
||||
numThreads=1
|
||||
activity=0
|
||||
workload=system.cpu.workload
|
||||
mem=system.cpu.dcache
|
||||
checker=null
|
||||
type=AtomicSimpleCPU
|
||||
max_insts_any_thread=0
|
||||
max_insts_all_threads=0
|
||||
max_loads_any_thread=0
|
||||
max_loads_all_threads=0
|
||||
cachePorts=200
|
||||
decodeToFetchDelay=1
|
||||
renameToFetchDelay=1
|
||||
iewToFetchDelay=1
|
||||
commitToFetchDelay=1
|
||||
fetchWidth=8
|
||||
renameToDecodeDelay=1
|
||||
iewToDecodeDelay=1
|
||||
commitToDecodeDelay=1
|
||||
fetchToDecodeDelay=1
|
||||
decodeWidth=8
|
||||
iewToRenameDelay=1
|
||||
commitToRenameDelay=1
|
||||
decodeToRenameDelay=1
|
||||
renameWidth=8
|
||||
commitToIEWDelay=1
|
||||
renameToIEWDelay=2
|
||||
issueToExecuteDelay=1
|
||||
dispatchWidth=8
|
||||
issueWidth=8
|
||||
wbWidth=8
|
||||
wbDepth=1
|
||||
fuPool=system.cpu.fuPool
|
||||
iewToCommitDelay=1
|
||||
renameToROBDelay=1
|
||||
commitWidth=8
|
||||
squashWidth=8
|
||||
trapLatency=13
|
||||
backComSize=5
|
||||
forwardComSize=5
|
||||
predType=tournament
|
||||
localPredictorSize=2048
|
||||
localCtrBits=2
|
||||
localHistoryTableSize=2048
|
||||
localHistoryBits=11
|
||||
globalPredictorSize=8192
|
||||
globalCtrBits=2
|
||||
globalHistoryBits=13
|
||||
choicePredictorSize=8192
|
||||
choiceCtrBits=2
|
||||
BTBEntries=4096
|
||||
BTBTagSize=16
|
||||
RASSize=16
|
||||
LQEntries=32
|
||||
SQEntries=32
|
||||
LFSTSize=1024
|
||||
SSITSize=1024
|
||||
numPhysIntRegs=256
|
||||
numPhysFloatRegs=256
|
||||
numIQEntries=64
|
||||
numROBEntries=192
|
||||
smtNumFetchingThreads=1
|
||||
smtFetchPolicy=SingleThread
|
||||
smtLSQPolicy=Partitioned
|
||||
smtLSQThreshold=100
|
||||
smtIQPolicy=Partitioned
|
||||
smtIQThreshold=100
|
||||
smtROBPolicy=Partitioned
|
||||
smtROBThreshold=100
|
||||
smtCommitPolicy=RoundRobin
|
||||
instShiftAmt=2
|
||||
progress_interval=0
|
||||
system=system
|
||||
cpu_id=0
|
||||
workload=system.cpu.workload
|
||||
clock=1
|
||||
phase=0
|
||||
defer_registration=false
|
||||
width=1
|
||||
function_trace=false
|
||||
function_trace_start=0
|
||||
|
||||
[system.cpu.icache]
|
||||
type=BaseCache
|
||||
size=131072
|
||||
assoc=2
|
||||
block_size=64
|
||||
latency=1
|
||||
mshrs=10
|
||||
tgts_per_mshr=5
|
||||
write_buffers=8
|
||||
prioritizeRequests=false
|
||||
do_copy=false
|
||||
protocol=null
|
||||
trace_addr=0
|
||||
hash_delay=1
|
||||
repl=null
|
||||
compressed_bus=false
|
||||
store_compressed=false
|
||||
adaptive_compression=false
|
||||
compression_latency=0
|
||||
block_size=64
|
||||
max_miss_count=0
|
||||
addr_range=[0,18446744073709551615]
|
||||
split=false
|
||||
split_size=0
|
||||
lifo=false
|
||||
two_queue=false
|
||||
prefetch_miss=false
|
||||
prefetch_access=false
|
||||
prefetcher_size=100
|
||||
prefetch_past_page=false
|
||||
prefetch_serial_squash=false
|
||||
prefetch_latency=10
|
||||
prefetch_degree=1
|
||||
prefetch_policy=none
|
||||
prefetch_cache_check_push=true
|
||||
prefetch_use_cpu_id=true
|
||||
prefetch_data_accesses_only=false
|
||||
hit_latency=1
|
||||
|
||||
[system.cpu.l2cache]
|
||||
type=BaseCache
|
||||
size=2097152
|
||||
assoc=2
|
||||
block_size=64
|
||||
latency=1
|
||||
mshrs=10
|
||||
tgts_per_mshr=5
|
||||
write_buffers=8
|
||||
prioritizeRequests=false
|
||||
do_copy=false
|
||||
protocol=null
|
||||
trace_addr=0
|
||||
hash_delay=1
|
||||
repl=null
|
||||
compressed_bus=false
|
||||
store_compressed=false
|
||||
adaptive_compression=false
|
||||
compression_latency=0
|
||||
block_size=64
|
||||
max_miss_count=0
|
||||
addr_range=[0,18446744073709551615]
|
||||
split=false
|
||||
split_size=0
|
||||
lifo=false
|
||||
two_queue=false
|
||||
prefetch_miss=false
|
||||
prefetch_access=false
|
||||
prefetcher_size=100
|
||||
prefetch_past_page=false
|
||||
prefetch_serial_squash=false
|
||||
prefetch_latency=10
|
||||
prefetch_degree=1
|
||||
prefetch_policy=none
|
||||
prefetch_cache_check_push=true
|
||||
prefetch_use_cpu_id=true
|
||||
prefetch_data_accesses_only=false
|
||||
hit_latency=1
|
||||
|
||||
[system.cpu.toL2Bus]
|
||||
type=Bus
|
||||
bus_id=0
|
||||
simulate_stalls=false
|
||||
|
||||
[trace]
|
||||
flags=
|
||||
start=0
|
||||
cycle=0
|
||||
bufsize=0
|
||||
file=cout
|
||||
dump_on_exit=false
|
||||
|
|
@ -396,8 +99,9 @@ print_cpseq=false
|
|||
print_reg_delta=false
|
||||
pc_symbol=true
|
||||
intel_format=false
|
||||
legion_lockstep=false
|
||||
trace_system=client
|
||||
|
||||
[debug]
|
||||
break_cycles=
|
||||
[statsreset]
|
||||
reset_cycle=0
|
||||
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -1,3 +1,2 @@
|
|||
warn: Entering event queue @ 0. Starting simulation...
|
||||
warn: cycle 0: fault (page_table_fault) detected @ PC 0x000000
|
||||
warn: Increasing stack 0x11ff92000:0x11ff9b000 to 0x11ff90000:0x11ff9b000 because of access to 0x11ff91ff0
|
||||
warn: ignoring syscall sigprocmask(1, 0, ...)
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -7,11 +7,9 @@ max_tick=0
|
|||
output_file=cout
|
||||
progress_interval=0
|
||||
|
||||
[debug]
|
||||
break_cycles=
|
||||
|
||||
[exetrace]
|
||||
intel_format=false
|
||||
legion_lockstep=false
|
||||
pc_symbol=true
|
||||
print_cpseq=false
|
||||
print_cycle=true
|
||||
|
|
@ -53,73 +51,20 @@ mem_mode=atomic
|
|||
physmem=system.physmem
|
||||
|
||||
[system.cpu]
|
||||
type=DerivO3CPU
|
||||
children=dcache fuPool icache l2cache toL2Bus workload
|
||||
BTBEntries=4096
|
||||
BTBTagSize=16
|
||||
LFSTSize=1024
|
||||
LQEntries=32
|
||||
RASSize=16
|
||||
SQEntries=32
|
||||
SSITSize=1024
|
||||
activity=0
|
||||
backComSize=5
|
||||
choiceCtrBits=2
|
||||
choicePredictorSize=8192
|
||||
type=TimingSimpleCPU
|
||||
children=dcache icache l2cache toL2Bus workload
|
||||
clock=1
|
||||
commitToDecodeDelay=1
|
||||
commitToFetchDelay=1
|
||||
commitToIEWDelay=1
|
||||
commitToRenameDelay=1
|
||||
commitWidth=8
|
||||
decodeToFetchDelay=1
|
||||
decodeToRenameDelay=1
|
||||
decodeWidth=8
|
||||
cpu_id=0
|
||||
defer_registration=false
|
||||
dispatchWidth=8
|
||||
fetchToDecodeDelay=1
|
||||
fetchTrapLatency=1
|
||||
fetchWidth=8
|
||||
forwardComSize=5
|
||||
fuPool=system.cpu.fuPool
|
||||
function_trace=false
|
||||
function_trace_start=0
|
||||
globalCtrBits=2
|
||||
globalHistoryBits=13
|
||||
globalPredictorSize=8192
|
||||
iewToCommitDelay=1
|
||||
iewToDecodeDelay=1
|
||||
iewToFetchDelay=1
|
||||
iewToRenameDelay=1
|
||||
instShiftAmt=2
|
||||
issueToExecuteDelay=1
|
||||
issueWidth=8
|
||||
localCtrBits=2
|
||||
localHistoryBits=11
|
||||
localHistoryTableSize=2048
|
||||
localPredictorSize=2048
|
||||
max_insts_all_threads=0
|
||||
max_insts_any_thread=0
|
||||
max_loads_all_threads=0
|
||||
max_loads_any_thread=0
|
||||
mem=system.cpu.dcache
|
||||
numIQEntries=64
|
||||
numPhysFloatRegs=256
|
||||
numPhysIntRegs=256
|
||||
numROBEntries=192
|
||||
numRobs=1
|
||||
numThreads=1
|
||||
predType=tournament
|
||||
renameToDecodeDelay=1
|
||||
renameToFetchDelay=1
|
||||
renameToIEWDelay=2
|
||||
renameToROBDelay=1
|
||||
renameWidth=8
|
||||
squashWidth=8
|
||||
phase=0
|
||||
progress_interval=0
|
||||
system=system
|
||||
trapLatency=13
|
||||
wbDepth=1
|
||||
wbWidth=8
|
||||
workload=system.cpu.workload
|
||||
dcache_port=system.cpu.dcache.cpu_side
|
||||
icache_port=system.cpu.icache.cpu_side
|
||||
|
|
@ -131,7 +76,6 @@ assoc=2
|
|||
block_size=64
|
||||
compressed_bus=false
|
||||
compression_latency=0
|
||||
do_copy=false
|
||||
hash_delay=1
|
||||
hit_latency=1
|
||||
latency=1
|
||||
|
|
@ -164,143 +108,6 @@ write_buffers=8
|
|||
cpu_side=system.cpu.dcache_port
|
||||
mem_side=system.cpu.toL2Bus.port[1]
|
||||
|
||||
[system.cpu.fuPool]
|
||||
type=FUPool
|
||||
children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7
|
||||
FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7
|
||||
|
||||
[system.cpu.fuPool.FUList0]
|
||||
type=FUDesc
|
||||
children=opList0
|
||||
count=6
|
||||
opList=system.cpu.fuPool.FUList0.opList0
|
||||
|
||||
[system.cpu.fuPool.FUList0.opList0]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=IntAlu
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList1]
|
||||
type=FUDesc
|
||||
children=opList0 opList1
|
||||
count=2
|
||||
opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
|
||||
|
||||
[system.cpu.fuPool.FUList1.opList0]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=IntMult
|
||||
opLat=3
|
||||
|
||||
[system.cpu.fuPool.FUList1.opList1]
|
||||
type=OpDesc
|
||||
issueLat=19
|
||||
opClass=IntDiv
|
||||
opLat=20
|
||||
|
||||
[system.cpu.fuPool.FUList2]
|
||||
type=FUDesc
|
||||
children=opList0 opList1 opList2
|
||||
count=4
|
||||
opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
|
||||
|
||||
[system.cpu.fuPool.FUList2.opList0]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=FloatAdd
|
||||
opLat=2
|
||||
|
||||
[system.cpu.fuPool.FUList2.opList1]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=FloatCmp
|
||||
opLat=2
|
||||
|
||||
[system.cpu.fuPool.FUList2.opList2]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=FloatCvt
|
||||
opLat=2
|
||||
|
||||
[system.cpu.fuPool.FUList3]
|
||||
type=FUDesc
|
||||
children=opList0 opList1 opList2
|
||||
count=2
|
||||
opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
|
||||
|
||||
[system.cpu.fuPool.FUList3.opList0]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=FloatMult
|
||||
opLat=4
|
||||
|
||||
[system.cpu.fuPool.FUList3.opList1]
|
||||
type=OpDesc
|
||||
issueLat=12
|
||||
opClass=FloatDiv
|
||||
opLat=12
|
||||
|
||||
[system.cpu.fuPool.FUList3.opList2]
|
||||
type=OpDesc
|
||||
issueLat=24
|
||||
opClass=FloatSqrt
|
||||
opLat=24
|
||||
|
||||
[system.cpu.fuPool.FUList4]
|
||||
type=FUDesc
|
||||
children=opList0
|
||||
count=0
|
||||
opList=system.cpu.fuPool.FUList4.opList0
|
||||
|
||||
[system.cpu.fuPool.FUList4.opList0]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=MemRead
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5]
|
||||
type=FUDesc
|
||||
children=opList0
|
||||
count=0
|
||||
opList=system.cpu.fuPool.FUList5.opList0
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList0]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=MemWrite
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList6]
|
||||
type=FUDesc
|
||||
children=opList0 opList1
|
||||
count=4
|
||||
opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1
|
||||
|
||||
[system.cpu.fuPool.FUList6.opList0]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=MemRead
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList6.opList1]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=MemWrite
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList7]
|
||||
type=FUDesc
|
||||
children=opList0
|
||||
count=1
|
||||
opList=system.cpu.fuPool.FUList7.opList0
|
||||
|
||||
[system.cpu.fuPool.FUList7.opList0]
|
||||
type=OpDesc
|
||||
issueLat=3
|
||||
opClass=IprAccess
|
||||
opLat=3
|
||||
|
||||
[system.cpu.icache]
|
||||
type=BaseCache
|
||||
adaptive_compression=false
|
||||
|
|
@ -308,7 +115,6 @@ assoc=2
|
|||
block_size=64
|
||||
compressed_bus=false
|
||||
compression_latency=0
|
||||
do_copy=false
|
||||
hash_delay=1
|
||||
hit_latency=1
|
||||
latency=1
|
||||
|
|
@ -348,7 +154,6 @@ assoc=2
|
|||
block_size=64
|
||||
compressed_bus=false
|
||||
compression_latency=0
|
||||
do_copy=false
|
||||
hash_delay=1
|
||||
hit_latency=1
|
||||
latency=1
|
||||
|
|
@ -384,20 +189,33 @@ mem_side=system.membus.port[1]
|
|||
[system.cpu.toL2Bus]
|
||||
type=Bus
|
||||
bus_id=0
|
||||
clock=1000
|
||||
responder_set=false
|
||||
width=64
|
||||
port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
|
||||
|
||||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
cmd=hello
|
||||
cmd=perlbmk -I. -I lib lgred.makerand.pl
|
||||
cwd=build/ALPHA_SE/tests/opt/long/40.perlbmk/alpha/linux/simple-timing
|
||||
egid=100
|
||||
env=
|
||||
executable=tests/test-progs/hello/bin/alpha/linux/hello
|
||||
euid=100
|
||||
executable=/dist/m5/cpu2000/binaries/alpha/tru64/perlbmk
|
||||
gid=100
|
||||
input=cin
|
||||
output=cout
|
||||
pid=100
|
||||
ppid=99
|
||||
system=system
|
||||
uid=100
|
||||
|
||||
[system.membus]
|
||||
type=Bus
|
||||
bus_id=0
|
||||
clock=1000
|
||||
responder_set=false
|
||||
width=64
|
||||
port=system.physmem.port system.cpu.l2cache.mem_side
|
||||
|
||||
[system.physmem]
|
||||
|
|
@ -409,6 +227,7 @@ port=system.membus.port[0]
|
|||
|
||||
[trace]
|
||||
bufsize=0
|
||||
cycle=0
|
||||
dump_on_exit=false
|
||||
file=cout
|
||||
flags=
|
||||
|
|
|
|||
|
|
@ -19,19 +19,54 @@ mem_mode=atomic
|
|||
[system.membus]
|
||||
type=Bus
|
||||
bus_id=0
|
||||
clock=1000
|
||||
width=64
|
||||
responder_set=false
|
||||
|
||||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
cmd=hello
|
||||
executable=tests/test-progs/hello/bin/alpha/linux/hello
|
||||
cmd=perlbmk -I. -I lib lgred.makerand.pl
|
||||
executable=/dist/m5/cpu2000/binaries/alpha/tru64/perlbmk
|
||||
input=cin
|
||||
output=cout
|
||||
env=
|
||||
cwd=build/ALPHA_SE/tests/opt/long/40.perlbmk/alpha/linux/simple-timing
|
||||
system=system
|
||||
uid=100
|
||||
euid=100
|
||||
gid=100
|
||||
egid=100
|
||||
pid=100
|
||||
ppid=99
|
||||
|
||||
[system.cpu.dcache]
|
||||
[system.cpu]
|
||||
type=TimingSimpleCPU
|
||||
max_insts_any_thread=0
|
||||
max_insts_all_threads=0
|
||||
max_loads_any_thread=0
|
||||
max_loads_all_threads=0
|
||||
progress_interval=0
|
||||
system=system
|
||||
cpu_id=0
|
||||
workload=system.cpu.workload
|
||||
clock=1
|
||||
phase=0
|
||||
defer_registration=false
|
||||
// width not specified
|
||||
function_trace=false
|
||||
function_trace_start=0
|
||||
// simulate_stalls not specified
|
||||
|
||||
[system.cpu.toL2Bus]
|
||||
type=Bus
|
||||
bus_id=0
|
||||
clock=1000
|
||||
width=64
|
||||
responder_set=false
|
||||
|
||||
[system.cpu.icache]
|
||||
type=BaseCache
|
||||
size=262144
|
||||
size=131072
|
||||
assoc=2
|
||||
block_size=64
|
||||
latency=1
|
||||
|
|
@ -39,7 +74,6 @@ mshrs=10
|
|||
tgts_per_mshr=5
|
||||
write_buffers=8
|
||||
prioritizeRequests=false
|
||||
do_copy=false
|
||||
protocol=null
|
||||
trace_addr=0
|
||||
hash_delay=1
|
||||
|
|
@ -68,214 +102,9 @@ prefetch_use_cpu_id=true
|
|||
prefetch_data_accesses_only=false
|
||||
hit_latency=1
|
||||
|
||||
[system.cpu.fuPool.FUList0.opList0]
|
||||
type=OpDesc
|
||||
opClass=IntAlu
|
||||
opLat=1
|
||||
issueLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList0]
|
||||
type=FUDesc
|
||||
opList=system.cpu.fuPool.FUList0.opList0
|
||||
count=6
|
||||
|
||||
[system.cpu.fuPool.FUList1.opList0]
|
||||
type=OpDesc
|
||||
opClass=IntMult
|
||||
opLat=3
|
||||
issueLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList1.opList1]
|
||||
type=OpDesc
|
||||
opClass=IntDiv
|
||||
opLat=20
|
||||
issueLat=19
|
||||
|
||||
[system.cpu.fuPool.FUList1]
|
||||
type=FUDesc
|
||||
opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
|
||||
count=2
|
||||
|
||||
[system.cpu.fuPool.FUList2.opList0]
|
||||
type=OpDesc
|
||||
opClass=FloatAdd
|
||||
opLat=2
|
||||
issueLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList2.opList1]
|
||||
type=OpDesc
|
||||
opClass=FloatCmp
|
||||
opLat=2
|
||||
issueLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList2.opList2]
|
||||
type=OpDesc
|
||||
opClass=FloatCvt
|
||||
opLat=2
|
||||
issueLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList2]
|
||||
type=FUDesc
|
||||
opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
|
||||
count=4
|
||||
|
||||
[system.cpu.fuPool.FUList3.opList0]
|
||||
type=OpDesc
|
||||
opClass=FloatMult
|
||||
opLat=4
|
||||
issueLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList3.opList1]
|
||||
type=OpDesc
|
||||
opClass=FloatDiv
|
||||
opLat=12
|
||||
issueLat=12
|
||||
|
||||
[system.cpu.fuPool.FUList3.opList2]
|
||||
type=OpDesc
|
||||
opClass=FloatSqrt
|
||||
opLat=24
|
||||
issueLat=24
|
||||
|
||||
[system.cpu.fuPool.FUList3]
|
||||
type=FUDesc
|
||||
opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
|
||||
count=2
|
||||
|
||||
[system.cpu.fuPool.FUList4.opList0]
|
||||
type=OpDesc
|
||||
opClass=MemRead
|
||||
opLat=1
|
||||
issueLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList4]
|
||||
type=FUDesc
|
||||
opList=system.cpu.fuPool.FUList4.opList0
|
||||
count=0
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList0]
|
||||
type=OpDesc
|
||||
opClass=MemWrite
|
||||
opLat=1
|
||||
issueLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5]
|
||||
type=FUDesc
|
||||
opList=system.cpu.fuPool.FUList5.opList0
|
||||
count=0
|
||||
|
||||
[system.cpu.fuPool.FUList6.opList0]
|
||||
type=OpDesc
|
||||
opClass=MemRead
|
||||
opLat=1
|
||||
issueLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList6.opList1]
|
||||
type=OpDesc
|
||||
opClass=MemWrite
|
||||
opLat=1
|
||||
issueLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList6]
|
||||
type=FUDesc
|
||||
opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1
|
||||
count=4
|
||||
|
||||
[system.cpu.fuPool.FUList7.opList0]
|
||||
type=OpDesc
|
||||
opClass=IprAccess
|
||||
opLat=3
|
||||
issueLat=3
|
||||
|
||||
[system.cpu.fuPool.FUList7]
|
||||
type=FUDesc
|
||||
opList=system.cpu.fuPool.FUList7.opList0
|
||||
count=1
|
||||
|
||||
[system.cpu.fuPool]
|
||||
type=FUPool
|
||||
FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7
|
||||
|
||||
[system.cpu]
|
||||
type=DerivO3CPU
|
||||
clock=1
|
||||
numThreads=1
|
||||
activity=0
|
||||
workload=system.cpu.workload
|
||||
mem=system.cpu.dcache
|
||||
checker=null
|
||||
max_insts_any_thread=0
|
||||
max_insts_all_threads=0
|
||||
max_loads_any_thread=0
|
||||
max_loads_all_threads=0
|
||||
cachePorts=200
|
||||
decodeToFetchDelay=1
|
||||
renameToFetchDelay=1
|
||||
iewToFetchDelay=1
|
||||
commitToFetchDelay=1
|
||||
fetchWidth=8
|
||||
renameToDecodeDelay=1
|
||||
iewToDecodeDelay=1
|
||||
commitToDecodeDelay=1
|
||||
fetchToDecodeDelay=1
|
||||
decodeWidth=8
|
||||
iewToRenameDelay=1
|
||||
commitToRenameDelay=1
|
||||
decodeToRenameDelay=1
|
||||
renameWidth=8
|
||||
commitToIEWDelay=1
|
||||
renameToIEWDelay=2
|
||||
issueToExecuteDelay=1
|
||||
dispatchWidth=8
|
||||
issueWidth=8
|
||||
wbWidth=8
|
||||
wbDepth=1
|
||||
fuPool=system.cpu.fuPool
|
||||
iewToCommitDelay=1
|
||||
renameToROBDelay=1
|
||||
commitWidth=8
|
||||
squashWidth=8
|
||||
trapLatency=13
|
||||
backComSize=5
|
||||
forwardComSize=5
|
||||
predType=tournament
|
||||
localPredictorSize=2048
|
||||
localCtrBits=2
|
||||
localHistoryTableSize=2048
|
||||
localHistoryBits=11
|
||||
globalPredictorSize=8192
|
||||
globalCtrBits=2
|
||||
globalHistoryBits=13
|
||||
choicePredictorSize=8192
|
||||
choiceCtrBits=2
|
||||
BTBEntries=4096
|
||||
BTBTagSize=16
|
||||
RASSize=16
|
||||
LQEntries=32
|
||||
SQEntries=32
|
||||
LFSTSize=1024
|
||||
SSITSize=1024
|
||||
numPhysIntRegs=256
|
||||
numPhysFloatRegs=256
|
||||
numIQEntries=64
|
||||
numROBEntries=192
|
||||
smtNumFetchingThreads=1
|
||||
smtFetchPolicy=SingleThread
|
||||
smtLSQPolicy=Partitioned
|
||||
smtLSQThreshold=100
|
||||
smtIQPolicy=Partitioned
|
||||
smtIQThreshold=100
|
||||
smtROBPolicy=Partitioned
|
||||
smtROBThreshold=100
|
||||
smtCommitPolicy=RoundRobin
|
||||
instShiftAmt=2
|
||||
defer_registration=false
|
||||
function_trace=false
|
||||
function_trace_start=0
|
||||
|
||||
[system.cpu.icache]
|
||||
[system.cpu.dcache]
|
||||
type=BaseCache
|
||||
size=131072
|
||||
size=262144
|
||||
assoc=2
|
||||
block_size=64
|
||||
latency=1
|
||||
|
|
@ -283,7 +112,6 @@ mshrs=10
|
|||
tgts_per_mshr=5
|
||||
write_buffers=8
|
||||
prioritizeRequests=false
|
||||
do_copy=false
|
||||
protocol=null
|
||||
trace_addr=0
|
||||
hash_delay=1
|
||||
|
|
@ -322,7 +150,6 @@ mshrs=10
|
|||
tgts_per_mshr=5
|
||||
write_buffers=8
|
||||
prioritizeRequests=false
|
||||
do_copy=false
|
||||
protocol=null
|
||||
trace_addr=0
|
||||
hash_delay=1
|
||||
|
|
@ -351,13 +178,10 @@ prefetch_use_cpu_id=true
|
|||
prefetch_data_accesses_only=false
|
||||
hit_latency=1
|
||||
|
||||
[system.cpu.toL2Bus]
|
||||
type=Bus
|
||||
bus_id=0
|
||||
|
||||
[trace]
|
||||
flags=
|
||||
start=0
|
||||
cycle=0
|
||||
bufsize=0
|
||||
file=cout
|
||||
dump_on_exit=false
|
||||
|
|
@ -396,8 +220,9 @@ print_cpseq=false
|
|||
print_reg_delta=false
|
||||
pc_symbol=true
|
||||
intel_format=false
|
||||
legion_lockstep=false
|
||||
trace_system=client
|
||||
|
||||
[debug]
|
||||
break_cycles=
|
||||
[statsreset]
|
||||
reset_cycle=0
|
||||
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -1,3 +1,2 @@
|
|||
warn: Entering event queue @ 0. Starting simulation...
|
||||
warn: cycle 0: fault (page_table_fault) detected @ PC 0x000000
|
||||
warn: Increasing stack 0x11ff92000:0x11ff9b000 to 0x11ff90000:0x11ff9b000 because of access to 0x11ff91ff0
|
||||
warn: ignoring syscall sigprocmask(1, 0, ...)
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -7,11 +7,9 @@ max_tick=0
|
|||
output_file=cout
|
||||
progress_interval=0
|
||||
|
||||
[debug]
|
||||
break_cycles=
|
||||
|
||||
[exetrace]
|
||||
intel_format=false
|
||||
legion_lockstep=false
|
||||
pc_symbol=true
|
||||
print_cpseq=false
|
||||
print_cycle=true
|
||||
|
|
@ -102,14 +100,15 @@ max_insts_all_threads=0
|
|||
max_insts_any_thread=0
|
||||
max_loads_all_threads=0
|
||||
max_loads_any_thread=0
|
||||
mem=system.cpu.dcache
|
||||
numIQEntries=64
|
||||
numPhysFloatRegs=256
|
||||
numPhysIntRegs=256
|
||||
numROBEntries=192
|
||||
numRobs=1
|
||||
numThreads=1
|
||||
phase=0
|
||||
predType=tournament
|
||||
progress_interval=0
|
||||
renameToDecodeDelay=1
|
||||
renameToFetchDelay=1
|
||||
renameToIEWDelay=2
|
||||
|
|
@ -131,7 +130,6 @@ assoc=2
|
|||
block_size=64
|
||||
compressed_bus=false
|
||||
compression_latency=0
|
||||
do_copy=false
|
||||
hash_delay=1
|
||||
hit_latency=1
|
||||
latency=1
|
||||
|
|
@ -308,7 +306,6 @@ assoc=2
|
|||
block_size=64
|
||||
compressed_bus=false
|
||||
compression_latency=0
|
||||
do_copy=false
|
||||
hash_delay=1
|
||||
hit_latency=1
|
||||
latency=1
|
||||
|
|
@ -348,7 +345,6 @@ assoc=2
|
|||
block_size=64
|
||||
compressed_bus=false
|
||||
compression_latency=0
|
||||
do_copy=false
|
||||
hash_delay=1
|
||||
hit_latency=1
|
||||
latency=1
|
||||
|
|
@ -384,20 +380,33 @@ mem_side=system.membus.port[1]
|
|||
[system.cpu.toL2Bus]
|
||||
type=Bus
|
||||
bus_id=0
|
||||
clock=1000
|
||||
responder_set=false
|
||||
width=64
|
||||
port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
|
||||
|
||||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
cmd=hello
|
||||
cmd=vortex lendian.raw
|
||||
cwd=build/ALPHA_SE/tests/opt/long/50.vortex/alpha/linux/o3-timing
|
||||
egid=100
|
||||
env=
|
||||
executable=tests/test-progs/hello/bin/alpha/linux/hello
|
||||
euid=100
|
||||
executable=/dist/m5/cpu2000/binaries/alpha/tru64/vortex
|
||||
gid=100
|
||||
input=cin
|
||||
output=cout
|
||||
pid=100
|
||||
ppid=99
|
||||
system=system
|
||||
uid=100
|
||||
|
||||
[system.membus]
|
||||
type=Bus
|
||||
bus_id=0
|
||||
clock=1000
|
||||
responder_set=false
|
||||
width=64
|
||||
port=system.physmem.port system.cpu.l2cache.mem_side
|
||||
|
||||
[system.physmem]
|
||||
|
|
@ -409,6 +418,7 @@ port=system.membus.port[0]
|
|||
|
||||
[trace]
|
||||
bufsize=0
|
||||
cycle=0
|
||||
dump_on_exit=false
|
||||
file=cout
|
||||
flags=
|
||||
|
|
|
|||
|
|
@ -19,54 +19,25 @@ mem_mode=atomic
|
|||
[system.membus]
|
||||
type=Bus
|
||||
bus_id=0
|
||||
clock=1000
|
||||
width=64
|
||||
responder_set=false
|
||||
|
||||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
cmd=hello
|
||||
executable=tests/test-progs/hello/bin/alpha/linux/hello
|
||||
cmd=vortex lendian.raw
|
||||
executable=/dist/m5/cpu2000/binaries/alpha/tru64/vortex
|
||||
input=cin
|
||||
output=cout
|
||||
env=
|
||||
cwd=build/ALPHA_SE/tests/opt/long/50.vortex/alpha/linux/o3-timing
|
||||
system=system
|
||||
|
||||
[system.cpu.dcache]
|
||||
type=BaseCache
|
||||
size=262144
|
||||
assoc=2
|
||||
block_size=64
|
||||
latency=1
|
||||
mshrs=10
|
||||
tgts_per_mshr=5
|
||||
write_buffers=8
|
||||
prioritizeRequests=false
|
||||
do_copy=false
|
||||
protocol=null
|
||||
trace_addr=0
|
||||
hash_delay=1
|
||||
repl=null
|
||||
compressed_bus=false
|
||||
store_compressed=false
|
||||
adaptive_compression=false
|
||||
compression_latency=0
|
||||
block_size=64
|
||||
max_miss_count=0
|
||||
addr_range=[0,18446744073709551615]
|
||||
split=false
|
||||
split_size=0
|
||||
lifo=false
|
||||
two_queue=false
|
||||
prefetch_miss=false
|
||||
prefetch_access=false
|
||||
prefetcher_size=100
|
||||
prefetch_past_page=false
|
||||
prefetch_serial_squash=false
|
||||
prefetch_latency=10
|
||||
prefetch_degree=1
|
||||
prefetch_policy=none
|
||||
prefetch_cache_check_push=true
|
||||
prefetch_use_cpu_id=true
|
||||
prefetch_data_accesses_only=false
|
||||
hit_latency=1
|
||||
uid=100
|
||||
euid=100
|
||||
gid=100
|
||||
egid=100
|
||||
pid=100
|
||||
ppid=99
|
||||
|
||||
[system.cpu.fuPool.FUList0.opList0]
|
||||
type=OpDesc
|
||||
|
|
@ -199,15 +170,16 @@ FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUL
|
|||
[system.cpu]
|
||||
type=DerivO3CPU
|
||||
clock=1
|
||||
phase=0
|
||||
numThreads=1
|
||||
activity=0
|
||||
workload=system.cpu.workload
|
||||
mem=system.cpu.dcache
|
||||
checker=null
|
||||
max_insts_any_thread=0
|
||||
max_insts_all_threads=0
|
||||
max_loads_any_thread=0
|
||||
max_loads_all_threads=0
|
||||
progress_interval=0
|
||||
cachePorts=200
|
||||
decodeToFetchDelay=1
|
||||
renameToFetchDelay=1
|
||||
|
|
@ -283,7 +255,44 @@ mshrs=10
|
|||
tgts_per_mshr=5
|
||||
write_buffers=8
|
||||
prioritizeRequests=false
|
||||
do_copy=false
|
||||
protocol=null
|
||||
trace_addr=0
|
||||
hash_delay=1
|
||||
repl=null
|
||||
compressed_bus=false
|
||||
store_compressed=false
|
||||
adaptive_compression=false
|
||||
compression_latency=0
|
||||
block_size=64
|
||||
max_miss_count=0
|
||||
addr_range=[0,18446744073709551615]
|
||||
split=false
|
||||
split_size=0
|
||||
lifo=false
|
||||
two_queue=false
|
||||
prefetch_miss=false
|
||||
prefetch_access=false
|
||||
prefetcher_size=100
|
||||
prefetch_past_page=false
|
||||
prefetch_serial_squash=false
|
||||
prefetch_latency=10
|
||||
prefetch_degree=1
|
||||
prefetch_policy=none
|
||||
prefetch_cache_check_push=true
|
||||
prefetch_use_cpu_id=true
|
||||
prefetch_data_accesses_only=false
|
||||
hit_latency=1
|
||||
|
||||
[system.cpu.dcache]
|
||||
type=BaseCache
|
||||
size=262144
|
||||
assoc=2
|
||||
block_size=64
|
||||
latency=1
|
||||
mshrs=10
|
||||
tgts_per_mshr=5
|
||||
write_buffers=8
|
||||
prioritizeRequests=false
|
||||
protocol=null
|
||||
trace_addr=0
|
||||
hash_delay=1
|
||||
|
|
@ -322,7 +331,6 @@ mshrs=10
|
|||
tgts_per_mshr=5
|
||||
write_buffers=8
|
||||
prioritizeRequests=false
|
||||
do_copy=false
|
||||
protocol=null
|
||||
trace_addr=0
|
||||
hash_delay=1
|
||||
|
|
@ -354,10 +362,14 @@ hit_latency=1
|
|||
[system.cpu.toL2Bus]
|
||||
type=Bus
|
||||
bus_id=0
|
||||
clock=1000
|
||||
width=64
|
||||
responder_set=false
|
||||
|
||||
[trace]
|
||||
flags=
|
||||
start=0
|
||||
cycle=0
|
||||
bufsize=0
|
||||
file=cout
|
||||
dump_on_exit=false
|
||||
|
|
@ -396,8 +408,9 @@ print_cpseq=false
|
|||
print_reg_delta=false
|
||||
pc_symbol=true
|
||||
intel_format=false
|
||||
legion_lockstep=false
|
||||
trace_system=client
|
||||
|
||||
[debug]
|
||||
break_cycles=
|
||||
[statsreset]
|
||||
reset_cycle=0
|
||||
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
158
tests/long/50.vortex/ref/alpha/linux/o3-timing/smred.msg
Normal file
158
tests/long/50.vortex/ref/alpha/linux/o3-timing/smred.msg
Normal file
|
|
@ -0,0 +1,158 @@
|
|||
|
||||
SYSTEM TYPE...
|
||||
__ZTC__ := False
|
||||
__UNIX__ := True
|
||||
__RISC__ := True
|
||||
SPEC_CPU2000_LP64 := True
|
||||
__MAC__ := False
|
||||
__BCC__ := False
|
||||
__BORLANDC__ := False
|
||||
__GUI__ := False
|
||||
__WTC__ := False
|
||||
__HP__ := False
|
||||
|
||||
CODE OPTIONS...
|
||||
__MACROIZE_HM__ := True
|
||||
__MACROIZE_MEM__ := True
|
||||
ENV01 := True
|
||||
USE_HPP_STYPE_HDRS := False
|
||||
USE_H_STYPE_HDRS := False
|
||||
|
||||
CODE INCLUSION PARAMETERS...
|
||||
INCLUDE_ALL_CODE := False
|
||||
INCLUDE_DELETE_CODE := True
|
||||
__SWAP_GRP_POS__ := True
|
||||
__INCLUDE_MTRX__ := False
|
||||
__BAD_CODE__ := False
|
||||
API_INCLUDE := False
|
||||
BE_CAREFUL := False
|
||||
OLDWAY := False
|
||||
NOTUSED := False
|
||||
|
||||
SYSTEM PARAMETERS...
|
||||
EXT_ENUM := 999999999L
|
||||
CHUNK_CONSTANT := 55555555
|
||||
CORE_CONSTANT := 55555555
|
||||
CORE_LIMIT := 20971520
|
||||
CorePage_Size := 384000
|
||||
ALIGN_BYTES := True
|
||||
CORE_BLOCK_ALIGN := 8
|
||||
FAR_MEM := False
|
||||
|
||||
MEMORY MANAGEMENT PARAMETERS...
|
||||
SYSTEM_ALLOC := True
|
||||
SYSTEM_FREESTORE := True
|
||||
__NO_DISKCACHE__ := False
|
||||
__FREEZE_VCHUNKS__ := True
|
||||
__FREEZE_GRP_PACKETS__ := True
|
||||
__MINIMIZE_TREE_CACHE__:= True
|
||||
|
||||
SYSTEM STD PARAMETERS...
|
||||
__STDOUT__ := False
|
||||
NULL := 0
|
||||
LPTR := False
|
||||
False_Status := 1
|
||||
True_Status := 0
|
||||
LARGE := True
|
||||
TWOBYTE_BOOL := False
|
||||
__NOSTR__ := False
|
||||
|
||||
MEMORY VALIDATION PARAMETERS...
|
||||
CORE_CRC_CHECK := False
|
||||
VALIDATE_MEM_CHUNKS := False
|
||||
|
||||
SYSTEM DEBUG OPTIONS...
|
||||
DEBUG := False
|
||||
MCSTAT := False
|
||||
TRACKBACK := False
|
||||
FLUSH_FILES := False
|
||||
DEBUG_CORE0 := False
|
||||
DEBUG_RISC := False
|
||||
__TREE_BUG__ := False
|
||||
__TRACK_FILE_READS__ := False
|
||||
PAGE_SPACE := False
|
||||
LEAVE_NO_TRACE := True
|
||||
NULL_TRACE_STRS := False
|
||||
|
||||
TIME PARAMETERS...
|
||||
CLOCK_IS_LONG := False
|
||||
__DISPLAY_TIME__ := False
|
||||
__TREE_TIME__ := False
|
||||
__DISPLAY_ERRORS__ := False
|
||||
|
||||
API MACROS...
|
||||
__BMT01__ := True
|
||||
OPTIMIZE := True
|
||||
|
||||
END OF DEFINES.
|
||||
|
||||
|
||||
|
||||
... IMPLODE MEMORY ...
|
||||
|
||||
SWAP to DiskCache := False
|
||||
|
||||
FREEZE_GRP_PACKETS:= True
|
||||
|
||||
QueBug := 1000
|
||||
|
||||
sizeof(boolean) = 4
|
||||
sizeof(sizetype) = 4
|
||||
sizeof(chunkstruc) = 32
|
||||
|
||||
sizeof(shorttype ) = 2
|
||||
sizeof(idtype ) = 2
|
||||
sizeof(sizetype ) = 4
|
||||
sizeof(indextype ) = 4
|
||||
sizeof(numtype ) = 4
|
||||
sizeof(handletype) = 4
|
||||
sizeof(tokentype ) = 8
|
||||
|
||||
sizeof(short ) = 2
|
||||
sizeof(int ) = 4
|
||||
|
||||
sizeof(lt64 ) = 4
|
||||
sizeof(farlongtype) = 4
|
||||
sizeof(long ) = 8
|
||||
sizeof(longaddr ) = 8
|
||||
|
||||
sizeof(float ) = 4
|
||||
sizeof(double ) = 8
|
||||
|
||||
sizeof(addrtype ) = 8
|
||||
sizeof(char * ) = 8
|
||||
ALLOC CORE_1 :: 16
|
||||
BHOOLE NATH
|
||||
|
||||
OPEN File ./input/lendian.rnv
|
||||
*Status = 0
|
||||
DB HDR restored from FileVbn[ 0]
|
||||
DB BlkDirOffset : @ 2030c0
|
||||
DB BlkDirChunk : Chunk[ 10] AT Vbn[3146]
|
||||
DB BlkTknChunk : Chunk[ 11] AT Vbn[3147]
|
||||
DB BlkSizeChunk : Chunk[ 12] AT Vbn[3148]
|
||||
DB Handle Chunk's StackPtr = 20797
|
||||
|
||||
DB[ 1] LOADED; Handles= 20797
|
||||
KERNEL in CORE[ 1] Restored @ 40054800
|
||||
|
||||
OPEN File ./input/lendian.wnv
|
||||
*Status = 0
|
||||
DB HDR restored from FileVbn[ 0]
|
||||
DB BlkDirOffset : @ 21c40
|
||||
DB BlkDirChunk : Chunk[ 31] AT Vbn[ 81]
|
||||
DB BlkTknChunk : Chunk[ 32] AT Vbn[ 82]
|
||||
DB BlkSizeChunk : Chunk[ 33] AT Vbn[ 83]
|
||||
DB Handle Chunk's StackPtr = 17
|
||||
|
||||
DB[ 2] LOADED; Handles= 17
|
||||
VORTEx_Status == -8 || fffffff8
|
||||
|
||||
BE HERE NOW !!!
|
||||
|
||||
|
||||
|
||||
... VORTEx ON LINE ...
|
||||
|
||||
|
||||
... END OF SESSION ...
|
||||
258
tests/long/50.vortex/ref/alpha/linux/o3-timing/smred.out
Normal file
258
tests/long/50.vortex/ref/alpha/linux/o3-timing/smred.out
Normal file
|
|
@ -0,0 +1,258 @@
|
|||
CREATE Db Header and Db Primal ...
|
||||
NEW DB [ 3] Created.
|
||||
|
||||
VORTEX INPUT PARAMETERS::
|
||||
MESSAGE FileName: smred.msg
|
||||
OUTPUT FileName: smred.out
|
||||
DISK CACHE FileName: NULL
|
||||
PART DB FileName: parts.db
|
||||
DRAW DB FileName: draw.db
|
||||
PERSON DB FileName: emp.db
|
||||
PERSONS Data FileName: ./input/persons.250
|
||||
PARTS Count : 100
|
||||
OUTER Loops : 1
|
||||
INNER Loops : 1
|
||||
LOOKUP Parts : 25
|
||||
DELETE Parts : 10
|
||||
STUFF Parts : 10
|
||||
DEPTH Traverse: 5
|
||||
% DECREASE Parts : 0
|
||||
% INCREASE LookUps : 0
|
||||
% INCREASE Deletes : 0
|
||||
% INCREASE Stuffs : 0
|
||||
FREEZE_PACKETS : 1
|
||||
ALLOC_CHUNKS : 10000
|
||||
EXTEND_CHUNKS : 5000
|
||||
DELETE Draw objects : True
|
||||
DELETE Part objects : False
|
||||
QUE_BUG : 1000
|
||||
VOID_BOUNDARY : 67108864
|
||||
VOID_RESERVE : 1048576
|
||||
|
||||
COMMIT_DBS : False
|
||||
|
||||
|
||||
|
||||
BMT TEST :: files...
|
||||
EdbName := PartLib
|
||||
EdbFileName := parts.db
|
||||
DrwName := DrawLib
|
||||
DrwFileName := draw.db
|
||||
EmpName := PersonLib
|
||||
EmpFileName := emp.db
|
||||
|
||||
Swap to DiskCache := False
|
||||
Freeze the cache := True
|
||||
|
||||
|
||||
BMT TEST :: parms...
|
||||
DeBug modulo := 1000
|
||||
Create Parts count:= 100
|
||||
Outer Loops := 1
|
||||
Inner Loops := 1
|
||||
Look Ups := 25
|
||||
Delete Parts := 10
|
||||
Stuff Parts := 10
|
||||
Traverse Limit := 5
|
||||
Delete Draws := True
|
||||
Delete Parts := False
|
||||
Delete ALL Parts := after every <mod 0>Outer Loop
|
||||
|
||||
INITIALIZE LIBRARY ::
|
||||
|
||||
INITIALIZE SCHEMA ::
|
||||
Primal_CreateDb Accessed !!!
|
||||
CREATE Db Header and Db Primal ...
|
||||
NEW DB [ 4] Created.
|
||||
PartLibCreate:: Db[ 4]; VpartsDir= 1
|
||||
|
||||
Part Count= 1
|
||||
|
||||
Initialize the Class maps
|
||||
LIST HEADS loaded ... DbListHead_Class = 207
|
||||
DbListNode_Class = 206
|
||||
|
||||
...NOTE... ShellLoadCode:: Class[ 228] will NOT be Activated.
|
||||
|
||||
|
||||
...NOTE... ShellLoadCode:: Class[ 229] will NOT be Activated.
|
||||
|
||||
Primal_CreateDb Accessed !!!
|
||||
CREATE Db Header and Db Primal ...
|
||||
NEW DB [ 5] Created.
|
||||
DrawLibCreate:: Db[ 5]; VpartsDir= 1
|
||||
|
||||
Initialize the Class maps of this schema.
|
||||
Primal_CreateDb Accessed !!!
|
||||
CREATE Db Header and Db Primal ...
|
||||
NEW DB [ 6] Created.
|
||||
|
||||
***NOTE*** Persons Library Extended!
|
||||
|
||||
Create <131072> Persons.
|
||||
ItNum 0. Person[ 6: 5]. Name= Riddell , Robert V. ;
|
||||
|
||||
LAST Person Read::
|
||||
ItNum 250. Person[ 6: 503]. Name= Gonzales , Warren X. ;
|
||||
|
||||
BUILD <Query0> for <Part2> class::
|
||||
|
||||
if (link[1].length >= 5) ::
|
||||
|
||||
Build Query2 for <Address> class::
|
||||
|
||||
if (State == CA || State == T*)
|
||||
|
||||
Build Query1 for <Person> class::
|
||||
|
||||
if (LastName >= H* && LastName <= P* && Query0(Residence)) ::
|
||||
|
||||
BUILD <Query3> for <DrawObj> class::
|
||||
|
||||
if (Id >= 3000
|
||||
&& (Id >= 3000 && Id <= 3001)
|
||||
&& Id >= 3002)
|
||||
|
||||
BUILD <Query4> for <NamedDrawObj> class::
|
||||
|
||||
if (Nam == Pre*
|
||||
|| (Nam == ??Mid??? || == Pre??Mid?? || == ??Post
|
||||
|| == Pre??Post || == ??Mid???Post || == Pre??Mid???Post)
|
||||
&& Id <= 7)
|
||||
SEED := 1008; Swap = False; RgnEntries = 135
|
||||
|
||||
OUTER LOOP [ 1] : NewParts = 100 LookUps = 25 StuffParts = 10.
|
||||
|
||||
Create 100 New Parts
|
||||
Create Part 1. Token[ 4: 2].
|
||||
|
||||
< 100> Parts Created. CurrentId= 100
|
||||
|
||||
Connect each instantiated Part TO 3 unique Parts
|
||||
Connect Part 1. Token[ 4: 2]
|
||||
Connect Part 25. Token[ 4: 26] FromList= 26.
|
||||
Connect Part 12. Token[ 4: 13] FromList= 13.
|
||||
Connect Part 59. Token[ 4: 60] FromList= 60.
|
||||
|
||||
SET <DrawObjs> entries::
|
||||
1. [ 5: 5] := <1 >; @[: 6]
|
||||
Iteration count = 100
|
||||
|
||||
SET <NamedDrawObjs> entries::
|
||||
1. [ 5: 39] := <14 >;
|
||||
Iteration count = 12
|
||||
|
||||
SET <LibRectangles> entries::
|
||||
1. [ 5: 23] := <8 >; @[: 24]
|
||||
Iteration count = 12
|
||||
|
||||
LIST <DbRectangles> entries::
|
||||
1. [ 5: 23]
|
||||
Iteration count = 12
|
||||
|
||||
SET <PersonNames > entries::
|
||||
Iteration count = 250
|
||||
|
||||
COMMIT All Image copies:: Release=<True>; Max Parts= 100
|
||||
< 100> Part images' Committed.
|
||||
< 0> are Named.
|
||||
< 50> Point images' Committed.
|
||||
< 81> Person images' Committed.
|
||||
|
||||
COMMIT Parts(* 100)
|
||||
|
||||
Commit TestObj_Class in <Primal> DB.
|
||||
ItNum 0. Token[ 0: 0]. TestObj Committed.
|
||||
< 0> TestObj images' Committed.
|
||||
|
||||
Commit CartesianPoint_Class in <Primal> DB.
|
||||
ItNum 0. Token[ 0: 0]. CartesianPoint Committed.
|
||||
< 0> CartesianPoint images' Committed.
|
||||
|
||||
BEGIN Inner Loop Sequence::.
|
||||
|
||||
INNER LOOP [ 1: 1] :
|
||||
|
||||
LOOK UP 25 Random Parts and Export each Part.
|
||||
|
||||
LookUp for 26 parts; Asserts = 8
|
||||
<Part2 > Asserts = 2; NULL Asserts = 3.
|
||||
<DrawObj > Asserts = 0; NULL Asserts = 5.
|
||||
<NamedObj > Asserts = 0; NULL Asserts = 0.
|
||||
<Person > Asserts = 0; NULL Asserts = 5.
|
||||
<TestObj > Asserts = 60; NULL Asserts = 0.
|
||||
|
||||
DELETE 10 Random Parts.
|
||||
|
||||
PartDelete :: Token[ 4: 91].
|
||||
PartDisconnect:: Token[ 4: 91] id:= 90 for each link.
|
||||
DisConnect link [ 0]:= 50; PartToken[ 51: 51].
|
||||
DisConnect link [ 1]:= 17; PartToken[ 18: 18].
|
||||
DisConnect link [ 2]:= 72; PartToken[ 73: 73].
|
||||
DeleteFromList:: Vchunk[ 4: 91]. (* 1)
|
||||
DisConnect FromList[ 0]:= 56; Token[ 57: 57].
|
||||
Vlists[ 89] := 100;
|
||||
|
||||
Delete for 11 parts;
|
||||
|
||||
Traverse Count= 0
|
||||
|
||||
TRAVERSE PartId[ 6] and all Connections to 5 Levels
|
||||
SEED In Traverse Part [ 4: 65] @ Level = 4.
|
||||
|
||||
Traverse Count= 357
|
||||
Traverse Asserts = 5. True Tests = 1
|
||||
< 5> DrawObj objects DELETED.
|
||||
< 2> are Named.
|
||||
< 2> Point objects DELETED.
|
||||
|
||||
CREATE 10 Additional Parts
|
||||
|
||||
Create 10 New Parts
|
||||
Create Part 101. Token[ 4: 102].
|
||||
|
||||
< 10> Parts Created. CurrentId= 110
|
||||
|
||||
Connect each instantiated Part TO 3 unique Parts
|
||||
|
||||
COMMIT All Image copies:: Release=<True>; Max Parts= 110
|
||||
< 81> Part images' Committed.
|
||||
< 0> are Named.
|
||||
< 38> Point images' Committed.
|
||||
< 31> Person images' Committed.
|
||||
|
||||
COMMIT Parts(* 100)
|
||||
|
||||
Commit TestObj_Class in <Primal> DB.
|
||||
ItNum 0. Token[ 3: 4]. TestObj Committed.
|
||||
< 15> TestObj images' Committed.
|
||||
|
||||
Commit CartesianPoint_Class in <Primal> DB.
|
||||
ItNum 0. Token[ 3: 3]. CartesianPoint Committed.
|
||||
< 16> CartesianPoint images' Committed.
|
||||
|
||||
DELETE All TestObj objects;
|
||||
|
||||
Delete TestObj_Class in <Primal> DB.
|
||||
ItNum 0. Token[ 3: 4]. TestObj Deleted.
|
||||
< 15> TestObj objects Deleted.
|
||||
|
||||
Commit CartesianPoint_Class in <Primal> DB.
|
||||
ItNum 0. Token[ 3: 3]. CartesianPoint Deleted.
|
||||
< 16> CartesianPoint objects Deleted.
|
||||
|
||||
DELETE TestObj and Point objects...
|
||||
|
||||
END INNER LOOP [ 1: 1].
|
||||
|
||||
DELETE All TestObj objects;
|
||||
|
||||
Delete TestObj_Class in <Primal> DB.
|
||||
< 0> TestObj objects Deleted.
|
||||
|
||||
Commit CartesianPoint_Class in <Primal> DB.
|
||||
< 0> CartesianPoint objects Deleted.
|
||||
|
||||
DELETE TestObj and Point objects...
|
||||
STATUS= -201
|
||||
V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1!
|
||||
|
|
@ -1,3 +1 @@
|
|||
warn: Entering event queue @ 0. Starting simulation...
|
||||
warn: cycle 0: fault (page_table_fault) detected @ PC 0x000000
|
||||
warn: Increasing stack 0x11ff92000:0x11ff9b000 to 0x11ff90000:0x11ff9b000 because of access to 0x11ff91ff0
|
||||
|
|
|
|||
|
|
@ -1,13 +0,0 @@
|
|||
Hello world!
|
||||
M5 Simulator System
|
||||
|
||||
Copyright (c) 2001-2006
|
||||
The Regents of The University of Michigan
|
||||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Sep 5 2006 15:28:48
|
||||
M5 started Tue Sep 5 15:42:12 2006
|
||||
M5 executing on zizzer.eecs.umich.edu
|
||||
command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/o3-timing tests/run.py quick/00.hello/alpha/linux/o3-timing
|
||||
Exiting @ tick 6870 because target called exit()
|
||||
|
|
@ -7,11 +7,9 @@ max_tick=0
|
|||
output_file=cout
|
||||
progress_interval=0
|
||||
|
||||
[debug]
|
||||
break_cycles=
|
||||
|
||||
[exetrace]
|
||||
intel_format=false
|
||||
legion_lockstep=false
|
||||
pc_symbol=true
|
||||
print_cpseq=false
|
||||
print_cycle=true
|
||||
|
|
@ -53,352 +51,49 @@ mem_mode=atomic
|
|||
physmem=system.physmem
|
||||
|
||||
[system.cpu]
|
||||
type=DerivO3CPU
|
||||
children=dcache fuPool icache l2cache toL2Bus workload
|
||||
BTBEntries=4096
|
||||
BTBTagSize=16
|
||||
LFSTSize=1024
|
||||
LQEntries=32
|
||||
RASSize=16
|
||||
SQEntries=32
|
||||
SSITSize=1024
|
||||
activity=0
|
||||
backComSize=5
|
||||
choiceCtrBits=2
|
||||
choicePredictorSize=8192
|
||||
type=AtomicSimpleCPU
|
||||
children=workload
|
||||
clock=1
|
||||
commitToDecodeDelay=1
|
||||
commitToFetchDelay=1
|
||||
commitToIEWDelay=1
|
||||
commitToRenameDelay=1
|
||||
commitWidth=8
|
||||
decodeToFetchDelay=1
|
||||
decodeToRenameDelay=1
|
||||
decodeWidth=8
|
||||
cpu_id=0
|
||||
defer_registration=false
|
||||
dispatchWidth=8
|
||||
fetchToDecodeDelay=1
|
||||
fetchTrapLatency=1
|
||||
fetchWidth=8
|
||||
forwardComSize=5
|
||||
fuPool=system.cpu.fuPool
|
||||
function_trace=false
|
||||
function_trace_start=0
|
||||
globalCtrBits=2
|
||||
globalHistoryBits=13
|
||||
globalPredictorSize=8192
|
||||
iewToCommitDelay=1
|
||||
iewToDecodeDelay=1
|
||||
iewToFetchDelay=1
|
||||
iewToRenameDelay=1
|
||||
instShiftAmt=2
|
||||
issueToExecuteDelay=1
|
||||
issueWidth=8
|
||||
localCtrBits=2
|
||||
localHistoryBits=11
|
||||
localHistoryTableSize=2048
|
||||
localPredictorSize=2048
|
||||
max_insts_all_threads=0
|
||||
max_insts_any_thread=0
|
||||
max_loads_all_threads=0
|
||||
max_loads_any_thread=0
|
||||
mem=system.cpu.dcache
|
||||
numIQEntries=64
|
||||
numPhysFloatRegs=256
|
||||
numPhysIntRegs=256
|
||||
numROBEntries=192
|
||||
numRobs=1
|
||||
numThreads=1
|
||||
predType=tournament
|
||||
renameToDecodeDelay=1
|
||||
renameToFetchDelay=1
|
||||
renameToIEWDelay=2
|
||||
renameToROBDelay=1
|
||||
renameWidth=8
|
||||
squashWidth=8
|
||||
phase=0
|
||||
progress_interval=0
|
||||
simulate_stalls=false
|
||||
system=system
|
||||
trapLatency=13
|
||||
wbDepth=1
|
||||
wbWidth=8
|
||||
width=1
|
||||
workload=system.cpu.workload
|
||||
dcache_port=system.cpu.dcache.cpu_side
|
||||
icache_port=system.cpu.icache.cpu_side
|
||||
|
||||
[system.cpu.dcache]
|
||||
type=BaseCache
|
||||
adaptive_compression=false
|
||||
assoc=2
|
||||
block_size=64
|
||||
compressed_bus=false
|
||||
compression_latency=0
|
||||
do_copy=false
|
||||
hash_delay=1
|
||||
hit_latency=1
|
||||
latency=1
|
||||
lifo=false
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
prefetch_access=false
|
||||
prefetch_cache_check_push=true
|
||||
prefetch_data_accesses_only=false
|
||||
prefetch_degree=1
|
||||
prefetch_latency=10
|
||||
prefetch_miss=false
|
||||
prefetch_past_page=false
|
||||
prefetch_policy=none
|
||||
prefetch_serial_squash=false
|
||||
prefetch_use_cpu_id=true
|
||||
prefetcher_size=100
|
||||
prioritizeRequests=false
|
||||
protocol=Null
|
||||
repl=Null
|
||||
size=262144
|
||||
split=false
|
||||
split_size=0
|
||||
store_compressed=false
|
||||
subblock_size=0
|
||||
tgts_per_mshr=5
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu.dcache_port
|
||||
mem_side=system.cpu.toL2Bus.port[1]
|
||||
|
||||
[system.cpu.fuPool]
|
||||
type=FUPool
|
||||
children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7
|
||||
FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7
|
||||
|
||||
[system.cpu.fuPool.FUList0]
|
||||
type=FUDesc
|
||||
children=opList0
|
||||
count=6
|
||||
opList=system.cpu.fuPool.FUList0.opList0
|
||||
|
||||
[system.cpu.fuPool.FUList0.opList0]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=IntAlu
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList1]
|
||||
type=FUDesc
|
||||
children=opList0 opList1
|
||||
count=2
|
||||
opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
|
||||
|
||||
[system.cpu.fuPool.FUList1.opList0]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=IntMult
|
||||
opLat=3
|
||||
|
||||
[system.cpu.fuPool.FUList1.opList1]
|
||||
type=OpDesc
|
||||
issueLat=19
|
||||
opClass=IntDiv
|
||||
opLat=20
|
||||
|
||||
[system.cpu.fuPool.FUList2]
|
||||
type=FUDesc
|
||||
children=opList0 opList1 opList2
|
||||
count=4
|
||||
opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
|
||||
|
||||
[system.cpu.fuPool.FUList2.opList0]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=FloatAdd
|
||||
opLat=2
|
||||
|
||||
[system.cpu.fuPool.FUList2.opList1]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=FloatCmp
|
||||
opLat=2
|
||||
|
||||
[system.cpu.fuPool.FUList2.opList2]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=FloatCvt
|
||||
opLat=2
|
||||
|
||||
[system.cpu.fuPool.FUList3]
|
||||
type=FUDesc
|
||||
children=opList0 opList1 opList2
|
||||
count=2
|
||||
opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
|
||||
|
||||
[system.cpu.fuPool.FUList3.opList0]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=FloatMult
|
||||
opLat=4
|
||||
|
||||
[system.cpu.fuPool.FUList3.opList1]
|
||||
type=OpDesc
|
||||
issueLat=12
|
||||
opClass=FloatDiv
|
||||
opLat=12
|
||||
|
||||
[system.cpu.fuPool.FUList3.opList2]
|
||||
type=OpDesc
|
||||
issueLat=24
|
||||
opClass=FloatSqrt
|
||||
opLat=24
|
||||
|
||||
[system.cpu.fuPool.FUList4]
|
||||
type=FUDesc
|
||||
children=opList0
|
||||
count=0
|
||||
opList=system.cpu.fuPool.FUList4.opList0
|
||||
|
||||
[system.cpu.fuPool.FUList4.opList0]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=MemRead
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5]
|
||||
type=FUDesc
|
||||
children=opList0
|
||||
count=0
|
||||
opList=system.cpu.fuPool.FUList5.opList0
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList0]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=MemWrite
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList6]
|
||||
type=FUDesc
|
||||
children=opList0 opList1
|
||||
count=4
|
||||
opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1
|
||||
|
||||
[system.cpu.fuPool.FUList6.opList0]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=MemRead
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList6.opList1]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=MemWrite
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList7]
|
||||
type=FUDesc
|
||||
children=opList0
|
||||
count=1
|
||||
opList=system.cpu.fuPool.FUList7.opList0
|
||||
|
||||
[system.cpu.fuPool.FUList7.opList0]
|
||||
type=OpDesc
|
||||
issueLat=3
|
||||
opClass=IprAccess
|
||||
opLat=3
|
||||
|
||||
[system.cpu.icache]
|
||||
type=BaseCache
|
||||
adaptive_compression=false
|
||||
assoc=2
|
||||
block_size=64
|
||||
compressed_bus=false
|
||||
compression_latency=0
|
||||
do_copy=false
|
||||
hash_delay=1
|
||||
hit_latency=1
|
||||
latency=1
|
||||
lifo=false
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
prefetch_access=false
|
||||
prefetch_cache_check_push=true
|
||||
prefetch_data_accesses_only=false
|
||||
prefetch_degree=1
|
||||
prefetch_latency=10
|
||||
prefetch_miss=false
|
||||
prefetch_past_page=false
|
||||
prefetch_policy=none
|
||||
prefetch_serial_squash=false
|
||||
prefetch_use_cpu_id=true
|
||||
prefetcher_size=100
|
||||
prioritizeRequests=false
|
||||
protocol=Null
|
||||
repl=Null
|
||||
size=131072
|
||||
split=false
|
||||
split_size=0
|
||||
store_compressed=false
|
||||
subblock_size=0
|
||||
tgts_per_mshr=5
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu.icache_port
|
||||
mem_side=system.cpu.toL2Bus.port[0]
|
||||
|
||||
[system.cpu.l2cache]
|
||||
type=BaseCache
|
||||
adaptive_compression=false
|
||||
assoc=2
|
||||
block_size=64
|
||||
compressed_bus=false
|
||||
compression_latency=0
|
||||
do_copy=false
|
||||
hash_delay=1
|
||||
hit_latency=1
|
||||
latency=1
|
||||
lifo=false
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
prefetch_access=false
|
||||
prefetch_cache_check_push=true
|
||||
prefetch_data_accesses_only=false
|
||||
prefetch_degree=1
|
||||
prefetch_latency=10
|
||||
prefetch_miss=false
|
||||
prefetch_past_page=false
|
||||
prefetch_policy=none
|
||||
prefetch_serial_squash=false
|
||||
prefetch_use_cpu_id=true
|
||||
prefetcher_size=100
|
||||
prioritizeRequests=false
|
||||
protocol=Null
|
||||
repl=Null
|
||||
size=2097152
|
||||
split=false
|
||||
split_size=0
|
||||
store_compressed=false
|
||||
subblock_size=0
|
||||
tgts_per_mshr=5
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu.toL2Bus.port[2]
|
||||
mem_side=system.membus.port[1]
|
||||
|
||||
[system.cpu.toL2Bus]
|
||||
type=Bus
|
||||
bus_id=0
|
||||
port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
|
||||
dcache_port=system.membus.port[2]
|
||||
icache_port=system.membus.port[1]
|
||||
|
||||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
cmd=hello
|
||||
cmd=vortex lendian.raw
|
||||
cwd=build/ALPHA_SE/tests/opt/long/50.vortex/alpha/linux/simple-atomic
|
||||
egid=100
|
||||
env=
|
||||
executable=tests/test-progs/hello/bin/alpha/linux/hello
|
||||
euid=100
|
||||
executable=/dist/m5/cpu2000/binaries/alpha/tru64/vortex
|
||||
gid=100
|
||||
input=cin
|
||||
output=cout
|
||||
pid=100
|
||||
ppid=99
|
||||
system=system
|
||||
uid=100
|
||||
|
||||
[system.membus]
|
||||
type=Bus
|
||||
bus_id=0
|
||||
port=system.physmem.port system.cpu.l2cache.mem_side
|
||||
clock=1000
|
||||
responder_set=false
|
||||
width=64
|
||||
port=system.physmem.port system.cpu.icache_port system.cpu.dcache_port
|
||||
|
||||
[system.physmem]
|
||||
type=PhysicalMemory
|
||||
|
|
@ -409,6 +104,7 @@ port=system.membus.port[0]
|
|||
|
||||
[trace]
|
||||
bufsize=0
|
||||
cycle=0
|
||||
dump_on_exit=false
|
||||
file=cout
|
||||
flags=
|
||||
|
|
|
|||
|
|
@ -19,345 +19,48 @@ mem_mode=atomic
|
|||
[system.membus]
|
||||
type=Bus
|
||||
bus_id=0
|
||||
clock=1000
|
||||
width=64
|
||||
responder_set=false
|
||||
|
||||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
cmd=hello
|
||||
executable=tests/test-progs/hello/bin/alpha/linux/hello
|
||||
cmd=vortex lendian.raw
|
||||
executable=/dist/m5/cpu2000/binaries/alpha/tru64/vortex
|
||||
input=cin
|
||||
output=cout
|
||||
env=
|
||||
cwd=build/ALPHA_SE/tests/opt/long/50.vortex/alpha/linux/simple-atomic
|
||||
system=system
|
||||
|
||||
[system.cpu.dcache]
|
||||
type=BaseCache
|
||||
size=262144
|
||||
assoc=2
|
||||
block_size=64
|
||||
latency=1
|
||||
mshrs=10
|
||||
tgts_per_mshr=5
|
||||
write_buffers=8
|
||||
prioritizeRequests=false
|
||||
do_copy=false
|
||||
protocol=null
|
||||
trace_addr=0
|
||||
hash_delay=1
|
||||
repl=null
|
||||
compressed_bus=false
|
||||
store_compressed=false
|
||||
adaptive_compression=false
|
||||
compression_latency=0
|
||||
block_size=64
|
||||
max_miss_count=0
|
||||
addr_range=[0,18446744073709551615]
|
||||
split=false
|
||||
split_size=0
|
||||
lifo=false
|
||||
two_queue=false
|
||||
prefetch_miss=false
|
||||
prefetch_access=false
|
||||
prefetcher_size=100
|
||||
prefetch_past_page=false
|
||||
prefetch_serial_squash=false
|
||||
prefetch_latency=10
|
||||
prefetch_degree=1
|
||||
prefetch_policy=none
|
||||
prefetch_cache_check_push=true
|
||||
prefetch_use_cpu_id=true
|
||||
prefetch_data_accesses_only=false
|
||||
hit_latency=1
|
||||
|
||||
[system.cpu.fuPool.FUList0.opList0]
|
||||
type=OpDesc
|
||||
opClass=IntAlu
|
||||
opLat=1
|
||||
issueLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList0]
|
||||
type=FUDesc
|
||||
opList=system.cpu.fuPool.FUList0.opList0
|
||||
count=6
|
||||
|
||||
[system.cpu.fuPool.FUList1.opList0]
|
||||
type=OpDesc
|
||||
opClass=IntMult
|
||||
opLat=3
|
||||
issueLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList1.opList1]
|
||||
type=OpDesc
|
||||
opClass=IntDiv
|
||||
opLat=20
|
||||
issueLat=19
|
||||
|
||||
[system.cpu.fuPool.FUList1]
|
||||
type=FUDesc
|
||||
opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
|
||||
count=2
|
||||
|
||||
[system.cpu.fuPool.FUList2.opList0]
|
||||
type=OpDesc
|
||||
opClass=FloatAdd
|
||||
opLat=2
|
||||
issueLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList2.opList1]
|
||||
type=OpDesc
|
||||
opClass=FloatCmp
|
||||
opLat=2
|
||||
issueLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList2.opList2]
|
||||
type=OpDesc
|
||||
opClass=FloatCvt
|
||||
opLat=2
|
||||
issueLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList2]
|
||||
type=FUDesc
|
||||
opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
|
||||
count=4
|
||||
|
||||
[system.cpu.fuPool.FUList3.opList0]
|
||||
type=OpDesc
|
||||
opClass=FloatMult
|
||||
opLat=4
|
||||
issueLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList3.opList1]
|
||||
type=OpDesc
|
||||
opClass=FloatDiv
|
||||
opLat=12
|
||||
issueLat=12
|
||||
|
||||
[system.cpu.fuPool.FUList3.opList2]
|
||||
type=OpDesc
|
||||
opClass=FloatSqrt
|
||||
opLat=24
|
||||
issueLat=24
|
||||
|
||||
[system.cpu.fuPool.FUList3]
|
||||
type=FUDesc
|
||||
opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
|
||||
count=2
|
||||
|
||||
[system.cpu.fuPool.FUList4.opList0]
|
||||
type=OpDesc
|
||||
opClass=MemRead
|
||||
opLat=1
|
||||
issueLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList4]
|
||||
type=FUDesc
|
||||
opList=system.cpu.fuPool.FUList4.opList0
|
||||
count=0
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList0]
|
||||
type=OpDesc
|
||||
opClass=MemWrite
|
||||
opLat=1
|
||||
issueLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5]
|
||||
type=FUDesc
|
||||
opList=system.cpu.fuPool.FUList5.opList0
|
||||
count=0
|
||||
|
||||
[system.cpu.fuPool.FUList6.opList0]
|
||||
type=OpDesc
|
||||
opClass=MemRead
|
||||
opLat=1
|
||||
issueLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList6.opList1]
|
||||
type=OpDesc
|
||||
opClass=MemWrite
|
||||
opLat=1
|
||||
issueLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList6]
|
||||
type=FUDesc
|
||||
opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1
|
||||
count=4
|
||||
|
||||
[system.cpu.fuPool.FUList7.opList0]
|
||||
type=OpDesc
|
||||
opClass=IprAccess
|
||||
opLat=3
|
||||
issueLat=3
|
||||
|
||||
[system.cpu.fuPool.FUList7]
|
||||
type=FUDesc
|
||||
opList=system.cpu.fuPool.FUList7.opList0
|
||||
count=1
|
||||
|
||||
[system.cpu.fuPool]
|
||||
type=FUPool
|
||||
FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7
|
||||
uid=100
|
||||
euid=100
|
||||
gid=100
|
||||
egid=100
|
||||
pid=100
|
||||
ppid=99
|
||||
|
||||
[system.cpu]
|
||||
type=DerivO3CPU
|
||||
clock=1
|
||||
numThreads=1
|
||||
activity=0
|
||||
workload=system.cpu.workload
|
||||
mem=system.cpu.dcache
|
||||
checker=null
|
||||
type=AtomicSimpleCPU
|
||||
max_insts_any_thread=0
|
||||
max_insts_all_threads=0
|
||||
max_loads_any_thread=0
|
||||
max_loads_all_threads=0
|
||||
cachePorts=200
|
||||
decodeToFetchDelay=1
|
||||
renameToFetchDelay=1
|
||||
iewToFetchDelay=1
|
||||
commitToFetchDelay=1
|
||||
fetchWidth=8
|
||||
renameToDecodeDelay=1
|
||||
iewToDecodeDelay=1
|
||||
commitToDecodeDelay=1
|
||||
fetchToDecodeDelay=1
|
||||
decodeWidth=8
|
||||
iewToRenameDelay=1
|
||||
commitToRenameDelay=1
|
||||
decodeToRenameDelay=1
|
||||
renameWidth=8
|
||||
commitToIEWDelay=1
|
||||
renameToIEWDelay=2
|
||||
issueToExecuteDelay=1
|
||||
dispatchWidth=8
|
||||
issueWidth=8
|
||||
wbWidth=8
|
||||
wbDepth=1
|
||||
fuPool=system.cpu.fuPool
|
||||
iewToCommitDelay=1
|
||||
renameToROBDelay=1
|
||||
commitWidth=8
|
||||
squashWidth=8
|
||||
trapLatency=13
|
||||
backComSize=5
|
||||
forwardComSize=5
|
||||
predType=tournament
|
||||
localPredictorSize=2048
|
||||
localCtrBits=2
|
||||
localHistoryTableSize=2048
|
||||
localHistoryBits=11
|
||||
globalPredictorSize=8192
|
||||
globalCtrBits=2
|
||||
globalHistoryBits=13
|
||||
choicePredictorSize=8192
|
||||
choiceCtrBits=2
|
||||
BTBEntries=4096
|
||||
BTBTagSize=16
|
||||
RASSize=16
|
||||
LQEntries=32
|
||||
SQEntries=32
|
||||
LFSTSize=1024
|
||||
SSITSize=1024
|
||||
numPhysIntRegs=256
|
||||
numPhysFloatRegs=256
|
||||
numIQEntries=64
|
||||
numROBEntries=192
|
||||
smtNumFetchingThreads=1
|
||||
smtFetchPolicy=SingleThread
|
||||
smtLSQPolicy=Partitioned
|
||||
smtLSQThreshold=100
|
||||
smtIQPolicy=Partitioned
|
||||
smtIQThreshold=100
|
||||
smtROBPolicy=Partitioned
|
||||
smtROBThreshold=100
|
||||
smtCommitPolicy=RoundRobin
|
||||
instShiftAmt=2
|
||||
progress_interval=0
|
||||
system=system
|
||||
cpu_id=0
|
||||
workload=system.cpu.workload
|
||||
clock=1
|
||||
phase=0
|
||||
defer_registration=false
|
||||
width=1
|
||||
function_trace=false
|
||||
function_trace_start=0
|
||||
|
||||
[system.cpu.icache]
|
||||
type=BaseCache
|
||||
size=131072
|
||||
assoc=2
|
||||
block_size=64
|
||||
latency=1
|
||||
mshrs=10
|
||||
tgts_per_mshr=5
|
||||
write_buffers=8
|
||||
prioritizeRequests=false
|
||||
do_copy=false
|
||||
protocol=null
|
||||
trace_addr=0
|
||||
hash_delay=1
|
||||
repl=null
|
||||
compressed_bus=false
|
||||
store_compressed=false
|
||||
adaptive_compression=false
|
||||
compression_latency=0
|
||||
block_size=64
|
||||
max_miss_count=0
|
||||
addr_range=[0,18446744073709551615]
|
||||
split=false
|
||||
split_size=0
|
||||
lifo=false
|
||||
two_queue=false
|
||||
prefetch_miss=false
|
||||
prefetch_access=false
|
||||
prefetcher_size=100
|
||||
prefetch_past_page=false
|
||||
prefetch_serial_squash=false
|
||||
prefetch_latency=10
|
||||
prefetch_degree=1
|
||||
prefetch_policy=none
|
||||
prefetch_cache_check_push=true
|
||||
prefetch_use_cpu_id=true
|
||||
prefetch_data_accesses_only=false
|
||||
hit_latency=1
|
||||
|
||||
[system.cpu.l2cache]
|
||||
type=BaseCache
|
||||
size=2097152
|
||||
assoc=2
|
||||
block_size=64
|
||||
latency=1
|
||||
mshrs=10
|
||||
tgts_per_mshr=5
|
||||
write_buffers=8
|
||||
prioritizeRequests=false
|
||||
do_copy=false
|
||||
protocol=null
|
||||
trace_addr=0
|
||||
hash_delay=1
|
||||
repl=null
|
||||
compressed_bus=false
|
||||
store_compressed=false
|
||||
adaptive_compression=false
|
||||
compression_latency=0
|
||||
block_size=64
|
||||
max_miss_count=0
|
||||
addr_range=[0,18446744073709551615]
|
||||
split=false
|
||||
split_size=0
|
||||
lifo=false
|
||||
two_queue=false
|
||||
prefetch_miss=false
|
||||
prefetch_access=false
|
||||
prefetcher_size=100
|
||||
prefetch_past_page=false
|
||||
prefetch_serial_squash=false
|
||||
prefetch_latency=10
|
||||
prefetch_degree=1
|
||||
prefetch_policy=none
|
||||
prefetch_cache_check_push=true
|
||||
prefetch_use_cpu_id=true
|
||||
prefetch_data_accesses_only=false
|
||||
hit_latency=1
|
||||
|
||||
[system.cpu.toL2Bus]
|
||||
type=Bus
|
||||
bus_id=0
|
||||
simulate_stalls=false
|
||||
|
||||
[trace]
|
||||
flags=
|
||||
start=0
|
||||
cycle=0
|
||||
bufsize=0
|
||||
file=cout
|
||||
dump_on_exit=false
|
||||
|
|
@ -396,8 +99,9 @@ print_cpseq=false
|
|||
print_reg_delta=false
|
||||
pc_symbol=true
|
||||
intel_format=false
|
||||
legion_lockstep=false
|
||||
trace_system=client
|
||||
|
||||
[debug]
|
||||
break_cycles=
|
||||
[statsreset]
|
||||
reset_cycle=0
|
||||
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
158
tests/long/50.vortex/ref/alpha/linux/simple-atomic/smred.msg
Normal file
158
tests/long/50.vortex/ref/alpha/linux/simple-atomic/smred.msg
Normal file
|
|
@ -0,0 +1,158 @@
|
|||
|
||||
SYSTEM TYPE...
|
||||
__ZTC__ := False
|
||||
__UNIX__ := True
|
||||
__RISC__ := True
|
||||
SPEC_CPU2000_LP64 := True
|
||||
__MAC__ := False
|
||||
__BCC__ := False
|
||||
__BORLANDC__ := False
|
||||
__GUI__ := False
|
||||
__WTC__ := False
|
||||
__HP__ := False
|
||||
|
||||
CODE OPTIONS...
|
||||
__MACROIZE_HM__ := True
|
||||
__MACROIZE_MEM__ := True
|
||||
ENV01 := True
|
||||
USE_HPP_STYPE_HDRS := False
|
||||
USE_H_STYPE_HDRS := False
|
||||
|
||||
CODE INCLUSION PARAMETERS...
|
||||
INCLUDE_ALL_CODE := False
|
||||
INCLUDE_DELETE_CODE := True
|
||||
__SWAP_GRP_POS__ := True
|
||||
__INCLUDE_MTRX__ := False
|
||||
__BAD_CODE__ := False
|
||||
API_INCLUDE := False
|
||||
BE_CAREFUL := False
|
||||
OLDWAY := False
|
||||
NOTUSED := False
|
||||
|
||||
SYSTEM PARAMETERS...
|
||||
EXT_ENUM := 999999999L
|
||||
CHUNK_CONSTANT := 55555555
|
||||
CORE_CONSTANT := 55555555
|
||||
CORE_LIMIT := 20971520
|
||||
CorePage_Size := 384000
|
||||
ALIGN_BYTES := True
|
||||
CORE_BLOCK_ALIGN := 8
|
||||
FAR_MEM := False
|
||||
|
||||
MEMORY MANAGEMENT PARAMETERS...
|
||||
SYSTEM_ALLOC := True
|
||||
SYSTEM_FREESTORE := True
|
||||
__NO_DISKCACHE__ := False
|
||||
__FREEZE_VCHUNKS__ := True
|
||||
__FREEZE_GRP_PACKETS__ := True
|
||||
__MINIMIZE_TREE_CACHE__:= True
|
||||
|
||||
SYSTEM STD PARAMETERS...
|
||||
__STDOUT__ := False
|
||||
NULL := 0
|
||||
LPTR := False
|
||||
False_Status := 1
|
||||
True_Status := 0
|
||||
LARGE := True
|
||||
TWOBYTE_BOOL := False
|
||||
__NOSTR__ := False
|
||||
|
||||
MEMORY VALIDATION PARAMETERS...
|
||||
CORE_CRC_CHECK := False
|
||||
VALIDATE_MEM_CHUNKS := False
|
||||
|
||||
SYSTEM DEBUG OPTIONS...
|
||||
DEBUG := False
|
||||
MCSTAT := False
|
||||
TRACKBACK := False
|
||||
FLUSH_FILES := False
|
||||
DEBUG_CORE0 := False
|
||||
DEBUG_RISC := False
|
||||
__TREE_BUG__ := False
|
||||
__TRACK_FILE_READS__ := False
|
||||
PAGE_SPACE := False
|
||||
LEAVE_NO_TRACE := True
|
||||
NULL_TRACE_STRS := False
|
||||
|
||||
TIME PARAMETERS...
|
||||
CLOCK_IS_LONG := False
|
||||
__DISPLAY_TIME__ := False
|
||||
__TREE_TIME__ := False
|
||||
__DISPLAY_ERRORS__ := False
|
||||
|
||||
API MACROS...
|
||||
__BMT01__ := True
|
||||
OPTIMIZE := True
|
||||
|
||||
END OF DEFINES.
|
||||
|
||||
|
||||
|
||||
... IMPLODE MEMORY ...
|
||||
|
||||
SWAP to DiskCache := False
|
||||
|
||||
FREEZE_GRP_PACKETS:= True
|
||||
|
||||
QueBug := 1000
|
||||
|
||||
sizeof(boolean) = 4
|
||||
sizeof(sizetype) = 4
|
||||
sizeof(chunkstruc) = 32
|
||||
|
||||
sizeof(shorttype ) = 2
|
||||
sizeof(idtype ) = 2
|
||||
sizeof(sizetype ) = 4
|
||||
sizeof(indextype ) = 4
|
||||
sizeof(numtype ) = 4
|
||||
sizeof(handletype) = 4
|
||||
sizeof(tokentype ) = 8
|
||||
|
||||
sizeof(short ) = 2
|
||||
sizeof(int ) = 4
|
||||
|
||||
sizeof(lt64 ) = 4
|
||||
sizeof(farlongtype) = 4
|
||||
sizeof(long ) = 8
|
||||
sizeof(longaddr ) = 8
|
||||
|
||||
sizeof(float ) = 4
|
||||
sizeof(double ) = 8
|
||||
|
||||
sizeof(addrtype ) = 8
|
||||
sizeof(char * ) = 8
|
||||
ALLOC CORE_1 :: 16
|
||||
BHOOLE NATH
|
||||
|
||||
OPEN File ./input/lendian.rnv
|
||||
*Status = 0
|
||||
DB HDR restored from FileVbn[ 0]
|
||||
DB BlkDirOffset : @ 2030c0
|
||||
DB BlkDirChunk : Chunk[ 10] AT Vbn[3146]
|
||||
DB BlkTknChunk : Chunk[ 11] AT Vbn[3147]
|
||||
DB BlkSizeChunk : Chunk[ 12] AT Vbn[3148]
|
||||
DB Handle Chunk's StackPtr = 20797
|
||||
|
||||
DB[ 1] LOADED; Handles= 20797
|
||||
KERNEL in CORE[ 1] Restored @ 40054800
|
||||
|
||||
OPEN File ./input/lendian.wnv
|
||||
*Status = 0
|
||||
DB HDR restored from FileVbn[ 0]
|
||||
DB BlkDirOffset : @ 21c40
|
||||
DB BlkDirChunk : Chunk[ 31] AT Vbn[ 81]
|
||||
DB BlkTknChunk : Chunk[ 32] AT Vbn[ 82]
|
||||
DB BlkSizeChunk : Chunk[ 33] AT Vbn[ 83]
|
||||
DB Handle Chunk's StackPtr = 17
|
||||
|
||||
DB[ 2] LOADED; Handles= 17
|
||||
VORTEx_Status == -8 || fffffff8
|
||||
|
||||
BE HERE NOW !!!
|
||||
|
||||
|
||||
|
||||
... VORTEx ON LINE ...
|
||||
|
||||
|
||||
... END OF SESSION ...
|
||||
258
tests/long/50.vortex/ref/alpha/linux/simple-atomic/smred.out
Normal file
258
tests/long/50.vortex/ref/alpha/linux/simple-atomic/smred.out
Normal file
|
|
@ -0,0 +1,258 @@
|
|||
CREATE Db Header and Db Primal ...
|
||||
NEW DB [ 3] Created.
|
||||
|
||||
VORTEX INPUT PARAMETERS::
|
||||
MESSAGE FileName: smred.msg
|
||||
OUTPUT FileName: smred.out
|
||||
DISK CACHE FileName: NULL
|
||||
PART DB FileName: parts.db
|
||||
DRAW DB FileName: draw.db
|
||||
PERSON DB FileName: emp.db
|
||||
PERSONS Data FileName: ./input/persons.250
|
||||
PARTS Count : 100
|
||||
OUTER Loops : 1
|
||||
INNER Loops : 1
|
||||
LOOKUP Parts : 25
|
||||
DELETE Parts : 10
|
||||
STUFF Parts : 10
|
||||
DEPTH Traverse: 5
|
||||
% DECREASE Parts : 0
|
||||
% INCREASE LookUps : 0
|
||||
% INCREASE Deletes : 0
|
||||
% INCREASE Stuffs : 0
|
||||
FREEZE_PACKETS : 1
|
||||
ALLOC_CHUNKS : 10000
|
||||
EXTEND_CHUNKS : 5000
|
||||
DELETE Draw objects : True
|
||||
DELETE Part objects : False
|
||||
QUE_BUG : 1000
|
||||
VOID_BOUNDARY : 67108864
|
||||
VOID_RESERVE : 1048576
|
||||
|
||||
COMMIT_DBS : False
|
||||
|
||||
|
||||
|
||||
BMT TEST :: files...
|
||||
EdbName := PartLib
|
||||
EdbFileName := parts.db
|
||||
DrwName := DrawLib
|
||||
DrwFileName := draw.db
|
||||
EmpName := PersonLib
|
||||
EmpFileName := emp.db
|
||||
|
||||
Swap to DiskCache := False
|
||||
Freeze the cache := True
|
||||
|
||||
|
||||
BMT TEST :: parms...
|
||||
DeBug modulo := 1000
|
||||
Create Parts count:= 100
|
||||
Outer Loops := 1
|
||||
Inner Loops := 1
|
||||
Look Ups := 25
|
||||
Delete Parts := 10
|
||||
Stuff Parts := 10
|
||||
Traverse Limit := 5
|
||||
Delete Draws := True
|
||||
Delete Parts := False
|
||||
Delete ALL Parts := after every <mod 0>Outer Loop
|
||||
|
||||
INITIALIZE LIBRARY ::
|
||||
|
||||
INITIALIZE SCHEMA ::
|
||||
Primal_CreateDb Accessed !!!
|
||||
CREATE Db Header and Db Primal ...
|
||||
NEW DB [ 4] Created.
|
||||
PartLibCreate:: Db[ 4]; VpartsDir= 1
|
||||
|
||||
Part Count= 1
|
||||
|
||||
Initialize the Class maps
|
||||
LIST HEADS loaded ... DbListHead_Class = 207
|
||||
DbListNode_Class = 206
|
||||
|
||||
...NOTE... ShellLoadCode:: Class[ 228] will NOT be Activated.
|
||||
|
||||
|
||||
...NOTE... ShellLoadCode:: Class[ 229] will NOT be Activated.
|
||||
|
||||
Primal_CreateDb Accessed !!!
|
||||
CREATE Db Header and Db Primal ...
|
||||
NEW DB [ 5] Created.
|
||||
DrawLibCreate:: Db[ 5]; VpartsDir= 1
|
||||
|
||||
Initialize the Class maps of this schema.
|
||||
Primal_CreateDb Accessed !!!
|
||||
CREATE Db Header and Db Primal ...
|
||||
NEW DB [ 6] Created.
|
||||
|
||||
***NOTE*** Persons Library Extended!
|
||||
|
||||
Create <131072> Persons.
|
||||
ItNum 0. Person[ 6: 5]. Name= Riddell , Robert V. ;
|
||||
|
||||
LAST Person Read::
|
||||
ItNum 250. Person[ 6: 503]. Name= Gonzales , Warren X. ;
|
||||
|
||||
BUILD <Query0> for <Part2> class::
|
||||
|
||||
if (link[1].length >= 5) ::
|
||||
|
||||
Build Query2 for <Address> class::
|
||||
|
||||
if (State == CA || State == T*)
|
||||
|
||||
Build Query1 for <Person> class::
|
||||
|
||||
if (LastName >= H* && LastName <= P* && Query0(Residence)) ::
|
||||
|
||||
BUILD <Query3> for <DrawObj> class::
|
||||
|
||||
if (Id >= 3000
|
||||
&& (Id >= 3000 && Id <= 3001)
|
||||
&& Id >= 3002)
|
||||
|
||||
BUILD <Query4> for <NamedDrawObj> class::
|
||||
|
||||
if (Nam == Pre*
|
||||
|| (Nam == ??Mid??? || == Pre??Mid?? || == ??Post
|
||||
|| == Pre??Post || == ??Mid???Post || == Pre??Mid???Post)
|
||||
&& Id <= 7)
|
||||
SEED := 1008; Swap = False; RgnEntries = 135
|
||||
|
||||
OUTER LOOP [ 1] : NewParts = 100 LookUps = 25 StuffParts = 10.
|
||||
|
||||
Create 100 New Parts
|
||||
Create Part 1. Token[ 4: 2].
|
||||
|
||||
< 100> Parts Created. CurrentId= 100
|
||||
|
||||
Connect each instantiated Part TO 3 unique Parts
|
||||
Connect Part 1. Token[ 4: 2]
|
||||
Connect Part 25. Token[ 4: 26] FromList= 26.
|
||||
Connect Part 12. Token[ 4: 13] FromList= 13.
|
||||
Connect Part 59. Token[ 4: 60] FromList= 60.
|
||||
|
||||
SET <DrawObjs> entries::
|
||||
1. [ 5: 5] := <1 >; @[: 6]
|
||||
Iteration count = 100
|
||||
|
||||
SET <NamedDrawObjs> entries::
|
||||
1. [ 5: 39] := <14 >;
|
||||
Iteration count = 12
|
||||
|
||||
SET <LibRectangles> entries::
|
||||
1. [ 5: 23] := <8 >; @[: 24]
|
||||
Iteration count = 12
|
||||
|
||||
LIST <DbRectangles> entries::
|
||||
1. [ 5: 23]
|
||||
Iteration count = 12
|
||||
|
||||
SET <PersonNames > entries::
|
||||
Iteration count = 250
|
||||
|
||||
COMMIT All Image copies:: Release=<True>; Max Parts= 100
|
||||
< 100> Part images' Committed.
|
||||
< 0> are Named.
|
||||
< 50> Point images' Committed.
|
||||
< 81> Person images' Committed.
|
||||
|
||||
COMMIT Parts(* 100)
|
||||
|
||||
Commit TestObj_Class in <Primal> DB.
|
||||
ItNum 0. Token[ 0: 0]. TestObj Committed.
|
||||
< 0> TestObj images' Committed.
|
||||
|
||||
Commit CartesianPoint_Class in <Primal> DB.
|
||||
ItNum 0. Token[ 0: 0]. CartesianPoint Committed.
|
||||
< 0> CartesianPoint images' Committed.
|
||||
|
||||
BEGIN Inner Loop Sequence::.
|
||||
|
||||
INNER LOOP [ 1: 1] :
|
||||
|
||||
LOOK UP 25 Random Parts and Export each Part.
|
||||
|
||||
LookUp for 26 parts; Asserts = 8
|
||||
<Part2 > Asserts = 2; NULL Asserts = 3.
|
||||
<DrawObj > Asserts = 0; NULL Asserts = 5.
|
||||
<NamedObj > Asserts = 0; NULL Asserts = 0.
|
||||
<Person > Asserts = 0; NULL Asserts = 5.
|
||||
<TestObj > Asserts = 60; NULL Asserts = 0.
|
||||
|
||||
DELETE 10 Random Parts.
|
||||
|
||||
PartDelete :: Token[ 4: 91].
|
||||
PartDisconnect:: Token[ 4: 91] id:= 90 for each link.
|
||||
DisConnect link [ 0]:= 50; PartToken[ 51: 51].
|
||||
DisConnect link [ 1]:= 17; PartToken[ 18: 18].
|
||||
DisConnect link [ 2]:= 72; PartToken[ 73: 73].
|
||||
DeleteFromList:: Vchunk[ 4: 91]. (* 1)
|
||||
DisConnect FromList[ 0]:= 56; Token[ 57: 57].
|
||||
Vlists[ 89] := 100;
|
||||
|
||||
Delete for 11 parts;
|
||||
|
||||
Traverse Count= 0
|
||||
|
||||
TRAVERSE PartId[ 6] and all Connections to 5 Levels
|
||||
SEED In Traverse Part [ 4: 65] @ Level = 4.
|
||||
|
||||
Traverse Count= 357
|
||||
Traverse Asserts = 5. True Tests = 1
|
||||
< 5> DrawObj objects DELETED.
|
||||
< 2> are Named.
|
||||
< 2> Point objects DELETED.
|
||||
|
||||
CREATE 10 Additional Parts
|
||||
|
||||
Create 10 New Parts
|
||||
Create Part 101. Token[ 4: 102].
|
||||
|
||||
< 10> Parts Created. CurrentId= 110
|
||||
|
||||
Connect each instantiated Part TO 3 unique Parts
|
||||
|
||||
COMMIT All Image copies:: Release=<True>; Max Parts= 110
|
||||
< 81> Part images' Committed.
|
||||
< 0> are Named.
|
||||
< 38> Point images' Committed.
|
||||
< 31> Person images' Committed.
|
||||
|
||||
COMMIT Parts(* 100)
|
||||
|
||||
Commit TestObj_Class in <Primal> DB.
|
||||
ItNum 0. Token[ 3: 4]. TestObj Committed.
|
||||
< 15> TestObj images' Committed.
|
||||
|
||||
Commit CartesianPoint_Class in <Primal> DB.
|
||||
ItNum 0. Token[ 3: 3]. CartesianPoint Committed.
|
||||
< 16> CartesianPoint images' Committed.
|
||||
|
||||
DELETE All TestObj objects;
|
||||
|
||||
Delete TestObj_Class in <Primal> DB.
|
||||
ItNum 0. Token[ 3: 4]. TestObj Deleted.
|
||||
< 15> TestObj objects Deleted.
|
||||
|
||||
Commit CartesianPoint_Class in <Primal> DB.
|
||||
ItNum 0. Token[ 3: 3]. CartesianPoint Deleted.
|
||||
< 16> CartesianPoint objects Deleted.
|
||||
|
||||
DELETE TestObj and Point objects...
|
||||
|
||||
END INNER LOOP [ 1: 1].
|
||||
|
||||
DELETE All TestObj objects;
|
||||
|
||||
Delete TestObj_Class in <Primal> DB.
|
||||
< 0> TestObj objects Deleted.
|
||||
|
||||
Commit CartesianPoint_Class in <Primal> DB.
|
||||
< 0> CartesianPoint objects Deleted.
|
||||
|
||||
DELETE TestObj and Point objects...
|
||||
STATUS= -201
|
||||
V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1!
|
||||
|
|
@ -1,3 +1 @@
|
|||
warn: Entering event queue @ 0. Starting simulation...
|
||||
warn: cycle 0: fault (page_table_fault) detected @ PC 0x000000
|
||||
warn: Increasing stack 0x11ff92000:0x11ff9b000 to 0x11ff90000:0x11ff9b000 because of access to 0x11ff91ff0
|
||||
|
|
|
|||
|
|
@ -1,13 +0,0 @@
|
|||
Hello world!
|
||||
M5 Simulator System
|
||||
|
||||
Copyright (c) 2001-2006
|
||||
The Regents of The University of Michigan
|
||||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Sep 5 2006 15:28:48
|
||||
M5 started Tue Sep 5 15:42:12 2006
|
||||
M5 executing on zizzer.eecs.umich.edu
|
||||
command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/o3-timing tests/run.py quick/00.hello/alpha/linux/o3-timing
|
||||
Exiting @ tick 6870 because target called exit()
|
||||
|
|
@ -7,11 +7,9 @@ max_tick=0
|
|||
output_file=cout
|
||||
progress_interval=0
|
||||
|
||||
[debug]
|
||||
break_cycles=
|
||||
|
||||
[exetrace]
|
||||
intel_format=false
|
||||
legion_lockstep=false
|
||||
pc_symbol=true
|
||||
print_cpseq=false
|
||||
print_cycle=true
|
||||
|
|
@ -53,73 +51,20 @@ mem_mode=atomic
|
|||
physmem=system.physmem
|
||||
|
||||
[system.cpu]
|
||||
type=DerivO3CPU
|
||||
children=dcache fuPool icache l2cache toL2Bus workload
|
||||
BTBEntries=4096
|
||||
BTBTagSize=16
|
||||
LFSTSize=1024
|
||||
LQEntries=32
|
||||
RASSize=16
|
||||
SQEntries=32
|
||||
SSITSize=1024
|
||||
activity=0
|
||||
backComSize=5
|
||||
choiceCtrBits=2
|
||||
choicePredictorSize=8192
|
||||
type=TimingSimpleCPU
|
||||
children=dcache icache l2cache toL2Bus workload
|
||||
clock=1
|
||||
commitToDecodeDelay=1
|
||||
commitToFetchDelay=1
|
||||
commitToIEWDelay=1
|
||||
commitToRenameDelay=1
|
||||
commitWidth=8
|
||||
decodeToFetchDelay=1
|
||||
decodeToRenameDelay=1
|
||||
decodeWidth=8
|
||||
cpu_id=0
|
||||
defer_registration=false
|
||||
dispatchWidth=8
|
||||
fetchToDecodeDelay=1
|
||||
fetchTrapLatency=1
|
||||
fetchWidth=8
|
||||
forwardComSize=5
|
||||
fuPool=system.cpu.fuPool
|
||||
function_trace=false
|
||||
function_trace_start=0
|
||||
globalCtrBits=2
|
||||
globalHistoryBits=13
|
||||
globalPredictorSize=8192
|
||||
iewToCommitDelay=1
|
||||
iewToDecodeDelay=1
|
||||
iewToFetchDelay=1
|
||||
iewToRenameDelay=1
|
||||
instShiftAmt=2
|
||||
issueToExecuteDelay=1
|
||||
issueWidth=8
|
||||
localCtrBits=2
|
||||
localHistoryBits=11
|
||||
localHistoryTableSize=2048
|
||||
localPredictorSize=2048
|
||||
max_insts_all_threads=0
|
||||
max_insts_any_thread=0
|
||||
max_loads_all_threads=0
|
||||
max_loads_any_thread=0
|
||||
mem=system.cpu.dcache
|
||||
numIQEntries=64
|
||||
numPhysFloatRegs=256
|
||||
numPhysIntRegs=256
|
||||
numROBEntries=192
|
||||
numRobs=1
|
||||
numThreads=1
|
||||
predType=tournament
|
||||
renameToDecodeDelay=1
|
||||
renameToFetchDelay=1
|
||||
renameToIEWDelay=2
|
||||
renameToROBDelay=1
|
||||
renameWidth=8
|
||||
squashWidth=8
|
||||
phase=0
|
||||
progress_interval=0
|
||||
system=system
|
||||
trapLatency=13
|
||||
wbDepth=1
|
||||
wbWidth=8
|
||||
workload=system.cpu.workload
|
||||
dcache_port=system.cpu.dcache.cpu_side
|
||||
icache_port=system.cpu.icache.cpu_side
|
||||
|
|
@ -131,7 +76,6 @@ assoc=2
|
|||
block_size=64
|
||||
compressed_bus=false
|
||||
compression_latency=0
|
||||
do_copy=false
|
||||
hash_delay=1
|
||||
hit_latency=1
|
||||
latency=1
|
||||
|
|
@ -164,143 +108,6 @@ write_buffers=8
|
|||
cpu_side=system.cpu.dcache_port
|
||||
mem_side=system.cpu.toL2Bus.port[1]
|
||||
|
||||
[system.cpu.fuPool]
|
||||
type=FUPool
|
||||
children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7
|
||||
FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7
|
||||
|
||||
[system.cpu.fuPool.FUList0]
|
||||
type=FUDesc
|
||||
children=opList0
|
||||
count=6
|
||||
opList=system.cpu.fuPool.FUList0.opList0
|
||||
|
||||
[system.cpu.fuPool.FUList0.opList0]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=IntAlu
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList1]
|
||||
type=FUDesc
|
||||
children=opList0 opList1
|
||||
count=2
|
||||
opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
|
||||
|
||||
[system.cpu.fuPool.FUList1.opList0]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=IntMult
|
||||
opLat=3
|
||||
|
||||
[system.cpu.fuPool.FUList1.opList1]
|
||||
type=OpDesc
|
||||
issueLat=19
|
||||
opClass=IntDiv
|
||||
opLat=20
|
||||
|
||||
[system.cpu.fuPool.FUList2]
|
||||
type=FUDesc
|
||||
children=opList0 opList1 opList2
|
||||
count=4
|
||||
opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
|
||||
|
||||
[system.cpu.fuPool.FUList2.opList0]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=FloatAdd
|
||||
opLat=2
|
||||
|
||||
[system.cpu.fuPool.FUList2.opList1]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=FloatCmp
|
||||
opLat=2
|
||||
|
||||
[system.cpu.fuPool.FUList2.opList2]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=FloatCvt
|
||||
opLat=2
|
||||
|
||||
[system.cpu.fuPool.FUList3]
|
||||
type=FUDesc
|
||||
children=opList0 opList1 opList2
|
||||
count=2
|
||||
opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
|
||||
|
||||
[system.cpu.fuPool.FUList3.opList0]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=FloatMult
|
||||
opLat=4
|
||||
|
||||
[system.cpu.fuPool.FUList3.opList1]
|
||||
type=OpDesc
|
||||
issueLat=12
|
||||
opClass=FloatDiv
|
||||
opLat=12
|
||||
|
||||
[system.cpu.fuPool.FUList3.opList2]
|
||||
type=OpDesc
|
||||
issueLat=24
|
||||
opClass=FloatSqrt
|
||||
opLat=24
|
||||
|
||||
[system.cpu.fuPool.FUList4]
|
||||
type=FUDesc
|
||||
children=opList0
|
||||
count=0
|
||||
opList=system.cpu.fuPool.FUList4.opList0
|
||||
|
||||
[system.cpu.fuPool.FUList4.opList0]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=MemRead
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5]
|
||||
type=FUDesc
|
||||
children=opList0
|
||||
count=0
|
||||
opList=system.cpu.fuPool.FUList5.opList0
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList0]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=MemWrite
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList6]
|
||||
type=FUDesc
|
||||
children=opList0 opList1
|
||||
count=4
|
||||
opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1
|
||||
|
||||
[system.cpu.fuPool.FUList6.opList0]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=MemRead
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList6.opList1]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=MemWrite
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList7]
|
||||
type=FUDesc
|
||||
children=opList0
|
||||
count=1
|
||||
opList=system.cpu.fuPool.FUList7.opList0
|
||||
|
||||
[system.cpu.fuPool.FUList7.opList0]
|
||||
type=OpDesc
|
||||
issueLat=3
|
||||
opClass=IprAccess
|
||||
opLat=3
|
||||
|
||||
[system.cpu.icache]
|
||||
type=BaseCache
|
||||
adaptive_compression=false
|
||||
|
|
@ -308,7 +115,6 @@ assoc=2
|
|||
block_size=64
|
||||
compressed_bus=false
|
||||
compression_latency=0
|
||||
do_copy=false
|
||||
hash_delay=1
|
||||
hit_latency=1
|
||||
latency=1
|
||||
|
|
@ -348,7 +154,6 @@ assoc=2
|
|||
block_size=64
|
||||
compressed_bus=false
|
||||
compression_latency=0
|
||||
do_copy=false
|
||||
hash_delay=1
|
||||
hit_latency=1
|
||||
latency=1
|
||||
|
|
@ -384,20 +189,33 @@ mem_side=system.membus.port[1]
|
|||
[system.cpu.toL2Bus]
|
||||
type=Bus
|
||||
bus_id=0
|
||||
clock=1000
|
||||
responder_set=false
|
||||
width=64
|
||||
port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
|
||||
|
||||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
cmd=hello
|
||||
cmd=vortex lendian.raw
|
||||
cwd=build/ALPHA_SE/tests/opt/long/50.vortex/alpha/linux/simple-timing
|
||||
egid=100
|
||||
env=
|
||||
executable=tests/test-progs/hello/bin/alpha/linux/hello
|
||||
euid=100
|
||||
executable=/dist/m5/cpu2000/binaries/alpha/tru64/vortex
|
||||
gid=100
|
||||
input=cin
|
||||
output=cout
|
||||
pid=100
|
||||
ppid=99
|
||||
system=system
|
||||
uid=100
|
||||
|
||||
[system.membus]
|
||||
type=Bus
|
||||
bus_id=0
|
||||
clock=1000
|
||||
responder_set=false
|
||||
width=64
|
||||
port=system.physmem.port system.cpu.l2cache.mem_side
|
||||
|
||||
[system.physmem]
|
||||
|
|
@ -409,6 +227,7 @@ port=system.membus.port[0]
|
|||
|
||||
[trace]
|
||||
bufsize=0
|
||||
cycle=0
|
||||
dump_on_exit=false
|
||||
file=cout
|
||||
flags=
|
||||
|
|
|
|||
|
|
@ -19,19 +19,54 @@ mem_mode=atomic
|
|||
[system.membus]
|
||||
type=Bus
|
||||
bus_id=0
|
||||
clock=1000
|
||||
width=64
|
||||
responder_set=false
|
||||
|
||||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
cmd=hello
|
||||
executable=tests/test-progs/hello/bin/alpha/linux/hello
|
||||
cmd=vortex lendian.raw
|
||||
executable=/dist/m5/cpu2000/binaries/alpha/tru64/vortex
|
||||
input=cin
|
||||
output=cout
|
||||
env=
|
||||
cwd=build/ALPHA_SE/tests/opt/long/50.vortex/alpha/linux/simple-timing
|
||||
system=system
|
||||
uid=100
|
||||
euid=100
|
||||
gid=100
|
||||
egid=100
|
||||
pid=100
|
||||
ppid=99
|
||||
|
||||
[system.cpu.dcache]
|
||||
[system.cpu]
|
||||
type=TimingSimpleCPU
|
||||
max_insts_any_thread=0
|
||||
max_insts_all_threads=0
|
||||
max_loads_any_thread=0
|
||||
max_loads_all_threads=0
|
||||
progress_interval=0
|
||||
system=system
|
||||
cpu_id=0
|
||||
workload=system.cpu.workload
|
||||
clock=1
|
||||
phase=0
|
||||
defer_registration=false
|
||||
// width not specified
|
||||
function_trace=false
|
||||
function_trace_start=0
|
||||
// simulate_stalls not specified
|
||||
|
||||
[system.cpu.toL2Bus]
|
||||
type=Bus
|
||||
bus_id=0
|
||||
clock=1000
|
||||
width=64
|
||||
responder_set=false
|
||||
|
||||
[system.cpu.icache]
|
||||
type=BaseCache
|
||||
size=262144
|
||||
size=131072
|
||||
assoc=2
|
||||
block_size=64
|
||||
latency=1
|
||||
|
|
@ -39,7 +74,6 @@ mshrs=10
|
|||
tgts_per_mshr=5
|
||||
write_buffers=8
|
||||
prioritizeRequests=false
|
||||
do_copy=false
|
||||
protocol=null
|
||||
trace_addr=0
|
||||
hash_delay=1
|
||||
|
|
@ -68,214 +102,9 @@ prefetch_use_cpu_id=true
|
|||
prefetch_data_accesses_only=false
|
||||
hit_latency=1
|
||||
|
||||
[system.cpu.fuPool.FUList0.opList0]
|
||||
type=OpDesc
|
||||
opClass=IntAlu
|
||||
opLat=1
|
||||
issueLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList0]
|
||||
type=FUDesc
|
||||
opList=system.cpu.fuPool.FUList0.opList0
|
||||
count=6
|
||||
|
||||
[system.cpu.fuPool.FUList1.opList0]
|
||||
type=OpDesc
|
||||
opClass=IntMult
|
||||
opLat=3
|
||||
issueLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList1.opList1]
|
||||
type=OpDesc
|
||||
opClass=IntDiv
|
||||
opLat=20
|
||||
issueLat=19
|
||||
|
||||
[system.cpu.fuPool.FUList1]
|
||||
type=FUDesc
|
||||
opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
|
||||
count=2
|
||||
|
||||
[system.cpu.fuPool.FUList2.opList0]
|
||||
type=OpDesc
|
||||
opClass=FloatAdd
|
||||
opLat=2
|
||||
issueLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList2.opList1]
|
||||
type=OpDesc
|
||||
opClass=FloatCmp
|
||||
opLat=2
|
||||
issueLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList2.opList2]
|
||||
type=OpDesc
|
||||
opClass=FloatCvt
|
||||
opLat=2
|
||||
issueLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList2]
|
||||
type=FUDesc
|
||||
opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
|
||||
count=4
|
||||
|
||||
[system.cpu.fuPool.FUList3.opList0]
|
||||
type=OpDesc
|
||||
opClass=FloatMult
|
||||
opLat=4
|
||||
issueLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList3.opList1]
|
||||
type=OpDesc
|
||||
opClass=FloatDiv
|
||||
opLat=12
|
||||
issueLat=12
|
||||
|
||||
[system.cpu.fuPool.FUList3.opList2]
|
||||
type=OpDesc
|
||||
opClass=FloatSqrt
|
||||
opLat=24
|
||||
issueLat=24
|
||||
|
||||
[system.cpu.fuPool.FUList3]
|
||||
type=FUDesc
|
||||
opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
|
||||
count=2
|
||||
|
||||
[system.cpu.fuPool.FUList4.opList0]
|
||||
type=OpDesc
|
||||
opClass=MemRead
|
||||
opLat=1
|
||||
issueLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList4]
|
||||
type=FUDesc
|
||||
opList=system.cpu.fuPool.FUList4.opList0
|
||||
count=0
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList0]
|
||||
type=OpDesc
|
||||
opClass=MemWrite
|
||||
opLat=1
|
||||
issueLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5]
|
||||
type=FUDesc
|
||||
opList=system.cpu.fuPool.FUList5.opList0
|
||||
count=0
|
||||
|
||||
[system.cpu.fuPool.FUList6.opList0]
|
||||
type=OpDesc
|
||||
opClass=MemRead
|
||||
opLat=1
|
||||
issueLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList6.opList1]
|
||||
type=OpDesc
|
||||
opClass=MemWrite
|
||||
opLat=1
|
||||
issueLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList6]
|
||||
type=FUDesc
|
||||
opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1
|
||||
count=4
|
||||
|
||||
[system.cpu.fuPool.FUList7.opList0]
|
||||
type=OpDesc
|
||||
opClass=IprAccess
|
||||
opLat=3
|
||||
issueLat=3
|
||||
|
||||
[system.cpu.fuPool.FUList7]
|
||||
type=FUDesc
|
||||
opList=system.cpu.fuPool.FUList7.opList0
|
||||
count=1
|
||||
|
||||
[system.cpu.fuPool]
|
||||
type=FUPool
|
||||
FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7
|
||||
|
||||
[system.cpu]
|
||||
type=DerivO3CPU
|
||||
clock=1
|
||||
numThreads=1
|
||||
activity=0
|
||||
workload=system.cpu.workload
|
||||
mem=system.cpu.dcache
|
||||
checker=null
|
||||
max_insts_any_thread=0
|
||||
max_insts_all_threads=0
|
||||
max_loads_any_thread=0
|
||||
max_loads_all_threads=0
|
||||
cachePorts=200
|
||||
decodeToFetchDelay=1
|
||||
renameToFetchDelay=1
|
||||
iewToFetchDelay=1
|
||||
commitToFetchDelay=1
|
||||
fetchWidth=8
|
||||
renameToDecodeDelay=1
|
||||
iewToDecodeDelay=1
|
||||
commitToDecodeDelay=1
|
||||
fetchToDecodeDelay=1
|
||||
decodeWidth=8
|
||||
iewToRenameDelay=1
|
||||
commitToRenameDelay=1
|
||||
decodeToRenameDelay=1
|
||||
renameWidth=8
|
||||
commitToIEWDelay=1
|
||||
renameToIEWDelay=2
|
||||
issueToExecuteDelay=1
|
||||
dispatchWidth=8
|
||||
issueWidth=8
|
||||
wbWidth=8
|
||||
wbDepth=1
|
||||
fuPool=system.cpu.fuPool
|
||||
iewToCommitDelay=1
|
||||
renameToROBDelay=1
|
||||
commitWidth=8
|
||||
squashWidth=8
|
||||
trapLatency=13
|
||||
backComSize=5
|
||||
forwardComSize=5
|
||||
predType=tournament
|
||||
localPredictorSize=2048
|
||||
localCtrBits=2
|
||||
localHistoryTableSize=2048
|
||||
localHistoryBits=11
|
||||
globalPredictorSize=8192
|
||||
globalCtrBits=2
|
||||
globalHistoryBits=13
|
||||
choicePredictorSize=8192
|
||||
choiceCtrBits=2
|
||||
BTBEntries=4096
|
||||
BTBTagSize=16
|
||||
RASSize=16
|
||||
LQEntries=32
|
||||
SQEntries=32
|
||||
LFSTSize=1024
|
||||
SSITSize=1024
|
||||
numPhysIntRegs=256
|
||||
numPhysFloatRegs=256
|
||||
numIQEntries=64
|
||||
numROBEntries=192
|
||||
smtNumFetchingThreads=1
|
||||
smtFetchPolicy=SingleThread
|
||||
smtLSQPolicy=Partitioned
|
||||
smtLSQThreshold=100
|
||||
smtIQPolicy=Partitioned
|
||||
smtIQThreshold=100
|
||||
smtROBPolicy=Partitioned
|
||||
smtROBThreshold=100
|
||||
smtCommitPolicy=RoundRobin
|
||||
instShiftAmt=2
|
||||
defer_registration=false
|
||||
function_trace=false
|
||||
function_trace_start=0
|
||||
|
||||
[system.cpu.icache]
|
||||
[system.cpu.dcache]
|
||||
type=BaseCache
|
||||
size=131072
|
||||
size=262144
|
||||
assoc=2
|
||||
block_size=64
|
||||
latency=1
|
||||
|
|
@ -283,7 +112,6 @@ mshrs=10
|
|||
tgts_per_mshr=5
|
||||
write_buffers=8
|
||||
prioritizeRequests=false
|
||||
do_copy=false
|
||||
protocol=null
|
||||
trace_addr=0
|
||||
hash_delay=1
|
||||
|
|
@ -322,7 +150,6 @@ mshrs=10
|
|||
tgts_per_mshr=5
|
||||
write_buffers=8
|
||||
prioritizeRequests=false
|
||||
do_copy=false
|
||||
protocol=null
|
||||
trace_addr=0
|
||||
hash_delay=1
|
||||
|
|
@ -351,13 +178,10 @@ prefetch_use_cpu_id=true
|
|||
prefetch_data_accesses_only=false
|
||||
hit_latency=1
|
||||
|
||||
[system.cpu.toL2Bus]
|
||||
type=Bus
|
||||
bus_id=0
|
||||
|
||||
[trace]
|
||||
flags=
|
||||
start=0
|
||||
cycle=0
|
||||
bufsize=0
|
||||
file=cout
|
||||
dump_on_exit=false
|
||||
|
|
@ -396,8 +220,9 @@ print_cpseq=false
|
|||
print_reg_delta=false
|
||||
pc_symbol=true
|
||||
intel_format=false
|
||||
legion_lockstep=false
|
||||
trace_system=client
|
||||
|
||||
[debug]
|
||||
break_cycles=
|
||||
[statsreset]
|
||||
reset_cycle=0
|
||||
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
158
tests/long/50.vortex/ref/alpha/linux/simple-timing/smred.msg
Normal file
158
tests/long/50.vortex/ref/alpha/linux/simple-timing/smred.msg
Normal file
|
|
@ -0,0 +1,158 @@
|
|||
|
||||
SYSTEM TYPE...
|
||||
__ZTC__ := False
|
||||
__UNIX__ := True
|
||||
__RISC__ := True
|
||||
SPEC_CPU2000_LP64 := True
|
||||
__MAC__ := False
|
||||
__BCC__ := False
|
||||
__BORLANDC__ := False
|
||||
__GUI__ := False
|
||||
__WTC__ := False
|
||||
__HP__ := False
|
||||
|
||||
CODE OPTIONS...
|
||||
__MACROIZE_HM__ := True
|
||||
__MACROIZE_MEM__ := True
|
||||
ENV01 := True
|
||||
USE_HPP_STYPE_HDRS := False
|
||||
USE_H_STYPE_HDRS := False
|
||||
|
||||
CODE INCLUSION PARAMETERS...
|
||||
INCLUDE_ALL_CODE := False
|
||||
INCLUDE_DELETE_CODE := True
|
||||
__SWAP_GRP_POS__ := True
|
||||
__INCLUDE_MTRX__ := False
|
||||
__BAD_CODE__ := False
|
||||
API_INCLUDE := False
|
||||
BE_CAREFUL := False
|
||||
OLDWAY := False
|
||||
NOTUSED := False
|
||||
|
||||
SYSTEM PARAMETERS...
|
||||
EXT_ENUM := 999999999L
|
||||
CHUNK_CONSTANT := 55555555
|
||||
CORE_CONSTANT := 55555555
|
||||
CORE_LIMIT := 20971520
|
||||
CorePage_Size := 384000
|
||||
ALIGN_BYTES := True
|
||||
CORE_BLOCK_ALIGN := 8
|
||||
FAR_MEM := False
|
||||
|
||||
MEMORY MANAGEMENT PARAMETERS...
|
||||
SYSTEM_ALLOC := True
|
||||
SYSTEM_FREESTORE := True
|
||||
__NO_DISKCACHE__ := False
|
||||
__FREEZE_VCHUNKS__ := True
|
||||
__FREEZE_GRP_PACKETS__ := True
|
||||
__MINIMIZE_TREE_CACHE__:= True
|
||||
|
||||
SYSTEM STD PARAMETERS...
|
||||
__STDOUT__ := False
|
||||
NULL := 0
|
||||
LPTR := False
|
||||
False_Status := 1
|
||||
True_Status := 0
|
||||
LARGE := True
|
||||
TWOBYTE_BOOL := False
|
||||
__NOSTR__ := False
|
||||
|
||||
MEMORY VALIDATION PARAMETERS...
|
||||
CORE_CRC_CHECK := False
|
||||
VALIDATE_MEM_CHUNKS := False
|
||||
|
||||
SYSTEM DEBUG OPTIONS...
|
||||
DEBUG := False
|
||||
MCSTAT := False
|
||||
TRACKBACK := False
|
||||
FLUSH_FILES := False
|
||||
DEBUG_CORE0 := False
|
||||
DEBUG_RISC := False
|
||||
__TREE_BUG__ := False
|
||||
__TRACK_FILE_READS__ := False
|
||||
PAGE_SPACE := False
|
||||
LEAVE_NO_TRACE := True
|
||||
NULL_TRACE_STRS := False
|
||||
|
||||
TIME PARAMETERS...
|
||||
CLOCK_IS_LONG := False
|
||||
__DISPLAY_TIME__ := False
|
||||
__TREE_TIME__ := False
|
||||
__DISPLAY_ERRORS__ := False
|
||||
|
||||
API MACROS...
|
||||
__BMT01__ := True
|
||||
OPTIMIZE := True
|
||||
|
||||
END OF DEFINES.
|
||||
|
||||
|
||||
|
||||
... IMPLODE MEMORY ...
|
||||
|
||||
SWAP to DiskCache := False
|
||||
|
||||
FREEZE_GRP_PACKETS:= True
|
||||
|
||||
QueBug := 1000
|
||||
|
||||
sizeof(boolean) = 4
|
||||
sizeof(sizetype) = 4
|
||||
sizeof(chunkstruc) = 32
|
||||
|
||||
sizeof(shorttype ) = 2
|
||||
sizeof(idtype ) = 2
|
||||
sizeof(sizetype ) = 4
|
||||
sizeof(indextype ) = 4
|
||||
sizeof(numtype ) = 4
|
||||
sizeof(handletype) = 4
|
||||
sizeof(tokentype ) = 8
|
||||
|
||||
sizeof(short ) = 2
|
||||
sizeof(int ) = 4
|
||||
|
||||
sizeof(lt64 ) = 4
|
||||
sizeof(farlongtype) = 4
|
||||
sizeof(long ) = 8
|
||||
sizeof(longaddr ) = 8
|
||||
|
||||
sizeof(float ) = 4
|
||||
sizeof(double ) = 8
|
||||
|
||||
sizeof(addrtype ) = 8
|
||||
sizeof(char * ) = 8
|
||||
ALLOC CORE_1 :: 16
|
||||
BHOOLE NATH
|
||||
|
||||
OPEN File ./input/lendian.rnv
|
||||
*Status = 0
|
||||
DB HDR restored from FileVbn[ 0]
|
||||
DB BlkDirOffset : @ 2030c0
|
||||
DB BlkDirChunk : Chunk[ 10] AT Vbn[3146]
|
||||
DB BlkTknChunk : Chunk[ 11] AT Vbn[3147]
|
||||
DB BlkSizeChunk : Chunk[ 12] AT Vbn[3148]
|
||||
DB Handle Chunk's StackPtr = 20797
|
||||
|
||||
DB[ 1] LOADED; Handles= 20797
|
||||
KERNEL in CORE[ 1] Restored @ 40054800
|
||||
|
||||
OPEN File ./input/lendian.wnv
|
||||
*Status = 0
|
||||
DB HDR restored from FileVbn[ 0]
|
||||
DB BlkDirOffset : @ 21c40
|
||||
DB BlkDirChunk : Chunk[ 31] AT Vbn[ 81]
|
||||
DB BlkTknChunk : Chunk[ 32] AT Vbn[ 82]
|
||||
DB BlkSizeChunk : Chunk[ 33] AT Vbn[ 83]
|
||||
DB Handle Chunk's StackPtr = 17
|
||||
|
||||
DB[ 2] LOADED; Handles= 17
|
||||
VORTEx_Status == -8 || fffffff8
|
||||
|
||||
BE HERE NOW !!!
|
||||
|
||||
|
||||
|
||||
... VORTEx ON LINE ...
|
||||
|
||||
|
||||
... END OF SESSION ...
|
||||
258
tests/long/50.vortex/ref/alpha/linux/simple-timing/smred.out
Normal file
258
tests/long/50.vortex/ref/alpha/linux/simple-timing/smred.out
Normal file
|
|
@ -0,0 +1,258 @@
|
|||
CREATE Db Header and Db Primal ...
|
||||
NEW DB [ 3] Created.
|
||||
|
||||
VORTEX INPUT PARAMETERS::
|
||||
MESSAGE FileName: smred.msg
|
||||
OUTPUT FileName: smred.out
|
||||
DISK CACHE FileName: NULL
|
||||
PART DB FileName: parts.db
|
||||
DRAW DB FileName: draw.db
|
||||
PERSON DB FileName: emp.db
|
||||
PERSONS Data FileName: ./input/persons.250
|
||||
PARTS Count : 100
|
||||
OUTER Loops : 1
|
||||
INNER Loops : 1
|
||||
LOOKUP Parts : 25
|
||||
DELETE Parts : 10
|
||||
STUFF Parts : 10
|
||||
DEPTH Traverse: 5
|
||||
% DECREASE Parts : 0
|
||||
% INCREASE LookUps : 0
|
||||
% INCREASE Deletes : 0
|
||||
% INCREASE Stuffs : 0
|
||||
FREEZE_PACKETS : 1
|
||||
ALLOC_CHUNKS : 10000
|
||||
EXTEND_CHUNKS : 5000
|
||||
DELETE Draw objects : True
|
||||
DELETE Part objects : False
|
||||
QUE_BUG : 1000
|
||||
VOID_BOUNDARY : 67108864
|
||||
VOID_RESERVE : 1048576
|
||||
|
||||
COMMIT_DBS : False
|
||||
|
||||
|
||||
|
||||
BMT TEST :: files...
|
||||
EdbName := PartLib
|
||||
EdbFileName := parts.db
|
||||
DrwName := DrawLib
|
||||
DrwFileName := draw.db
|
||||
EmpName := PersonLib
|
||||
EmpFileName := emp.db
|
||||
|
||||
Swap to DiskCache := False
|
||||
Freeze the cache := True
|
||||
|
||||
|
||||
BMT TEST :: parms...
|
||||
DeBug modulo := 1000
|
||||
Create Parts count:= 100
|
||||
Outer Loops := 1
|
||||
Inner Loops := 1
|
||||
Look Ups := 25
|
||||
Delete Parts := 10
|
||||
Stuff Parts := 10
|
||||
Traverse Limit := 5
|
||||
Delete Draws := True
|
||||
Delete Parts := False
|
||||
Delete ALL Parts := after every <mod 0>Outer Loop
|
||||
|
||||
INITIALIZE LIBRARY ::
|
||||
|
||||
INITIALIZE SCHEMA ::
|
||||
Primal_CreateDb Accessed !!!
|
||||
CREATE Db Header and Db Primal ...
|
||||
NEW DB [ 4] Created.
|
||||
PartLibCreate:: Db[ 4]; VpartsDir= 1
|
||||
|
||||
Part Count= 1
|
||||
|
||||
Initialize the Class maps
|
||||
LIST HEADS loaded ... DbListHead_Class = 207
|
||||
DbListNode_Class = 206
|
||||
|
||||
...NOTE... ShellLoadCode:: Class[ 228] will NOT be Activated.
|
||||
|
||||
|
||||
...NOTE... ShellLoadCode:: Class[ 229] will NOT be Activated.
|
||||
|
||||
Primal_CreateDb Accessed !!!
|
||||
CREATE Db Header and Db Primal ...
|
||||
NEW DB [ 5] Created.
|
||||
DrawLibCreate:: Db[ 5]; VpartsDir= 1
|
||||
|
||||
Initialize the Class maps of this schema.
|
||||
Primal_CreateDb Accessed !!!
|
||||
CREATE Db Header and Db Primal ...
|
||||
NEW DB [ 6] Created.
|
||||
|
||||
***NOTE*** Persons Library Extended!
|
||||
|
||||
Create <131072> Persons.
|
||||
ItNum 0. Person[ 6: 5]. Name= Riddell , Robert V. ;
|
||||
|
||||
LAST Person Read::
|
||||
ItNum 250. Person[ 6: 503]. Name= Gonzales , Warren X. ;
|
||||
|
||||
BUILD <Query0> for <Part2> class::
|
||||
|
||||
if (link[1].length >= 5) ::
|
||||
|
||||
Build Query2 for <Address> class::
|
||||
|
||||
if (State == CA || State == T*)
|
||||
|
||||
Build Query1 for <Person> class::
|
||||
|
||||
if (LastName >= H* && LastName <= P* && Query0(Residence)) ::
|
||||
|
||||
BUILD <Query3> for <DrawObj> class::
|
||||
|
||||
if (Id >= 3000
|
||||
&& (Id >= 3000 && Id <= 3001)
|
||||
&& Id >= 3002)
|
||||
|
||||
BUILD <Query4> for <NamedDrawObj> class::
|
||||
|
||||
if (Nam == Pre*
|
||||
|| (Nam == ??Mid??? || == Pre??Mid?? || == ??Post
|
||||
|| == Pre??Post || == ??Mid???Post || == Pre??Mid???Post)
|
||||
&& Id <= 7)
|
||||
SEED := 1008; Swap = False; RgnEntries = 135
|
||||
|
||||
OUTER LOOP [ 1] : NewParts = 100 LookUps = 25 StuffParts = 10.
|
||||
|
||||
Create 100 New Parts
|
||||
Create Part 1. Token[ 4: 2].
|
||||
|
||||
< 100> Parts Created. CurrentId= 100
|
||||
|
||||
Connect each instantiated Part TO 3 unique Parts
|
||||
Connect Part 1. Token[ 4: 2]
|
||||
Connect Part 25. Token[ 4: 26] FromList= 26.
|
||||
Connect Part 12. Token[ 4: 13] FromList= 13.
|
||||
Connect Part 59. Token[ 4: 60] FromList= 60.
|
||||
|
||||
SET <DrawObjs> entries::
|
||||
1. [ 5: 5] := <1 >; @[: 6]
|
||||
Iteration count = 100
|
||||
|
||||
SET <NamedDrawObjs> entries::
|
||||
1. [ 5: 39] := <14 >;
|
||||
Iteration count = 12
|
||||
|
||||
SET <LibRectangles> entries::
|
||||
1. [ 5: 23] := <8 >; @[: 24]
|
||||
Iteration count = 12
|
||||
|
||||
LIST <DbRectangles> entries::
|
||||
1. [ 5: 23]
|
||||
Iteration count = 12
|
||||
|
||||
SET <PersonNames > entries::
|
||||
Iteration count = 250
|
||||
|
||||
COMMIT All Image copies:: Release=<True>; Max Parts= 100
|
||||
< 100> Part images' Committed.
|
||||
< 0> are Named.
|
||||
< 50> Point images' Committed.
|
||||
< 81> Person images' Committed.
|
||||
|
||||
COMMIT Parts(* 100)
|
||||
|
||||
Commit TestObj_Class in <Primal> DB.
|
||||
ItNum 0. Token[ 0: 0]. TestObj Committed.
|
||||
< 0> TestObj images' Committed.
|
||||
|
||||
Commit CartesianPoint_Class in <Primal> DB.
|
||||
ItNum 0. Token[ 0: 0]. CartesianPoint Committed.
|
||||
< 0> CartesianPoint images' Committed.
|
||||
|
||||
BEGIN Inner Loop Sequence::.
|
||||
|
||||
INNER LOOP [ 1: 1] :
|
||||
|
||||
LOOK UP 25 Random Parts and Export each Part.
|
||||
|
||||
LookUp for 26 parts; Asserts = 8
|
||||
<Part2 > Asserts = 2; NULL Asserts = 3.
|
||||
<DrawObj > Asserts = 0; NULL Asserts = 5.
|
||||
<NamedObj > Asserts = 0; NULL Asserts = 0.
|
||||
<Person > Asserts = 0; NULL Asserts = 5.
|
||||
<TestObj > Asserts = 60; NULL Asserts = 0.
|
||||
|
||||
DELETE 10 Random Parts.
|
||||
|
||||
PartDelete :: Token[ 4: 91].
|
||||
PartDisconnect:: Token[ 4: 91] id:= 90 for each link.
|
||||
DisConnect link [ 0]:= 50; PartToken[ 51: 51].
|
||||
DisConnect link [ 1]:= 17; PartToken[ 18: 18].
|
||||
DisConnect link [ 2]:= 72; PartToken[ 73: 73].
|
||||
DeleteFromList:: Vchunk[ 4: 91]. (* 1)
|
||||
DisConnect FromList[ 0]:= 56; Token[ 57: 57].
|
||||
Vlists[ 89] := 100;
|
||||
|
||||
Delete for 11 parts;
|
||||
|
||||
Traverse Count= 0
|
||||
|
||||
TRAVERSE PartId[ 6] and all Connections to 5 Levels
|
||||
SEED In Traverse Part [ 4: 65] @ Level = 4.
|
||||
|
||||
Traverse Count= 357
|
||||
Traverse Asserts = 5. True Tests = 1
|
||||
< 5> DrawObj objects DELETED.
|
||||
< 2> are Named.
|
||||
< 2> Point objects DELETED.
|
||||
|
||||
CREATE 10 Additional Parts
|
||||
|
||||
Create 10 New Parts
|
||||
Create Part 101. Token[ 4: 102].
|
||||
|
||||
< 10> Parts Created. CurrentId= 110
|
||||
|
||||
Connect each instantiated Part TO 3 unique Parts
|
||||
|
||||
COMMIT All Image copies:: Release=<True>; Max Parts= 110
|
||||
< 81> Part images' Committed.
|
||||
< 0> are Named.
|
||||
< 38> Point images' Committed.
|
||||
< 31> Person images' Committed.
|
||||
|
||||
COMMIT Parts(* 100)
|
||||
|
||||
Commit TestObj_Class in <Primal> DB.
|
||||
ItNum 0. Token[ 3: 4]. TestObj Committed.
|
||||
< 15> TestObj images' Committed.
|
||||
|
||||
Commit CartesianPoint_Class in <Primal> DB.
|
||||
ItNum 0. Token[ 3: 3]. CartesianPoint Committed.
|
||||
< 16> CartesianPoint images' Committed.
|
||||
|
||||
DELETE All TestObj objects;
|
||||
|
||||
Delete TestObj_Class in <Primal> DB.
|
||||
ItNum 0. Token[ 3: 4]. TestObj Deleted.
|
||||
< 15> TestObj objects Deleted.
|
||||
|
||||
Commit CartesianPoint_Class in <Primal> DB.
|
||||
ItNum 0. Token[ 3: 3]. CartesianPoint Deleted.
|
||||
< 16> CartesianPoint objects Deleted.
|
||||
|
||||
DELETE TestObj and Point objects...
|
||||
|
||||
END INNER LOOP [ 1: 1].
|
||||
|
||||
DELETE All TestObj objects;
|
||||
|
||||
Delete TestObj_Class in <Primal> DB.
|
||||
< 0> TestObj objects Deleted.
|
||||
|
||||
Commit CartesianPoint_Class in <Primal> DB.
|
||||
< 0> CartesianPoint objects Deleted.
|
||||
|
||||
DELETE TestObj and Point objects...
|
||||
STATUS= -201
|
||||
V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1!
|
||||
|
|
@ -1,3 +1 @@
|
|||
warn: Entering event queue @ 0. Starting simulation...
|
||||
warn: cycle 0: fault (page_table_fault) detected @ PC 0x000000
|
||||
warn: Increasing stack 0x11ff92000:0x11ff9b000 to 0x11ff90000:0x11ff9b000 because of access to 0x11ff91ff0
|
||||
|
|
|
|||
|
|
@ -1,13 +0,0 @@
|
|||
Hello world!
|
||||
M5 Simulator System
|
||||
|
||||
Copyright (c) 2001-2006
|
||||
The Regents of The University of Michigan
|
||||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Sep 5 2006 15:28:48
|
||||
M5 started Tue Sep 5 15:42:12 2006
|
||||
M5 executing on zizzer.eecs.umich.edu
|
||||
command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/o3-timing tests/run.py quick/00.hello/alpha/linux/o3-timing
|
||||
Exiting @ tick 6870 because target called exit()
|
||||
|
|
@ -7,11 +7,9 @@ max_tick=0
|
|||
output_file=cout
|
||||
progress_interval=0
|
||||
|
||||
[debug]
|
||||
break_cycles=
|
||||
|
||||
[exetrace]
|
||||
intel_format=false
|
||||
legion_lockstep=false
|
||||
pc_symbol=true
|
||||
print_cpseq=false
|
||||
print_cycle=true
|
||||
|
|
@ -102,14 +100,15 @@ max_insts_all_threads=0
|
|||
max_insts_any_thread=0
|
||||
max_loads_all_threads=0
|
||||
max_loads_any_thread=0
|
||||
mem=system.cpu.dcache
|
||||
numIQEntries=64
|
||||
numPhysFloatRegs=256
|
||||
numPhysIntRegs=256
|
||||
numROBEntries=192
|
||||
numRobs=1
|
||||
numThreads=1
|
||||
phase=0
|
||||
predType=tournament
|
||||
progress_interval=0
|
||||
renameToDecodeDelay=1
|
||||
renameToFetchDelay=1
|
||||
renameToIEWDelay=2
|
||||
|
|
@ -131,7 +130,6 @@ assoc=2
|
|||
block_size=64
|
||||
compressed_bus=false
|
||||
compression_latency=0
|
||||
do_copy=false
|
||||
hash_delay=1
|
||||
hit_latency=1
|
||||
latency=1
|
||||
|
|
@ -308,7 +306,6 @@ assoc=2
|
|||
block_size=64
|
||||
compressed_bus=false
|
||||
compression_latency=0
|
||||
do_copy=false
|
||||
hash_delay=1
|
||||
hit_latency=1
|
||||
latency=1
|
||||
|
|
@ -348,7 +345,6 @@ assoc=2
|
|||
block_size=64
|
||||
compressed_bus=false
|
||||
compression_latency=0
|
||||
do_copy=false
|
||||
hash_delay=1
|
||||
hit_latency=1
|
||||
latency=1
|
||||
|
|
@ -384,20 +380,33 @@ mem_side=system.membus.port[1]
|
|||
[system.cpu.toL2Bus]
|
||||
type=Bus
|
||||
bus_id=0
|
||||
clock=1000
|
||||
responder_set=false
|
||||
width=64
|
||||
port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
|
||||
|
||||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
cmd=hello
|
||||
cmd=bzip2 input.source 1
|
||||
cwd=build/ALPHA_SE/tests/opt/long/60.bzip2/alpha/linux/o3-timing
|
||||
egid=100
|
||||
env=
|
||||
executable=tests/test-progs/hello/bin/alpha/linux/hello
|
||||
euid=100
|
||||
executable=/dist/m5/cpu2000/binaries/alpha/tru64/bzip2
|
||||
gid=100
|
||||
input=cin
|
||||
output=cout
|
||||
pid=100
|
||||
ppid=99
|
||||
system=system
|
||||
uid=100
|
||||
|
||||
[system.membus]
|
||||
type=Bus
|
||||
bus_id=0
|
||||
clock=1000
|
||||
responder_set=false
|
||||
width=64
|
||||
port=system.physmem.port system.cpu.l2cache.mem_side
|
||||
|
||||
[system.physmem]
|
||||
|
|
@ -409,6 +418,7 @@ port=system.membus.port[0]
|
|||
|
||||
[trace]
|
||||
bufsize=0
|
||||
cycle=0
|
||||
dump_on_exit=false
|
||||
file=cout
|
||||
flags=
|
||||
|
|
|
|||
|
|
@ -19,54 +19,25 @@ mem_mode=atomic
|
|||
[system.membus]
|
||||
type=Bus
|
||||
bus_id=0
|
||||
clock=1000
|
||||
width=64
|
||||
responder_set=false
|
||||
|
||||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
cmd=hello
|
||||
executable=tests/test-progs/hello/bin/alpha/linux/hello
|
||||
cmd=bzip2 input.source 1
|
||||
executable=/dist/m5/cpu2000/binaries/alpha/tru64/bzip2
|
||||
input=cin
|
||||
output=cout
|
||||
env=
|
||||
cwd=build/ALPHA_SE/tests/opt/long/60.bzip2/alpha/linux/o3-timing
|
||||
system=system
|
||||
|
||||
[system.cpu.dcache]
|
||||
type=BaseCache
|
||||
size=262144
|
||||
assoc=2
|
||||
block_size=64
|
||||
latency=1
|
||||
mshrs=10
|
||||
tgts_per_mshr=5
|
||||
write_buffers=8
|
||||
prioritizeRequests=false
|
||||
do_copy=false
|
||||
protocol=null
|
||||
trace_addr=0
|
||||
hash_delay=1
|
||||
repl=null
|
||||
compressed_bus=false
|
||||
store_compressed=false
|
||||
adaptive_compression=false
|
||||
compression_latency=0
|
||||
block_size=64
|
||||
max_miss_count=0
|
||||
addr_range=[0,18446744073709551615]
|
||||
split=false
|
||||
split_size=0
|
||||
lifo=false
|
||||
two_queue=false
|
||||
prefetch_miss=false
|
||||
prefetch_access=false
|
||||
prefetcher_size=100
|
||||
prefetch_past_page=false
|
||||
prefetch_serial_squash=false
|
||||
prefetch_latency=10
|
||||
prefetch_degree=1
|
||||
prefetch_policy=none
|
||||
prefetch_cache_check_push=true
|
||||
prefetch_use_cpu_id=true
|
||||
prefetch_data_accesses_only=false
|
||||
hit_latency=1
|
||||
uid=100
|
||||
euid=100
|
||||
gid=100
|
||||
egid=100
|
||||
pid=100
|
||||
ppid=99
|
||||
|
||||
[system.cpu.fuPool.FUList0.opList0]
|
||||
type=OpDesc
|
||||
|
|
@ -199,15 +170,16 @@ FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUL
|
|||
[system.cpu]
|
||||
type=DerivO3CPU
|
||||
clock=1
|
||||
phase=0
|
||||
numThreads=1
|
||||
activity=0
|
||||
workload=system.cpu.workload
|
||||
mem=system.cpu.dcache
|
||||
checker=null
|
||||
max_insts_any_thread=0
|
||||
max_insts_all_threads=0
|
||||
max_loads_any_thread=0
|
||||
max_loads_all_threads=0
|
||||
progress_interval=0
|
||||
cachePorts=200
|
||||
decodeToFetchDelay=1
|
||||
renameToFetchDelay=1
|
||||
|
|
@ -283,7 +255,44 @@ mshrs=10
|
|||
tgts_per_mshr=5
|
||||
write_buffers=8
|
||||
prioritizeRequests=false
|
||||
do_copy=false
|
||||
protocol=null
|
||||
trace_addr=0
|
||||
hash_delay=1
|
||||
repl=null
|
||||
compressed_bus=false
|
||||
store_compressed=false
|
||||
adaptive_compression=false
|
||||
compression_latency=0
|
||||
block_size=64
|
||||
max_miss_count=0
|
||||
addr_range=[0,18446744073709551615]
|
||||
split=false
|
||||
split_size=0
|
||||
lifo=false
|
||||
two_queue=false
|
||||
prefetch_miss=false
|
||||
prefetch_access=false
|
||||
prefetcher_size=100
|
||||
prefetch_past_page=false
|
||||
prefetch_serial_squash=false
|
||||
prefetch_latency=10
|
||||
prefetch_degree=1
|
||||
prefetch_policy=none
|
||||
prefetch_cache_check_push=true
|
||||
prefetch_use_cpu_id=true
|
||||
prefetch_data_accesses_only=false
|
||||
hit_latency=1
|
||||
|
||||
[system.cpu.dcache]
|
||||
type=BaseCache
|
||||
size=262144
|
||||
assoc=2
|
||||
block_size=64
|
||||
latency=1
|
||||
mshrs=10
|
||||
tgts_per_mshr=5
|
||||
write_buffers=8
|
||||
prioritizeRequests=false
|
||||
protocol=null
|
||||
trace_addr=0
|
||||
hash_delay=1
|
||||
|
|
@ -322,7 +331,6 @@ mshrs=10
|
|||
tgts_per_mshr=5
|
||||
write_buffers=8
|
||||
prioritizeRequests=false
|
||||
do_copy=false
|
||||
protocol=null
|
||||
trace_addr=0
|
||||
hash_delay=1
|
||||
|
|
@ -354,10 +362,14 @@ hit_latency=1
|
|||
[system.cpu.toL2Bus]
|
||||
type=Bus
|
||||
bus_id=0
|
||||
clock=1000
|
||||
width=64
|
||||
responder_set=false
|
||||
|
||||
[trace]
|
||||
flags=
|
||||
start=0
|
||||
cycle=0
|
||||
bufsize=0
|
||||
file=cout
|
||||
dump_on_exit=false
|
||||
|
|
@ -396,8 +408,9 @@ print_cpseq=false
|
|||
print_reg_delta=false
|
||||
pc_symbol=true
|
||||
intel_format=false
|
||||
legion_lockstep=false
|
||||
trace_system=client
|
||||
|
||||
[debug]
|
||||
break_cycles=
|
||||
[statsreset]
|
||||
reset_cycle=0
|
||||
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -1,3 +1 @@
|
|||
warn: Entering event queue @ 0. Starting simulation...
|
||||
warn: cycle 0: fault (page_table_fault) detected @ PC 0x000000
|
||||
warn: Increasing stack 0x11ff92000:0x11ff9b000 to 0x11ff90000:0x11ff9b000 because of access to 0x11ff91ff0
|
||||
|
|
|
|||
|
|
@ -1,13 +1,14 @@
|
|||
Hello world!
|
||||
M5 Simulator System
|
||||
|
||||
Copyright (c) 2001-2006
|
||||
The Regents of The University of Michigan
|
||||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Sep 5 2006 15:28:48
|
||||
M5 started Tue Sep 5 15:42:12 2006
|
||||
M5 executing on zizzer.eecs.umich.edu
|
||||
command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/o3-timing tests/run.py quick/00.hello/alpha/linux/o3-timing
|
||||
Exiting @ tick 6870 because target called exit()
|
||||
spec_init
|
||||
Loading Input Data
|
||||
Input data 1048576 bytes in length
|
||||
Compressing Input Data, level 7
|
||||
Compressed data 198546 bytes in length
|
||||
Uncompressing Data
|
||||
Uncompressed data 1048576 bytes in length
|
||||
Uncompressed data compared correctly
|
||||
Compressing Input Data, level 9
|
||||
Compressed data 198677 bytes in length
|
||||
Uncompressing Data
|
||||
Uncompressed data 1048576 bytes in length
|
||||
Uncompressed data compared correctly
|
||||
Tested 1MB buffer: OK!
|
||||
|
|
|
|||
|
|
@ -7,11 +7,9 @@ max_tick=0
|
|||
output_file=cout
|
||||
progress_interval=0
|
||||
|
||||
[debug]
|
||||
break_cycles=
|
||||
|
||||
[exetrace]
|
||||
intel_format=false
|
||||
legion_lockstep=false
|
||||
pc_symbol=true
|
||||
print_cpseq=false
|
||||
print_cycle=true
|
||||
|
|
@ -53,352 +51,49 @@ mem_mode=atomic
|
|||
physmem=system.physmem
|
||||
|
||||
[system.cpu]
|
||||
type=DerivO3CPU
|
||||
children=dcache fuPool icache l2cache toL2Bus workload
|
||||
BTBEntries=4096
|
||||
BTBTagSize=16
|
||||
LFSTSize=1024
|
||||
LQEntries=32
|
||||
RASSize=16
|
||||
SQEntries=32
|
||||
SSITSize=1024
|
||||
activity=0
|
||||
backComSize=5
|
||||
choiceCtrBits=2
|
||||
choicePredictorSize=8192
|
||||
type=AtomicSimpleCPU
|
||||
children=workload
|
||||
clock=1
|
||||
commitToDecodeDelay=1
|
||||
commitToFetchDelay=1
|
||||
commitToIEWDelay=1
|
||||
commitToRenameDelay=1
|
||||
commitWidth=8
|
||||
decodeToFetchDelay=1
|
||||
decodeToRenameDelay=1
|
||||
decodeWidth=8
|
||||
cpu_id=0
|
||||
defer_registration=false
|
||||
dispatchWidth=8
|
||||
fetchToDecodeDelay=1
|
||||
fetchTrapLatency=1
|
||||
fetchWidth=8
|
||||
forwardComSize=5
|
||||
fuPool=system.cpu.fuPool
|
||||
function_trace=false
|
||||
function_trace_start=0
|
||||
globalCtrBits=2
|
||||
globalHistoryBits=13
|
||||
globalPredictorSize=8192
|
||||
iewToCommitDelay=1
|
||||
iewToDecodeDelay=1
|
||||
iewToFetchDelay=1
|
||||
iewToRenameDelay=1
|
||||
instShiftAmt=2
|
||||
issueToExecuteDelay=1
|
||||
issueWidth=8
|
||||
localCtrBits=2
|
||||
localHistoryBits=11
|
||||
localHistoryTableSize=2048
|
||||
localPredictorSize=2048
|
||||
max_insts_all_threads=0
|
||||
max_insts_any_thread=0
|
||||
max_loads_all_threads=0
|
||||
max_loads_any_thread=0
|
||||
mem=system.cpu.dcache
|
||||
numIQEntries=64
|
||||
numPhysFloatRegs=256
|
||||
numPhysIntRegs=256
|
||||
numROBEntries=192
|
||||
numRobs=1
|
||||
numThreads=1
|
||||
predType=tournament
|
||||
renameToDecodeDelay=1
|
||||
renameToFetchDelay=1
|
||||
renameToIEWDelay=2
|
||||
renameToROBDelay=1
|
||||
renameWidth=8
|
||||
squashWidth=8
|
||||
phase=0
|
||||
progress_interval=0
|
||||
simulate_stalls=false
|
||||
system=system
|
||||
trapLatency=13
|
||||
wbDepth=1
|
||||
wbWidth=8
|
||||
width=1
|
||||
workload=system.cpu.workload
|
||||
dcache_port=system.cpu.dcache.cpu_side
|
||||
icache_port=system.cpu.icache.cpu_side
|
||||
|
||||
[system.cpu.dcache]
|
||||
type=BaseCache
|
||||
adaptive_compression=false
|
||||
assoc=2
|
||||
block_size=64
|
||||
compressed_bus=false
|
||||
compression_latency=0
|
||||
do_copy=false
|
||||
hash_delay=1
|
||||
hit_latency=1
|
||||
latency=1
|
||||
lifo=false
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
prefetch_access=false
|
||||
prefetch_cache_check_push=true
|
||||
prefetch_data_accesses_only=false
|
||||
prefetch_degree=1
|
||||
prefetch_latency=10
|
||||
prefetch_miss=false
|
||||
prefetch_past_page=false
|
||||
prefetch_policy=none
|
||||
prefetch_serial_squash=false
|
||||
prefetch_use_cpu_id=true
|
||||
prefetcher_size=100
|
||||
prioritizeRequests=false
|
||||
protocol=Null
|
||||
repl=Null
|
||||
size=262144
|
||||
split=false
|
||||
split_size=0
|
||||
store_compressed=false
|
||||
subblock_size=0
|
||||
tgts_per_mshr=5
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu.dcache_port
|
||||
mem_side=system.cpu.toL2Bus.port[1]
|
||||
|
||||
[system.cpu.fuPool]
|
||||
type=FUPool
|
||||
children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7
|
||||
FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7
|
||||
|
||||
[system.cpu.fuPool.FUList0]
|
||||
type=FUDesc
|
||||
children=opList0
|
||||
count=6
|
||||
opList=system.cpu.fuPool.FUList0.opList0
|
||||
|
||||
[system.cpu.fuPool.FUList0.opList0]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=IntAlu
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList1]
|
||||
type=FUDesc
|
||||
children=opList0 opList1
|
||||
count=2
|
||||
opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
|
||||
|
||||
[system.cpu.fuPool.FUList1.opList0]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=IntMult
|
||||
opLat=3
|
||||
|
||||
[system.cpu.fuPool.FUList1.opList1]
|
||||
type=OpDesc
|
||||
issueLat=19
|
||||
opClass=IntDiv
|
||||
opLat=20
|
||||
|
||||
[system.cpu.fuPool.FUList2]
|
||||
type=FUDesc
|
||||
children=opList0 opList1 opList2
|
||||
count=4
|
||||
opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
|
||||
|
||||
[system.cpu.fuPool.FUList2.opList0]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=FloatAdd
|
||||
opLat=2
|
||||
|
||||
[system.cpu.fuPool.FUList2.opList1]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=FloatCmp
|
||||
opLat=2
|
||||
|
||||
[system.cpu.fuPool.FUList2.opList2]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=FloatCvt
|
||||
opLat=2
|
||||
|
||||
[system.cpu.fuPool.FUList3]
|
||||
type=FUDesc
|
||||
children=opList0 opList1 opList2
|
||||
count=2
|
||||
opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
|
||||
|
||||
[system.cpu.fuPool.FUList3.opList0]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=FloatMult
|
||||
opLat=4
|
||||
|
||||
[system.cpu.fuPool.FUList3.opList1]
|
||||
type=OpDesc
|
||||
issueLat=12
|
||||
opClass=FloatDiv
|
||||
opLat=12
|
||||
|
||||
[system.cpu.fuPool.FUList3.opList2]
|
||||
type=OpDesc
|
||||
issueLat=24
|
||||
opClass=FloatSqrt
|
||||
opLat=24
|
||||
|
||||
[system.cpu.fuPool.FUList4]
|
||||
type=FUDesc
|
||||
children=opList0
|
||||
count=0
|
||||
opList=system.cpu.fuPool.FUList4.opList0
|
||||
|
||||
[system.cpu.fuPool.FUList4.opList0]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=MemRead
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5]
|
||||
type=FUDesc
|
||||
children=opList0
|
||||
count=0
|
||||
opList=system.cpu.fuPool.FUList5.opList0
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList0]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=MemWrite
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList6]
|
||||
type=FUDesc
|
||||
children=opList0 opList1
|
||||
count=4
|
||||
opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1
|
||||
|
||||
[system.cpu.fuPool.FUList6.opList0]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=MemRead
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList6.opList1]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=MemWrite
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList7]
|
||||
type=FUDesc
|
||||
children=opList0
|
||||
count=1
|
||||
opList=system.cpu.fuPool.FUList7.opList0
|
||||
|
||||
[system.cpu.fuPool.FUList7.opList0]
|
||||
type=OpDesc
|
||||
issueLat=3
|
||||
opClass=IprAccess
|
||||
opLat=3
|
||||
|
||||
[system.cpu.icache]
|
||||
type=BaseCache
|
||||
adaptive_compression=false
|
||||
assoc=2
|
||||
block_size=64
|
||||
compressed_bus=false
|
||||
compression_latency=0
|
||||
do_copy=false
|
||||
hash_delay=1
|
||||
hit_latency=1
|
||||
latency=1
|
||||
lifo=false
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
prefetch_access=false
|
||||
prefetch_cache_check_push=true
|
||||
prefetch_data_accesses_only=false
|
||||
prefetch_degree=1
|
||||
prefetch_latency=10
|
||||
prefetch_miss=false
|
||||
prefetch_past_page=false
|
||||
prefetch_policy=none
|
||||
prefetch_serial_squash=false
|
||||
prefetch_use_cpu_id=true
|
||||
prefetcher_size=100
|
||||
prioritizeRequests=false
|
||||
protocol=Null
|
||||
repl=Null
|
||||
size=131072
|
||||
split=false
|
||||
split_size=0
|
||||
store_compressed=false
|
||||
subblock_size=0
|
||||
tgts_per_mshr=5
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu.icache_port
|
||||
mem_side=system.cpu.toL2Bus.port[0]
|
||||
|
||||
[system.cpu.l2cache]
|
||||
type=BaseCache
|
||||
adaptive_compression=false
|
||||
assoc=2
|
||||
block_size=64
|
||||
compressed_bus=false
|
||||
compression_latency=0
|
||||
do_copy=false
|
||||
hash_delay=1
|
||||
hit_latency=1
|
||||
latency=1
|
||||
lifo=false
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
prefetch_access=false
|
||||
prefetch_cache_check_push=true
|
||||
prefetch_data_accesses_only=false
|
||||
prefetch_degree=1
|
||||
prefetch_latency=10
|
||||
prefetch_miss=false
|
||||
prefetch_past_page=false
|
||||
prefetch_policy=none
|
||||
prefetch_serial_squash=false
|
||||
prefetch_use_cpu_id=true
|
||||
prefetcher_size=100
|
||||
prioritizeRequests=false
|
||||
protocol=Null
|
||||
repl=Null
|
||||
size=2097152
|
||||
split=false
|
||||
split_size=0
|
||||
store_compressed=false
|
||||
subblock_size=0
|
||||
tgts_per_mshr=5
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu.toL2Bus.port[2]
|
||||
mem_side=system.membus.port[1]
|
||||
|
||||
[system.cpu.toL2Bus]
|
||||
type=Bus
|
||||
bus_id=0
|
||||
port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
|
||||
dcache_port=system.membus.port[2]
|
||||
icache_port=system.membus.port[1]
|
||||
|
||||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
cmd=hello
|
||||
cmd=bzip2 input.source 1
|
||||
cwd=build/ALPHA_SE/tests/opt/long/60.bzip2/alpha/linux/simple-atomic
|
||||
egid=100
|
||||
env=
|
||||
executable=tests/test-progs/hello/bin/alpha/linux/hello
|
||||
euid=100
|
||||
executable=/dist/m5/cpu2000/binaries/alpha/tru64/bzip2
|
||||
gid=100
|
||||
input=cin
|
||||
output=cout
|
||||
pid=100
|
||||
ppid=99
|
||||
system=system
|
||||
uid=100
|
||||
|
||||
[system.membus]
|
||||
type=Bus
|
||||
bus_id=0
|
||||
port=system.physmem.port system.cpu.l2cache.mem_side
|
||||
clock=1000
|
||||
responder_set=false
|
||||
width=64
|
||||
port=system.physmem.port system.cpu.icache_port system.cpu.dcache_port
|
||||
|
||||
[system.physmem]
|
||||
type=PhysicalMemory
|
||||
|
|
@ -409,6 +104,7 @@ port=system.membus.port[0]
|
|||
|
||||
[trace]
|
||||
bufsize=0
|
||||
cycle=0
|
||||
dump_on_exit=false
|
||||
file=cout
|
||||
flags=
|
||||
|
|
|
|||
|
|
@ -19,345 +19,48 @@ mem_mode=atomic
|
|||
[system.membus]
|
||||
type=Bus
|
||||
bus_id=0
|
||||
clock=1000
|
||||
width=64
|
||||
responder_set=false
|
||||
|
||||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
cmd=hello
|
||||
executable=tests/test-progs/hello/bin/alpha/linux/hello
|
||||
cmd=bzip2 input.source 1
|
||||
executable=/dist/m5/cpu2000/binaries/alpha/tru64/bzip2
|
||||
input=cin
|
||||
output=cout
|
||||
env=
|
||||
cwd=build/ALPHA_SE/tests/opt/long/60.bzip2/alpha/linux/simple-atomic
|
||||
system=system
|
||||
|
||||
[system.cpu.dcache]
|
||||
type=BaseCache
|
||||
size=262144
|
||||
assoc=2
|
||||
block_size=64
|
||||
latency=1
|
||||
mshrs=10
|
||||
tgts_per_mshr=5
|
||||
write_buffers=8
|
||||
prioritizeRequests=false
|
||||
do_copy=false
|
||||
protocol=null
|
||||
trace_addr=0
|
||||
hash_delay=1
|
||||
repl=null
|
||||
compressed_bus=false
|
||||
store_compressed=false
|
||||
adaptive_compression=false
|
||||
compression_latency=0
|
||||
block_size=64
|
||||
max_miss_count=0
|
||||
addr_range=[0,18446744073709551615]
|
||||
split=false
|
||||
split_size=0
|
||||
lifo=false
|
||||
two_queue=false
|
||||
prefetch_miss=false
|
||||
prefetch_access=false
|
||||
prefetcher_size=100
|
||||
prefetch_past_page=false
|
||||
prefetch_serial_squash=false
|
||||
prefetch_latency=10
|
||||
prefetch_degree=1
|
||||
prefetch_policy=none
|
||||
prefetch_cache_check_push=true
|
||||
prefetch_use_cpu_id=true
|
||||
prefetch_data_accesses_only=false
|
||||
hit_latency=1
|
||||
|
||||
[system.cpu.fuPool.FUList0.opList0]
|
||||
type=OpDesc
|
||||
opClass=IntAlu
|
||||
opLat=1
|
||||
issueLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList0]
|
||||
type=FUDesc
|
||||
opList=system.cpu.fuPool.FUList0.opList0
|
||||
count=6
|
||||
|
||||
[system.cpu.fuPool.FUList1.opList0]
|
||||
type=OpDesc
|
||||
opClass=IntMult
|
||||
opLat=3
|
||||
issueLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList1.opList1]
|
||||
type=OpDesc
|
||||
opClass=IntDiv
|
||||
opLat=20
|
||||
issueLat=19
|
||||
|
||||
[system.cpu.fuPool.FUList1]
|
||||
type=FUDesc
|
||||
opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
|
||||
count=2
|
||||
|
||||
[system.cpu.fuPool.FUList2.opList0]
|
||||
type=OpDesc
|
||||
opClass=FloatAdd
|
||||
opLat=2
|
||||
issueLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList2.opList1]
|
||||
type=OpDesc
|
||||
opClass=FloatCmp
|
||||
opLat=2
|
||||
issueLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList2.opList2]
|
||||
type=OpDesc
|
||||
opClass=FloatCvt
|
||||
opLat=2
|
||||
issueLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList2]
|
||||
type=FUDesc
|
||||
opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
|
||||
count=4
|
||||
|
||||
[system.cpu.fuPool.FUList3.opList0]
|
||||
type=OpDesc
|
||||
opClass=FloatMult
|
||||
opLat=4
|
||||
issueLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList3.opList1]
|
||||
type=OpDesc
|
||||
opClass=FloatDiv
|
||||
opLat=12
|
||||
issueLat=12
|
||||
|
||||
[system.cpu.fuPool.FUList3.opList2]
|
||||
type=OpDesc
|
||||
opClass=FloatSqrt
|
||||
opLat=24
|
||||
issueLat=24
|
||||
|
||||
[system.cpu.fuPool.FUList3]
|
||||
type=FUDesc
|
||||
opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
|
||||
count=2
|
||||
|
||||
[system.cpu.fuPool.FUList4.opList0]
|
||||
type=OpDesc
|
||||
opClass=MemRead
|
||||
opLat=1
|
||||
issueLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList4]
|
||||
type=FUDesc
|
||||
opList=system.cpu.fuPool.FUList4.opList0
|
||||
count=0
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList0]
|
||||
type=OpDesc
|
||||
opClass=MemWrite
|
||||
opLat=1
|
||||
issueLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5]
|
||||
type=FUDesc
|
||||
opList=system.cpu.fuPool.FUList5.opList0
|
||||
count=0
|
||||
|
||||
[system.cpu.fuPool.FUList6.opList0]
|
||||
type=OpDesc
|
||||
opClass=MemRead
|
||||
opLat=1
|
||||
issueLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList6.opList1]
|
||||
type=OpDesc
|
||||
opClass=MemWrite
|
||||
opLat=1
|
||||
issueLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList6]
|
||||
type=FUDesc
|
||||
opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1
|
||||
count=4
|
||||
|
||||
[system.cpu.fuPool.FUList7.opList0]
|
||||
type=OpDesc
|
||||
opClass=IprAccess
|
||||
opLat=3
|
||||
issueLat=3
|
||||
|
||||
[system.cpu.fuPool.FUList7]
|
||||
type=FUDesc
|
||||
opList=system.cpu.fuPool.FUList7.opList0
|
||||
count=1
|
||||
|
||||
[system.cpu.fuPool]
|
||||
type=FUPool
|
||||
FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7
|
||||
uid=100
|
||||
euid=100
|
||||
gid=100
|
||||
egid=100
|
||||
pid=100
|
||||
ppid=99
|
||||
|
||||
[system.cpu]
|
||||
type=DerivO3CPU
|
||||
clock=1
|
||||
numThreads=1
|
||||
activity=0
|
||||
workload=system.cpu.workload
|
||||
mem=system.cpu.dcache
|
||||
checker=null
|
||||
type=AtomicSimpleCPU
|
||||
max_insts_any_thread=0
|
||||
max_insts_all_threads=0
|
||||
max_loads_any_thread=0
|
||||
max_loads_all_threads=0
|
||||
cachePorts=200
|
||||
decodeToFetchDelay=1
|
||||
renameToFetchDelay=1
|
||||
iewToFetchDelay=1
|
||||
commitToFetchDelay=1
|
||||
fetchWidth=8
|
||||
renameToDecodeDelay=1
|
||||
iewToDecodeDelay=1
|
||||
commitToDecodeDelay=1
|
||||
fetchToDecodeDelay=1
|
||||
decodeWidth=8
|
||||
iewToRenameDelay=1
|
||||
commitToRenameDelay=1
|
||||
decodeToRenameDelay=1
|
||||
renameWidth=8
|
||||
commitToIEWDelay=1
|
||||
renameToIEWDelay=2
|
||||
issueToExecuteDelay=1
|
||||
dispatchWidth=8
|
||||
issueWidth=8
|
||||
wbWidth=8
|
||||
wbDepth=1
|
||||
fuPool=system.cpu.fuPool
|
||||
iewToCommitDelay=1
|
||||
renameToROBDelay=1
|
||||
commitWidth=8
|
||||
squashWidth=8
|
||||
trapLatency=13
|
||||
backComSize=5
|
||||
forwardComSize=5
|
||||
predType=tournament
|
||||
localPredictorSize=2048
|
||||
localCtrBits=2
|
||||
localHistoryTableSize=2048
|
||||
localHistoryBits=11
|
||||
globalPredictorSize=8192
|
||||
globalCtrBits=2
|
||||
globalHistoryBits=13
|
||||
choicePredictorSize=8192
|
||||
choiceCtrBits=2
|
||||
BTBEntries=4096
|
||||
BTBTagSize=16
|
||||
RASSize=16
|
||||
LQEntries=32
|
||||
SQEntries=32
|
||||
LFSTSize=1024
|
||||
SSITSize=1024
|
||||
numPhysIntRegs=256
|
||||
numPhysFloatRegs=256
|
||||
numIQEntries=64
|
||||
numROBEntries=192
|
||||
smtNumFetchingThreads=1
|
||||
smtFetchPolicy=SingleThread
|
||||
smtLSQPolicy=Partitioned
|
||||
smtLSQThreshold=100
|
||||
smtIQPolicy=Partitioned
|
||||
smtIQThreshold=100
|
||||
smtROBPolicy=Partitioned
|
||||
smtROBThreshold=100
|
||||
smtCommitPolicy=RoundRobin
|
||||
instShiftAmt=2
|
||||
progress_interval=0
|
||||
system=system
|
||||
cpu_id=0
|
||||
workload=system.cpu.workload
|
||||
clock=1
|
||||
phase=0
|
||||
defer_registration=false
|
||||
width=1
|
||||
function_trace=false
|
||||
function_trace_start=0
|
||||
|
||||
[system.cpu.icache]
|
||||
type=BaseCache
|
||||
size=131072
|
||||
assoc=2
|
||||
block_size=64
|
||||
latency=1
|
||||
mshrs=10
|
||||
tgts_per_mshr=5
|
||||
write_buffers=8
|
||||
prioritizeRequests=false
|
||||
do_copy=false
|
||||
protocol=null
|
||||
trace_addr=0
|
||||
hash_delay=1
|
||||
repl=null
|
||||
compressed_bus=false
|
||||
store_compressed=false
|
||||
adaptive_compression=false
|
||||
compression_latency=0
|
||||
block_size=64
|
||||
max_miss_count=0
|
||||
addr_range=[0,18446744073709551615]
|
||||
split=false
|
||||
split_size=0
|
||||
lifo=false
|
||||
two_queue=false
|
||||
prefetch_miss=false
|
||||
prefetch_access=false
|
||||
prefetcher_size=100
|
||||
prefetch_past_page=false
|
||||
prefetch_serial_squash=false
|
||||
prefetch_latency=10
|
||||
prefetch_degree=1
|
||||
prefetch_policy=none
|
||||
prefetch_cache_check_push=true
|
||||
prefetch_use_cpu_id=true
|
||||
prefetch_data_accesses_only=false
|
||||
hit_latency=1
|
||||
|
||||
[system.cpu.l2cache]
|
||||
type=BaseCache
|
||||
size=2097152
|
||||
assoc=2
|
||||
block_size=64
|
||||
latency=1
|
||||
mshrs=10
|
||||
tgts_per_mshr=5
|
||||
write_buffers=8
|
||||
prioritizeRequests=false
|
||||
do_copy=false
|
||||
protocol=null
|
||||
trace_addr=0
|
||||
hash_delay=1
|
||||
repl=null
|
||||
compressed_bus=false
|
||||
store_compressed=false
|
||||
adaptive_compression=false
|
||||
compression_latency=0
|
||||
block_size=64
|
||||
max_miss_count=0
|
||||
addr_range=[0,18446744073709551615]
|
||||
split=false
|
||||
split_size=0
|
||||
lifo=false
|
||||
two_queue=false
|
||||
prefetch_miss=false
|
||||
prefetch_access=false
|
||||
prefetcher_size=100
|
||||
prefetch_past_page=false
|
||||
prefetch_serial_squash=false
|
||||
prefetch_latency=10
|
||||
prefetch_degree=1
|
||||
prefetch_policy=none
|
||||
prefetch_cache_check_push=true
|
||||
prefetch_use_cpu_id=true
|
||||
prefetch_data_accesses_only=false
|
||||
hit_latency=1
|
||||
|
||||
[system.cpu.toL2Bus]
|
||||
type=Bus
|
||||
bus_id=0
|
||||
simulate_stalls=false
|
||||
|
||||
[trace]
|
||||
flags=
|
||||
start=0
|
||||
cycle=0
|
||||
bufsize=0
|
||||
file=cout
|
||||
dump_on_exit=false
|
||||
|
|
@ -396,8 +99,9 @@ print_cpseq=false
|
|||
print_reg_delta=false
|
||||
pc_symbol=true
|
||||
intel_format=false
|
||||
legion_lockstep=false
|
||||
trace_system=client
|
||||
|
||||
[debug]
|
||||
break_cycles=
|
||||
[statsreset]
|
||||
reset_cycle=0
|
||||
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -1,3 +1 @@
|
|||
warn: Entering event queue @ 0. Starting simulation...
|
||||
warn: cycle 0: fault (page_table_fault) detected @ PC 0x000000
|
||||
warn: Increasing stack 0x11ff92000:0x11ff9b000 to 0x11ff90000:0x11ff9b000 because of access to 0x11ff91ff0
|
||||
|
|
|
|||
|
|
@ -1,13 +1,14 @@
|
|||
Hello world!
|
||||
M5 Simulator System
|
||||
|
||||
Copyright (c) 2001-2006
|
||||
The Regents of The University of Michigan
|
||||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Sep 5 2006 15:28:48
|
||||
M5 started Tue Sep 5 15:42:12 2006
|
||||
M5 executing on zizzer.eecs.umich.edu
|
||||
command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/o3-timing tests/run.py quick/00.hello/alpha/linux/o3-timing
|
||||
Exiting @ tick 6870 because target called exit()
|
||||
spec_init
|
||||
Loading Input Data
|
||||
Input data 1048576 bytes in length
|
||||
Compressing Input Data, level 7
|
||||
Compressed data 198546 bytes in length
|
||||
Uncompressing Data
|
||||
Uncompressed data 1048576 bytes in length
|
||||
Uncompressed data compared correctly
|
||||
Compressing Input Data, level 9
|
||||
Compressed data 198677 bytes in length
|
||||
Uncompressing Data
|
||||
Uncompressed data 1048576 bytes in length
|
||||
Uncompressed data compared correctly
|
||||
Tested 1MB buffer: OK!
|
||||
|
|
|
|||
|
|
@ -7,11 +7,9 @@ max_tick=0
|
|||
output_file=cout
|
||||
progress_interval=0
|
||||
|
||||
[debug]
|
||||
break_cycles=
|
||||
|
||||
[exetrace]
|
||||
intel_format=false
|
||||
legion_lockstep=false
|
||||
pc_symbol=true
|
||||
print_cpseq=false
|
||||
print_cycle=true
|
||||
|
|
@ -53,73 +51,20 @@ mem_mode=atomic
|
|||
physmem=system.physmem
|
||||
|
||||
[system.cpu]
|
||||
type=DerivO3CPU
|
||||
children=dcache fuPool icache l2cache toL2Bus workload
|
||||
BTBEntries=4096
|
||||
BTBTagSize=16
|
||||
LFSTSize=1024
|
||||
LQEntries=32
|
||||
RASSize=16
|
||||
SQEntries=32
|
||||
SSITSize=1024
|
||||
activity=0
|
||||
backComSize=5
|
||||
choiceCtrBits=2
|
||||
choicePredictorSize=8192
|
||||
type=TimingSimpleCPU
|
||||
children=dcache icache l2cache toL2Bus workload
|
||||
clock=1
|
||||
commitToDecodeDelay=1
|
||||
commitToFetchDelay=1
|
||||
commitToIEWDelay=1
|
||||
commitToRenameDelay=1
|
||||
commitWidth=8
|
||||
decodeToFetchDelay=1
|
||||
decodeToRenameDelay=1
|
||||
decodeWidth=8
|
||||
cpu_id=0
|
||||
defer_registration=false
|
||||
dispatchWidth=8
|
||||
fetchToDecodeDelay=1
|
||||
fetchTrapLatency=1
|
||||
fetchWidth=8
|
||||
forwardComSize=5
|
||||
fuPool=system.cpu.fuPool
|
||||
function_trace=false
|
||||
function_trace_start=0
|
||||
globalCtrBits=2
|
||||
globalHistoryBits=13
|
||||
globalPredictorSize=8192
|
||||
iewToCommitDelay=1
|
||||
iewToDecodeDelay=1
|
||||
iewToFetchDelay=1
|
||||
iewToRenameDelay=1
|
||||
instShiftAmt=2
|
||||
issueToExecuteDelay=1
|
||||
issueWidth=8
|
||||
localCtrBits=2
|
||||
localHistoryBits=11
|
||||
localHistoryTableSize=2048
|
||||
localPredictorSize=2048
|
||||
max_insts_all_threads=0
|
||||
max_insts_any_thread=0
|
||||
max_loads_all_threads=0
|
||||
max_loads_any_thread=0
|
||||
mem=system.cpu.dcache
|
||||
numIQEntries=64
|
||||
numPhysFloatRegs=256
|
||||
numPhysIntRegs=256
|
||||
numROBEntries=192
|
||||
numRobs=1
|
||||
numThreads=1
|
||||
predType=tournament
|
||||
renameToDecodeDelay=1
|
||||
renameToFetchDelay=1
|
||||
renameToIEWDelay=2
|
||||
renameToROBDelay=1
|
||||
renameWidth=8
|
||||
squashWidth=8
|
||||
phase=0
|
||||
progress_interval=0
|
||||
system=system
|
||||
trapLatency=13
|
||||
wbDepth=1
|
||||
wbWidth=8
|
||||
workload=system.cpu.workload
|
||||
dcache_port=system.cpu.dcache.cpu_side
|
||||
icache_port=system.cpu.icache.cpu_side
|
||||
|
|
@ -131,7 +76,6 @@ assoc=2
|
|||
block_size=64
|
||||
compressed_bus=false
|
||||
compression_latency=0
|
||||
do_copy=false
|
||||
hash_delay=1
|
||||
hit_latency=1
|
||||
latency=1
|
||||
|
|
@ -164,143 +108,6 @@ write_buffers=8
|
|||
cpu_side=system.cpu.dcache_port
|
||||
mem_side=system.cpu.toL2Bus.port[1]
|
||||
|
||||
[system.cpu.fuPool]
|
||||
type=FUPool
|
||||
children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7
|
||||
FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7
|
||||
|
||||
[system.cpu.fuPool.FUList0]
|
||||
type=FUDesc
|
||||
children=opList0
|
||||
count=6
|
||||
opList=system.cpu.fuPool.FUList0.opList0
|
||||
|
||||
[system.cpu.fuPool.FUList0.opList0]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=IntAlu
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList1]
|
||||
type=FUDesc
|
||||
children=opList0 opList1
|
||||
count=2
|
||||
opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
|
||||
|
||||
[system.cpu.fuPool.FUList1.opList0]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=IntMult
|
||||
opLat=3
|
||||
|
||||
[system.cpu.fuPool.FUList1.opList1]
|
||||
type=OpDesc
|
||||
issueLat=19
|
||||
opClass=IntDiv
|
||||
opLat=20
|
||||
|
||||
[system.cpu.fuPool.FUList2]
|
||||
type=FUDesc
|
||||
children=opList0 opList1 opList2
|
||||
count=4
|
||||
opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
|
||||
|
||||
[system.cpu.fuPool.FUList2.opList0]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=FloatAdd
|
||||
opLat=2
|
||||
|
||||
[system.cpu.fuPool.FUList2.opList1]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=FloatCmp
|
||||
opLat=2
|
||||
|
||||
[system.cpu.fuPool.FUList2.opList2]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=FloatCvt
|
||||
opLat=2
|
||||
|
||||
[system.cpu.fuPool.FUList3]
|
||||
type=FUDesc
|
||||
children=opList0 opList1 opList2
|
||||
count=2
|
||||
opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
|
||||
|
||||
[system.cpu.fuPool.FUList3.opList0]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=FloatMult
|
||||
opLat=4
|
||||
|
||||
[system.cpu.fuPool.FUList3.opList1]
|
||||
type=OpDesc
|
||||
issueLat=12
|
||||
opClass=FloatDiv
|
||||
opLat=12
|
||||
|
||||
[system.cpu.fuPool.FUList3.opList2]
|
||||
type=OpDesc
|
||||
issueLat=24
|
||||
opClass=FloatSqrt
|
||||
opLat=24
|
||||
|
||||
[system.cpu.fuPool.FUList4]
|
||||
type=FUDesc
|
||||
children=opList0
|
||||
count=0
|
||||
opList=system.cpu.fuPool.FUList4.opList0
|
||||
|
||||
[system.cpu.fuPool.FUList4.opList0]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=MemRead
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5]
|
||||
type=FUDesc
|
||||
children=opList0
|
||||
count=0
|
||||
opList=system.cpu.fuPool.FUList5.opList0
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList0]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=MemWrite
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList6]
|
||||
type=FUDesc
|
||||
children=opList0 opList1
|
||||
count=4
|
||||
opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1
|
||||
|
||||
[system.cpu.fuPool.FUList6.opList0]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=MemRead
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList6.opList1]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=MemWrite
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList7]
|
||||
type=FUDesc
|
||||
children=opList0
|
||||
count=1
|
||||
opList=system.cpu.fuPool.FUList7.opList0
|
||||
|
||||
[system.cpu.fuPool.FUList7.opList0]
|
||||
type=OpDesc
|
||||
issueLat=3
|
||||
opClass=IprAccess
|
||||
opLat=3
|
||||
|
||||
[system.cpu.icache]
|
||||
type=BaseCache
|
||||
adaptive_compression=false
|
||||
|
|
@ -308,7 +115,6 @@ assoc=2
|
|||
block_size=64
|
||||
compressed_bus=false
|
||||
compression_latency=0
|
||||
do_copy=false
|
||||
hash_delay=1
|
||||
hit_latency=1
|
||||
latency=1
|
||||
|
|
@ -348,7 +154,6 @@ assoc=2
|
|||
block_size=64
|
||||
compressed_bus=false
|
||||
compression_latency=0
|
||||
do_copy=false
|
||||
hash_delay=1
|
||||
hit_latency=1
|
||||
latency=1
|
||||
|
|
@ -384,20 +189,33 @@ mem_side=system.membus.port[1]
|
|||
[system.cpu.toL2Bus]
|
||||
type=Bus
|
||||
bus_id=0
|
||||
clock=1000
|
||||
responder_set=false
|
||||
width=64
|
||||
port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
|
||||
|
||||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
cmd=hello
|
||||
cmd=bzip2 input.source 1
|
||||
cwd=build/ALPHA_SE/tests/opt/long/60.bzip2/alpha/linux/simple-timing
|
||||
egid=100
|
||||
env=
|
||||
executable=tests/test-progs/hello/bin/alpha/linux/hello
|
||||
euid=100
|
||||
executable=/dist/m5/cpu2000/binaries/alpha/tru64/bzip2
|
||||
gid=100
|
||||
input=cin
|
||||
output=cout
|
||||
pid=100
|
||||
ppid=99
|
||||
system=system
|
||||
uid=100
|
||||
|
||||
[system.membus]
|
||||
type=Bus
|
||||
bus_id=0
|
||||
clock=1000
|
||||
responder_set=false
|
||||
width=64
|
||||
port=system.physmem.port system.cpu.l2cache.mem_side
|
||||
|
||||
[system.physmem]
|
||||
|
|
@ -409,6 +227,7 @@ port=system.membus.port[0]
|
|||
|
||||
[trace]
|
||||
bufsize=0
|
||||
cycle=0
|
||||
dump_on_exit=false
|
||||
file=cout
|
||||
flags=
|
||||
|
|
|
|||
|
|
@ -19,19 +19,54 @@ mem_mode=atomic
|
|||
[system.membus]
|
||||
type=Bus
|
||||
bus_id=0
|
||||
clock=1000
|
||||
width=64
|
||||
responder_set=false
|
||||
|
||||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
cmd=hello
|
||||
executable=tests/test-progs/hello/bin/alpha/linux/hello
|
||||
cmd=bzip2 input.source 1
|
||||
executable=/dist/m5/cpu2000/binaries/alpha/tru64/bzip2
|
||||
input=cin
|
||||
output=cout
|
||||
env=
|
||||
cwd=build/ALPHA_SE/tests/opt/long/60.bzip2/alpha/linux/simple-timing
|
||||
system=system
|
||||
uid=100
|
||||
euid=100
|
||||
gid=100
|
||||
egid=100
|
||||
pid=100
|
||||
ppid=99
|
||||
|
||||
[system.cpu.dcache]
|
||||
[system.cpu]
|
||||
type=TimingSimpleCPU
|
||||
max_insts_any_thread=0
|
||||
max_insts_all_threads=0
|
||||
max_loads_any_thread=0
|
||||
max_loads_all_threads=0
|
||||
progress_interval=0
|
||||
system=system
|
||||
cpu_id=0
|
||||
workload=system.cpu.workload
|
||||
clock=1
|
||||
phase=0
|
||||
defer_registration=false
|
||||
// width not specified
|
||||
function_trace=false
|
||||
function_trace_start=0
|
||||
// simulate_stalls not specified
|
||||
|
||||
[system.cpu.toL2Bus]
|
||||
type=Bus
|
||||
bus_id=0
|
||||
clock=1000
|
||||
width=64
|
||||
responder_set=false
|
||||
|
||||
[system.cpu.icache]
|
||||
type=BaseCache
|
||||
size=262144
|
||||
size=131072
|
||||
assoc=2
|
||||
block_size=64
|
||||
latency=1
|
||||
|
|
@ -39,7 +74,6 @@ mshrs=10
|
|||
tgts_per_mshr=5
|
||||
write_buffers=8
|
||||
prioritizeRequests=false
|
||||
do_copy=false
|
||||
protocol=null
|
||||
trace_addr=0
|
||||
hash_delay=1
|
||||
|
|
@ -68,214 +102,9 @@ prefetch_use_cpu_id=true
|
|||
prefetch_data_accesses_only=false
|
||||
hit_latency=1
|
||||
|
||||
[system.cpu.fuPool.FUList0.opList0]
|
||||
type=OpDesc
|
||||
opClass=IntAlu
|
||||
opLat=1
|
||||
issueLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList0]
|
||||
type=FUDesc
|
||||
opList=system.cpu.fuPool.FUList0.opList0
|
||||
count=6
|
||||
|
||||
[system.cpu.fuPool.FUList1.opList0]
|
||||
type=OpDesc
|
||||
opClass=IntMult
|
||||
opLat=3
|
||||
issueLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList1.opList1]
|
||||
type=OpDesc
|
||||
opClass=IntDiv
|
||||
opLat=20
|
||||
issueLat=19
|
||||
|
||||
[system.cpu.fuPool.FUList1]
|
||||
type=FUDesc
|
||||
opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
|
||||
count=2
|
||||
|
||||
[system.cpu.fuPool.FUList2.opList0]
|
||||
type=OpDesc
|
||||
opClass=FloatAdd
|
||||
opLat=2
|
||||
issueLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList2.opList1]
|
||||
type=OpDesc
|
||||
opClass=FloatCmp
|
||||
opLat=2
|
||||
issueLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList2.opList2]
|
||||
type=OpDesc
|
||||
opClass=FloatCvt
|
||||
opLat=2
|
||||
issueLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList2]
|
||||
type=FUDesc
|
||||
opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
|
||||
count=4
|
||||
|
||||
[system.cpu.fuPool.FUList3.opList0]
|
||||
type=OpDesc
|
||||
opClass=FloatMult
|
||||
opLat=4
|
||||
issueLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList3.opList1]
|
||||
type=OpDesc
|
||||
opClass=FloatDiv
|
||||
opLat=12
|
||||
issueLat=12
|
||||
|
||||
[system.cpu.fuPool.FUList3.opList2]
|
||||
type=OpDesc
|
||||
opClass=FloatSqrt
|
||||
opLat=24
|
||||
issueLat=24
|
||||
|
||||
[system.cpu.fuPool.FUList3]
|
||||
type=FUDesc
|
||||
opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
|
||||
count=2
|
||||
|
||||
[system.cpu.fuPool.FUList4.opList0]
|
||||
type=OpDesc
|
||||
opClass=MemRead
|
||||
opLat=1
|
||||
issueLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList4]
|
||||
type=FUDesc
|
||||
opList=system.cpu.fuPool.FUList4.opList0
|
||||
count=0
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList0]
|
||||
type=OpDesc
|
||||
opClass=MemWrite
|
||||
opLat=1
|
||||
issueLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5]
|
||||
type=FUDesc
|
||||
opList=system.cpu.fuPool.FUList5.opList0
|
||||
count=0
|
||||
|
||||
[system.cpu.fuPool.FUList6.opList0]
|
||||
type=OpDesc
|
||||
opClass=MemRead
|
||||
opLat=1
|
||||
issueLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList6.opList1]
|
||||
type=OpDesc
|
||||
opClass=MemWrite
|
||||
opLat=1
|
||||
issueLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList6]
|
||||
type=FUDesc
|
||||
opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1
|
||||
count=4
|
||||
|
||||
[system.cpu.fuPool.FUList7.opList0]
|
||||
type=OpDesc
|
||||
opClass=IprAccess
|
||||
opLat=3
|
||||
issueLat=3
|
||||
|
||||
[system.cpu.fuPool.FUList7]
|
||||
type=FUDesc
|
||||
opList=system.cpu.fuPool.FUList7.opList0
|
||||
count=1
|
||||
|
||||
[system.cpu.fuPool]
|
||||
type=FUPool
|
||||
FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7
|
||||
|
||||
[system.cpu]
|
||||
type=DerivO3CPU
|
||||
clock=1
|
||||
numThreads=1
|
||||
activity=0
|
||||
workload=system.cpu.workload
|
||||
mem=system.cpu.dcache
|
||||
checker=null
|
||||
max_insts_any_thread=0
|
||||
max_insts_all_threads=0
|
||||
max_loads_any_thread=0
|
||||
max_loads_all_threads=0
|
||||
cachePorts=200
|
||||
decodeToFetchDelay=1
|
||||
renameToFetchDelay=1
|
||||
iewToFetchDelay=1
|
||||
commitToFetchDelay=1
|
||||
fetchWidth=8
|
||||
renameToDecodeDelay=1
|
||||
iewToDecodeDelay=1
|
||||
commitToDecodeDelay=1
|
||||
fetchToDecodeDelay=1
|
||||
decodeWidth=8
|
||||
iewToRenameDelay=1
|
||||
commitToRenameDelay=1
|
||||
decodeToRenameDelay=1
|
||||
renameWidth=8
|
||||
commitToIEWDelay=1
|
||||
renameToIEWDelay=2
|
||||
issueToExecuteDelay=1
|
||||
dispatchWidth=8
|
||||
issueWidth=8
|
||||
wbWidth=8
|
||||
wbDepth=1
|
||||
fuPool=system.cpu.fuPool
|
||||
iewToCommitDelay=1
|
||||
renameToROBDelay=1
|
||||
commitWidth=8
|
||||
squashWidth=8
|
||||
trapLatency=13
|
||||
backComSize=5
|
||||
forwardComSize=5
|
||||
predType=tournament
|
||||
localPredictorSize=2048
|
||||
localCtrBits=2
|
||||
localHistoryTableSize=2048
|
||||
localHistoryBits=11
|
||||
globalPredictorSize=8192
|
||||
globalCtrBits=2
|
||||
globalHistoryBits=13
|
||||
choicePredictorSize=8192
|
||||
choiceCtrBits=2
|
||||
BTBEntries=4096
|
||||
BTBTagSize=16
|
||||
RASSize=16
|
||||
LQEntries=32
|
||||
SQEntries=32
|
||||
LFSTSize=1024
|
||||
SSITSize=1024
|
||||
numPhysIntRegs=256
|
||||
numPhysFloatRegs=256
|
||||
numIQEntries=64
|
||||
numROBEntries=192
|
||||
smtNumFetchingThreads=1
|
||||
smtFetchPolicy=SingleThread
|
||||
smtLSQPolicy=Partitioned
|
||||
smtLSQThreshold=100
|
||||
smtIQPolicy=Partitioned
|
||||
smtIQThreshold=100
|
||||
smtROBPolicy=Partitioned
|
||||
smtROBThreshold=100
|
||||
smtCommitPolicy=RoundRobin
|
||||
instShiftAmt=2
|
||||
defer_registration=false
|
||||
function_trace=false
|
||||
function_trace_start=0
|
||||
|
||||
[system.cpu.icache]
|
||||
[system.cpu.dcache]
|
||||
type=BaseCache
|
||||
size=131072
|
||||
size=262144
|
||||
assoc=2
|
||||
block_size=64
|
||||
latency=1
|
||||
|
|
@ -283,7 +112,6 @@ mshrs=10
|
|||
tgts_per_mshr=5
|
||||
write_buffers=8
|
||||
prioritizeRequests=false
|
||||
do_copy=false
|
||||
protocol=null
|
||||
trace_addr=0
|
||||
hash_delay=1
|
||||
|
|
@ -322,7 +150,6 @@ mshrs=10
|
|||
tgts_per_mshr=5
|
||||
write_buffers=8
|
||||
prioritizeRequests=false
|
||||
do_copy=false
|
||||
protocol=null
|
||||
trace_addr=0
|
||||
hash_delay=1
|
||||
|
|
@ -351,13 +178,10 @@ prefetch_use_cpu_id=true
|
|||
prefetch_data_accesses_only=false
|
||||
hit_latency=1
|
||||
|
||||
[system.cpu.toL2Bus]
|
||||
type=Bus
|
||||
bus_id=0
|
||||
|
||||
[trace]
|
||||
flags=
|
||||
start=0
|
||||
cycle=0
|
||||
bufsize=0
|
||||
file=cout
|
||||
dump_on_exit=false
|
||||
|
|
@ -396,8 +220,9 @@ print_cpseq=false
|
|||
print_reg_delta=false
|
||||
pc_symbol=true
|
||||
intel_format=false
|
||||
legion_lockstep=false
|
||||
trace_system=client
|
||||
|
||||
[debug]
|
||||
break_cycles=
|
||||
[statsreset]
|
||||
reset_cycle=0
|
||||
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -1,3 +1 @@
|
|||
warn: Entering event queue @ 0. Starting simulation...
|
||||
warn: cycle 0: fault (page_table_fault) detected @ PC 0x000000
|
||||
warn: Increasing stack 0x11ff92000:0x11ff9b000 to 0x11ff90000:0x11ff9b000 because of access to 0x11ff91ff0
|
||||
|
|
|
|||
|
|
@ -1,13 +1,14 @@
|
|||
Hello world!
|
||||
M5 Simulator System
|
||||
|
||||
Copyright (c) 2001-2006
|
||||
The Regents of The University of Michigan
|
||||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Sep 5 2006 15:28:48
|
||||
M5 started Tue Sep 5 15:42:12 2006
|
||||
M5 executing on zizzer.eecs.umich.edu
|
||||
command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/o3-timing tests/run.py quick/00.hello/alpha/linux/o3-timing
|
||||
Exiting @ tick 6870 because target called exit()
|
||||
spec_init
|
||||
Loading Input Data
|
||||
Input data 1048576 bytes in length
|
||||
Compressing Input Data, level 7
|
||||
Compressed data 198546 bytes in length
|
||||
Uncompressing Data
|
||||
Uncompressed data 1048576 bytes in length
|
||||
Uncompressed data compared correctly
|
||||
Compressing Input Data, level 9
|
||||
Compressed data 198677 bytes in length
|
||||
Uncompressing Data
|
||||
Uncompressed data 1048576 bytes in length
|
||||
Uncompressed data compared correctly
|
||||
Tested 1MB buffer: OK!
|
||||
|
|
|
|||
|
|
@ -7,11 +7,9 @@ max_tick=0
|
|||
output_file=cout
|
||||
progress_interval=0
|
||||
|
||||
[debug]
|
||||
break_cycles=
|
||||
|
||||
[exetrace]
|
||||
intel_format=false
|
||||
legion_lockstep=false
|
||||
pc_symbol=true
|
||||
print_cpseq=false
|
||||
print_cycle=true
|
||||
|
|
@ -102,14 +100,15 @@ max_insts_all_threads=0
|
|||
max_insts_any_thread=0
|
||||
max_loads_all_threads=0
|
||||
max_loads_any_thread=0
|
||||
mem=system.cpu.dcache
|
||||
numIQEntries=64
|
||||
numPhysFloatRegs=256
|
||||
numPhysIntRegs=256
|
||||
numROBEntries=192
|
||||
numRobs=1
|
||||
numThreads=1
|
||||
phase=0
|
||||
predType=tournament
|
||||
progress_interval=0
|
||||
renameToDecodeDelay=1
|
||||
renameToFetchDelay=1
|
||||
renameToIEWDelay=2
|
||||
|
|
@ -131,7 +130,6 @@ assoc=2
|
|||
block_size=64
|
||||
compressed_bus=false
|
||||
compression_latency=0
|
||||
do_copy=false
|
||||
hash_delay=1
|
||||
hit_latency=1
|
||||
latency=1
|
||||
|
|
@ -308,7 +306,6 @@ assoc=2
|
|||
block_size=64
|
||||
compressed_bus=false
|
||||
compression_latency=0
|
||||
do_copy=false
|
||||
hash_delay=1
|
||||
hit_latency=1
|
||||
latency=1
|
||||
|
|
@ -348,7 +345,6 @@ assoc=2
|
|||
block_size=64
|
||||
compressed_bus=false
|
||||
compression_latency=0
|
||||
do_copy=false
|
||||
hash_delay=1
|
||||
hit_latency=1
|
||||
latency=1
|
||||
|
|
@ -384,20 +380,33 @@ mem_side=system.membus.port[1]
|
|||
[system.cpu.toL2Bus]
|
||||
type=Bus
|
||||
bus_id=0
|
||||
clock=1000
|
||||
responder_set=false
|
||||
width=64
|
||||
port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
|
||||
|
||||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
cmd=hello
|
||||
cmd=twolf smred
|
||||
cwd=build/ALPHA_SE/tests/opt/long/70.twolf/alpha/linux/o3-timing
|
||||
egid=100
|
||||
env=
|
||||
executable=tests/test-progs/hello/bin/alpha/linux/hello
|
||||
euid=100
|
||||
executable=/dist/m5/cpu2000/binaries/alpha/tru64/twolf
|
||||
gid=100
|
||||
input=cin
|
||||
output=cout
|
||||
pid=100
|
||||
ppid=99
|
||||
system=system
|
||||
uid=100
|
||||
|
||||
[system.membus]
|
||||
type=Bus
|
||||
bus_id=0
|
||||
clock=1000
|
||||
responder_set=false
|
||||
width=64
|
||||
port=system.physmem.port system.cpu.l2cache.mem_side
|
||||
|
||||
[system.physmem]
|
||||
|
|
@ -409,6 +418,7 @@ port=system.membus.port[0]
|
|||
|
||||
[trace]
|
||||
bufsize=0
|
||||
cycle=0
|
||||
dump_on_exit=false
|
||||
file=cout
|
||||
flags=
|
||||
|
|
|
|||
|
|
@ -19,54 +19,25 @@ mem_mode=atomic
|
|||
[system.membus]
|
||||
type=Bus
|
||||
bus_id=0
|
||||
clock=1000
|
||||
width=64
|
||||
responder_set=false
|
||||
|
||||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
cmd=hello
|
||||
executable=tests/test-progs/hello/bin/alpha/linux/hello
|
||||
cmd=twolf smred
|
||||
executable=/dist/m5/cpu2000/binaries/alpha/tru64/twolf
|
||||
input=cin
|
||||
output=cout
|
||||
env=
|
||||
cwd=build/ALPHA_SE/tests/opt/long/70.twolf/alpha/linux/o3-timing
|
||||
system=system
|
||||
|
||||
[system.cpu.dcache]
|
||||
type=BaseCache
|
||||
size=262144
|
||||
assoc=2
|
||||
block_size=64
|
||||
latency=1
|
||||
mshrs=10
|
||||
tgts_per_mshr=5
|
||||
write_buffers=8
|
||||
prioritizeRequests=false
|
||||
do_copy=false
|
||||
protocol=null
|
||||
trace_addr=0
|
||||
hash_delay=1
|
||||
repl=null
|
||||
compressed_bus=false
|
||||
store_compressed=false
|
||||
adaptive_compression=false
|
||||
compression_latency=0
|
||||
block_size=64
|
||||
max_miss_count=0
|
||||
addr_range=[0,18446744073709551615]
|
||||
split=false
|
||||
split_size=0
|
||||
lifo=false
|
||||
two_queue=false
|
||||
prefetch_miss=false
|
||||
prefetch_access=false
|
||||
prefetcher_size=100
|
||||
prefetch_past_page=false
|
||||
prefetch_serial_squash=false
|
||||
prefetch_latency=10
|
||||
prefetch_degree=1
|
||||
prefetch_policy=none
|
||||
prefetch_cache_check_push=true
|
||||
prefetch_use_cpu_id=true
|
||||
prefetch_data_accesses_only=false
|
||||
hit_latency=1
|
||||
uid=100
|
||||
euid=100
|
||||
gid=100
|
||||
egid=100
|
||||
pid=100
|
||||
ppid=99
|
||||
|
||||
[system.cpu.fuPool.FUList0.opList0]
|
||||
type=OpDesc
|
||||
|
|
@ -199,15 +170,16 @@ FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUL
|
|||
[system.cpu]
|
||||
type=DerivO3CPU
|
||||
clock=1
|
||||
phase=0
|
||||
numThreads=1
|
||||
activity=0
|
||||
workload=system.cpu.workload
|
||||
mem=system.cpu.dcache
|
||||
checker=null
|
||||
max_insts_any_thread=0
|
||||
max_insts_all_threads=0
|
||||
max_loads_any_thread=0
|
||||
max_loads_all_threads=0
|
||||
progress_interval=0
|
||||
cachePorts=200
|
||||
decodeToFetchDelay=1
|
||||
renameToFetchDelay=1
|
||||
|
|
@ -283,7 +255,44 @@ mshrs=10
|
|||
tgts_per_mshr=5
|
||||
write_buffers=8
|
||||
prioritizeRequests=false
|
||||
do_copy=false
|
||||
protocol=null
|
||||
trace_addr=0
|
||||
hash_delay=1
|
||||
repl=null
|
||||
compressed_bus=false
|
||||
store_compressed=false
|
||||
adaptive_compression=false
|
||||
compression_latency=0
|
||||
block_size=64
|
||||
max_miss_count=0
|
||||
addr_range=[0,18446744073709551615]
|
||||
split=false
|
||||
split_size=0
|
||||
lifo=false
|
||||
two_queue=false
|
||||
prefetch_miss=false
|
||||
prefetch_access=false
|
||||
prefetcher_size=100
|
||||
prefetch_past_page=false
|
||||
prefetch_serial_squash=false
|
||||
prefetch_latency=10
|
||||
prefetch_degree=1
|
||||
prefetch_policy=none
|
||||
prefetch_cache_check_push=true
|
||||
prefetch_use_cpu_id=true
|
||||
prefetch_data_accesses_only=false
|
||||
hit_latency=1
|
||||
|
||||
[system.cpu.dcache]
|
||||
type=BaseCache
|
||||
size=262144
|
||||
assoc=2
|
||||
block_size=64
|
||||
latency=1
|
||||
mshrs=10
|
||||
tgts_per_mshr=5
|
||||
write_buffers=8
|
||||
prioritizeRequests=false
|
||||
protocol=null
|
||||
trace_addr=0
|
||||
hash_delay=1
|
||||
|
|
@ -322,7 +331,6 @@ mshrs=10
|
|||
tgts_per_mshr=5
|
||||
write_buffers=8
|
||||
prioritizeRequests=false
|
||||
do_copy=false
|
||||
protocol=null
|
||||
trace_addr=0
|
||||
hash_delay=1
|
||||
|
|
@ -354,10 +362,14 @@ hit_latency=1
|
|||
[system.cpu.toL2Bus]
|
||||
type=Bus
|
||||
bus_id=0
|
||||
clock=1000
|
||||
width=64
|
||||
responder_set=false
|
||||
|
||||
[trace]
|
||||
flags=
|
||||
start=0
|
||||
cycle=0
|
||||
bufsize=0
|
||||
file=cout
|
||||
dump_on_exit=false
|
||||
|
|
@ -396,8 +408,9 @@ print_cpseq=false
|
|||
print_reg_delta=false
|
||||
pc_symbol=true
|
||||
intel_format=false
|
||||
legion_lockstep=false
|
||||
trace_system=client
|
||||
|
||||
[debug]
|
||||
break_cycles=
|
||||
[statsreset]
|
||||
reset_cycle=0
|
||||
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
276
tests/long/70.twolf/ref/alpha/linux/o3-timing/smred.out
Normal file
276
tests/long/70.twolf/ref/alpha/linux/o3-timing/smred.out
Normal file
|
|
@ -0,0 +1,276 @@
|
|||
|
||||
TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988
|
||||
Standard Cell Placement and Global Routing Program
|
||||
Authors: Carl Sechen, Bill Swartz
|
||||
Yale University
|
||||
|
||||
|
||||
NOTE: Restart file .rs2 not used
|
||||
|
||||
TimberWolf will perform a global route step
|
||||
rowSep: 1.000000
|
||||
feedThruWidth: 4
|
||||
|
||||
******************
|
||||
BLOCK DATA
|
||||
block:1 desire:85
|
||||
block:2 desire:85
|
||||
Total Desired Length: 170
|
||||
total cell length: 168
|
||||
total block length: 168
|
||||
block x-span:84 block y-span:78
|
||||
implicit feed thru range: -84
|
||||
Using default value of bin.penalty.control:1.000000
|
||||
numBins automatically set to:5
|
||||
binWidth = average_cell_width + 0 sigma= 17
|
||||
average_cell_width is:16
|
||||
standard deviation of cell length is:23.6305
|
||||
TimberWolfSC starting from the beginning
|
||||
|
||||
|
||||
|
||||
THIS IS THE ROUTE COST OF THE ORIGINAL PLACEMENT: 645
|
||||
The number of nets with 1 pin is 4
|
||||
The number of nets with 2 pin is 9
|
||||
The number of nets with 3 pin is 0
|
||||
The number of nets with 4 pin is 2
|
||||
The number of nets with 5 pin is 0
|
||||
The number of nets with 6 pin is 0
|
||||
The number of nets with 7 pin is 0
|
||||
The number of nets with 8 pin is 0
|
||||
The number of nets with 9 pin is 0
|
||||
The number of nets with 10 pin or more is 0
|
||||
|
||||
New Cost Function: Initial Horizontal Cost:242
|
||||
New Cost Function: FEEDS:0 MISSING_ROWS:-46
|
||||
|
||||
bdxlen:86 bdylen:78
|
||||
l:0 t:78 r:86 b:0
|
||||
|
||||
|
||||
|
||||
THIS IS THE ROUTE COST OF THE CURRENT PLACEMENT: 645
|
||||
|
||||
|
||||
|
||||
THIS IS THE PENALTY OF THE CURRENT PLACEMENT: 44
|
||||
|
||||
The rand generator seed was at utemp() : 1
|
||||
|
||||
|
||||
tempfile[0][0] = 0.982500 tempfile[0][1] = 90.000000
|
||||
tempfile[1][0] = 0.915000 tempfile[1][1] = 20.000000
|
||||
tempfile[2][0] = 0.700000 tempfile[2][1] = 10.000000
|
||||
tempfile[3][0] = 0.100000 tempfile[3][1] = 0.000000
|
||||
|
||||
I T fds Wire Penalty P_lim Epct binC rowC acc s/p early FDs MRs
|
||||
1 500 0 929 592 160 30.0 1.0 3.0 84.2 34.7 0.0 0 40
|
||||
2 491 0 876 106 726 0.0 0.8 2.5 80.0 18.5 0.0 0 46
|
||||
3 482 0 822 273 372 0.0 0.5 1.5 80.8 21.2 0.0 0 46
|
||||
4 474 0 826 53 247 0.0 0.5 0.9 65.0 21.9 0.0 0 48
|
||||
5 465 8 987 73 190 0.0 0.5 0.5 50.0 38.3 0.0 0 46
|
||||
6 457 8 851 67 226 0.0 0.5 0.5 53.8 42.9 0.0 0 52
|
||||
7 449 8 1067 108 190 0.0 0.5 0.5 46.2 53.8 0.0 0 50
|
||||
8 441 8 918 106 171 0.0 0.5 0.5 47.1 40.4 0.0 0 48
|
||||
9 434 8 812 101 197 0.0 0.5 0.5 53.6 21.0 0.0 0 48
|
||||
10 426 8 1038 121 181 0.0 0.5 0.5 43.6 27.1 0.0 0 48
|
||||
11 419 8 898 93 187 0.0 0.5 0.5 45.3 47.8 0.0 0 50
|
||||
12 411 4 857 94 240 0.0 0.5 0.5 62.7 51.6 0.0 0 44
|
||||
13 404 8 1043 88 185 0.0 0.5 0.5 54.0 52.8 0.0 0 50
|
||||
14 397 8 767 94 154 0.0 0.5 0.5 33.8 35.0 0.0 0 50
|
||||
15 390 8 862 89 183 0.0 0.5 0.5 55.6 29.0 0.0 0 46
|
||||
16 383 4 798 79 173 0.0 0.5 0.5 57.5 35.3 0.0 0 52
|
||||
17 376 8 827 100 152 0.0 0.5 0.5 35.3 81.8 0.0 0 50
|
||||
18 370 8 878 101 208 0.0 0.5 0.5 44.7 46.2 0.0 0 48
|
||||
19 363 4 921 67 167 0.0 0.5 0.5 57.1 34.7 0.0 0 48
|
||||
20 357 8 933 93 154 0.0 0.5 0.5 46.5 43.6 0.0 0 52
|
||||
21 351 8 930 89 147 0.0 0.5 0.5 39.4 36.5 0.0 0 52
|
||||
22 345 8 951 79 142 0.0 0.5 0.5 32.8 51.3 0.0 0 50
|
||||
23 339 8 1046 87 207 0.0 0.5 0.5 52.8 61.0 0.0 0 48
|
||||
24 333 4 989 96 185 0.0 0.5 0.5 45.3 43.3 0.0 0 42
|
||||
25 327 4 577 86 157 0.0 0.5 0.5 31.1 55.3 0.0 0 52
|
||||
26 321 8 776 97 174 0.0 0.5 0.5 47.9 62.5 0.0 0 52
|
||||
27 315 8 850 81 188 0.0 0.5 0.5 45.0 55.2 0.0 0 50
|
||||
28 310 8 898 97 148 0.0 0.5 0.5 43.0 45.8 0.0 0 48
|
||||
29 304 8 889 65 173 0.0 0.5 0.5 32.5 41.3 0.0 0 50
|
||||
30 299 8 858 81 153 0.0 0.5 0.5 44.3 29.2 0.0 0 46
|
||||
31 294 8 871 82 187 0.0 0.5 0.5 45.7 47.7 0.0 0 48
|
||||
32 289 8 782 109 173 0.0 0.5 0.5 35.2 57.4 0.0 0 48
|
||||
33 284 8 743 98 189 0.0 0.6 0.5 41.8 64.3 0.0 0 52
|
||||
34 279 8 943 90 147 0.0 0.5 0.5 38.6 32.8 0.0 0 48
|
||||
35 274 8 907 57 166 0.0 0.5 0.5 33.6 51.0 0.0 0 48
|
||||
36 269 8 900 70 148 0.0 0.5 0.5 45.0 41.4 0.0 0 50
|
||||
37 264 4 875 106 133 0.0 0.5 0.5 31.7 55.3 0.0 0 52
|
||||
38 260 8 1023 145 149 0.0 0.6 0.5 28.7 65.0 0.0 0 52
|
||||
39 255 8 801 151 173 0.0 0.9 0.5 41.7 41.2 0.0 0 48
|
||||
40 251 8 741 104 159 0.0 0.8 0.5 36.2 47.5 0.0 0 48
|
||||
41 246 8 828 108 149 0.0 0.5 0.5 34.6 50.9 0.0 0 50
|
||||
42 242 8 947 128 132 0.0 0.7 0.5 34.2 39.0 0.0 0 50
|
||||
43 238 8 917 101 142 0.0 0.8 0.5 34.4 50.9 0.0 0 48
|
||||
44 234 8 761 86 129 0.0 0.5 0.5 42.0 36.4 0.0 0 52
|
||||
45 229 8 979 106 137 0.0 0.5 0.5 29.2 55.3 0.0 0 50
|
||||
46 225 8 806 74 130 0.0 0.7 0.5 33.1 65.4 0.0 0 52
|
||||
47 221 8 971 125 114 0.0 0.5 0.5 31.9 45.6 0.0 0 52
|
||||
48 218 8 869 125 104 0.0 0.9 0.5 30.0 56.0 0.0 0 48
|
||||
49 214 8 999 153 140 0.0 0.8 0.5 30.4 46.4 0.0 0 52
|
||||
50 210 8 798 192 139 0.0 1.0 0.5 28.9 50.0 0.0 0 52
|
||||
51 206 8 860 125 157 0.0 1.2 0.5 31.5 26.9 0.0 0 52
|
||||
52 203 8 893 186 127 5.9 0.9 0.5 26.4 42.3 0.0 0 46
|
||||
53 199 8 863 126 141 0.0 1.2 0.5 32.5 44.4 0.0 0 44
|
||||
54 196 8 788 97 133 0.0 0.9 0.5 37.5 40.0 0.0 0 50
|
||||
55 192 8 926 119 116 0.0 0.6 0.5 26.1 55.3 0.0 0 52
|
||||
56 189 8 789 162 107 0.0 0.8 0.5 25.2 40.4 0.0 0 48
|
||||
57 186 8 878 107 128 0.0 1.1 0.5 23.1 34.0 0.0 0 52
|
||||
58 182 8 775 105 122 0.0 0.8 0.5 25.5 57.4 0.0 0 50
|
||||
59 179 8 747 94 129 0.0 0.7 0.5 34.3 37.3 0.0 0 50
|
||||
60 176 8 845 96 138 0.0 0.6 0.5 28.3 41.7 0.0 0 52
|
||||
61 173 8 961 121 110 0.0 0.6 0.5 29.0 52.6 0.0 0 48
|
||||
62 170 4 911 110 109 0.0 0.9 0.5 33.5 33.3 0.0 0 48
|
||||
63 167 8 656 109 109 0.0 0.8 0.5 21.9 44.7 0.0 0 52
|
||||
64 164 8 934 117 105 0.0 0.8 0.5 15.5 50.0 0.0 0 52
|
||||
65 161 8 972 125 95 0.0 0.8 0.5 24.4 50.0 0.0 0 50
|
||||
66 158 8 894 125 101 0.0 0.9 0.5 27.2 35.9 0.0 0 52
|
||||
67 155 8 798 146 129 0.0 1.0 0.5 22.8 58.7 0.0 0 52
|
||||
68 153 8 901 183 92 0.0 1.1 0.5 23.6 34.5 0.0 0 52
|
||||
69 150 8 977 197 103 0.0 1.4 0.5 23.6 36.8 0.0 0 52
|
||||
70 147 8 905 262 93 0.0 1.5 0.5 20.3 63.4 0.0 0 52
|
||||
71 145 8 995 148 122 0.0 1.9 0.5 20.9 35.3 0.0 0 52
|
||||
72 142 8 934 230 99 0.0 1.6 0.5 20.0 65.9 0.0 0 52
|
||||
73 140 8 862 173 100 0.0 1.8 0.5 26.8 46.8 0.0 0 52
|
||||
74 137 8 924 139 90 0.0 1.7 0.5 16.8 42.5 0.0 0 52
|
||||
75 135 8 888 168 113 0.0 1.6 0.5 22.9 40.4 0.0 0 52
|
||||
76 133 8 712 212 84 0.0 1.6 0.5 13.4 46.9 0.0 0 52
|
||||
77 130 8 868 210 91 0.0 1.7 0.5 17.7 51.2 0.0 0 52
|
||||
78 128 8 952 307 92 0.0 1.9 0.5 19.7 44.9 0.0 0 50
|
||||
79 126 8 801 157 107 0.0 2.2 0.5 15.8 39.0 0.0 0 52
|
||||
80 123 8 849 147 93 0.0 2.1 0.5 15.6 51.4 0.0 0 52
|
||||
81 121 8 799 154 86 0.0 1.9 0.5 12.2 50.0 0.0 0 52
|
||||
82 119 8 941 213 82 0.0 1.8 0.5 19.5 41.2 0.0 0 50
|
||||
83 117 8 751 268 94 0.0 2.0 0.5 20.8 42.6 0.0 0 50
|
||||
84 115 8 828 198 102 0.0 2.2 0.5 15.5 59.5 0.0 0 52
|
||||
85 113 8 898 266 123 0.0 2.2 0.5 13.2 85.2 0.0 0 52
|
||||
86 111 8 943 190 93 0.0 2.4 0.5 19.5 45.1 0.0 0 52
|
||||
87 109 8 864 183 65 0.0 2.4 0.5 14.9 31.8 0.0 0 52
|
||||
88 107 8 793 203 93 0.0 2.4 0.5 11.8 35.3 0.0 0 52
|
||||
89 105 8 752 162 74 1.2 2.4 0.5 13.1 21.4 0.0 0 52
|
||||
90 103 8 801 149 77 0.0 2.3 0.5 9.7 58.3 0.0 0 52
|
||||
91 102 8 901 230 99 0.0 2.2 0.5 16.0 25.5 0.0 0 52
|
||||
92 100 8 826 201 87 0.0 2.4 0.5 12.8 45.7 0.0 0 52
|
||||
93 98 8 810 196 83 0.0 2.5 0.5 14.0 24.4 0.0 0 52
|
||||
94 96 8 857 209 68 1.0 2.5 0.5 11.5 27.0 5.1 0 52
|
||||
95 95 8 771 174 91 0.0 2.6 0.5 10.5 26.5 0.0 0 52
|
||||
96 93 8 955 210 59 0.0 2.6 0.5 10.0 36.7 0.7 0 52
|
||||
97 91 8 833 206 53 0.0 2.7 0.5 10.2 19.4 1.4 0 52
|
||||
98 90 8 888 229 86 0.0 2.8 0.5 8.1 36.0 0.0 0 52
|
||||
99 88 8 794 186 91 1.0 2.9 0.5 8.3 25.0 0.5 0 52
|
||||
100 81 8 756 170 72 1.0 2.9 0.5 6.0 23.8 7.0 0 52
|
||||
101 74 8 791 176 67 0.0 2.9 0.5 4.4 58.3 4.0 0 52
|
||||
102 67 8 813 213 43 0.0 3.0 0.5 7.0 150.0 4.2 0 52
|
||||
103 62 8 779 245 39 0.0 3.1 0.5 3.2 16.7 13.0 0 52
|
||||
104 56 8 767 303 63 0.0 3.2 0.5 4.1 20.0 0.7 0 52
|
||||
105 52 8 757 270 57 0.0 3.5 0.5 6.4 3.7 0.5 0 52
|
||||
106 47 8 763 283 41 0.0 3.7 0.5 4.5 0.0 0.0 0 52
|
||||
107 43 8 768 283 36 0.0 3.7 0.5 2.9 18.2 3.6 0 52
|
||||
108 39 8 804 283 25 0.0 3.7 0.5 3.1 0.0 6.2 0 52
|
||||
109 36 8 781 283 24 0.0 3.7 0.5 3.6 6.7 6.7 0 52
|
||||
110 33 8 738 298 42 0.0 3.7 0.5 3.3 15.4 3.5 0 52
|
||||
111 30 8 761 298 36 0.0 3.7 0.5 2.2 0.0 4.3 0 52
|
||||
112 27 8 769 298 37 0.0 3.7 0.5 0.9 0.0 2.2 0 52
|
||||
113 25 8 745 298 31 0.0 3.7 0.5 1.5 0.0 6.6 0 52
|
||||
114 23 8 753 298 16 0.0 3.7 0.5 1.3 0.0 2.8 0 52
|
||||
115 21 8 745 298 11 0.0 3.7 0.5 1.5 0.0 14.0 0 52
|
||||
116 19 8 747 298 21 0.0 3.7 0.5 2.1 0.0 5.8 0 52
|
||||
117 13 8 737 298 12 0.0 3.7 0.5 1.0 0.0 10.0 0 52
|
||||
118 9 8 736 298 4 0.0 3.7 0.5 1.5 0.0 18.5 0 52
|
||||
119 0 8 739 298 0 0.0 3.7 0.5 1.8 0.0 18.0 0 52
|
||||
120 0 8 732 298 0 0.0 3.7 0.5 1.2 0.0 21.8 0 52
|
||||
121 0 8 732 19 -1 0.0 0.0 0.5 0.0 100.0 54.8
|
||||
|
||||
Initial Wiring Cost: 645 Final Wiring Cost: 732
|
||||
############## Percent Wire Cost Reduction: -13
|
||||
|
||||
|
||||
Initial Wire Length: 645 Final Wire Length: 732
|
||||
************** Percent Wire Length Reduction: -13
|
||||
|
||||
|
||||
Initial Horiz. Wire: 216 Final Horiz. Wire: 147
|
||||
$$$$$$$$$$$ Percent H-Wire Length Reduction: 32
|
||||
|
||||
|
||||
Initial Vert. Wire: 429 Final Vert. Wire: 585
|
||||
@@@@@@@@@@@ Percent V-Wire Length Reduction: -36
|
||||
|
||||
Before Feeds are Added:
|
||||
BLOCK TOTAL CELL LENGTHS OVER/UNDER TARGET
|
||||
1 82 -20
|
||||
2 86 -16
|
||||
|
||||
LONGEST Block is:2 Its length is:86
|
||||
BLOCK TOTAL CELL LENGTHS OVER/UNDER TARGET
|
||||
1 86 -16
|
||||
2 86 -16
|
||||
|
||||
LONGEST Block is:1 Its length is:86
|
||||
Added: 1 feed-through cells
|
||||
|
||||
Removed the cell overlaps --- Will do neighbor interchanges only now
|
||||
|
||||
TOTAL INTERCONNECT LENGTH: 994
|
||||
OVERLAP PENALTY: 0
|
||||
|
||||
initialRowControl: 1.650
|
||||
finalRowControl: 0.300
|
||||
iter T Wire accept
|
||||
122 0.001 976 16%
|
||||
123 0.001 971 0%
|
||||
124 0.001 971 0%
|
||||
Total Feed-Alignment Movement (Pass 1): 0
|
||||
Total Feed-Alignment Movement (Pass 2): 0
|
||||
Total Feed-Alignment Movement (Pass 3): 0
|
||||
Total Feed-Alignment Movement (Pass 4): 0
|
||||
Total Feed-Alignment Movement (Pass 5): 0
|
||||
Total Feed-Alignment Movement (Pass 6): 0
|
||||
Total Feed-Alignment Movement (Pass 7): 0
|
||||
Total Feed-Alignment Movement (Pass 8): 0
|
||||
|
||||
The rand generator seed was at globroute() : 987654321
|
||||
|
||||
|
||||
Total Number of Net Segments: 9
|
||||
Number of Switchable Net Segments: 0
|
||||
|
||||
Number of channels: 3
|
||||
|
||||
|
||||
|
||||
THIS IS THE ORIGINAL NUMBER OF TRACKS: 5
|
||||
|
||||
|
||||
no. of accepted flips: 0
|
||||
no. of attempted flips: 0
|
||||
THIS IS THE NUMBER OF TRACKS: 5
|
||||
|
||||
|
||||
|
||||
FINAL NUMBER OF ROUTING TRACKS: 5
|
||||
|
||||
MAX OF CHANNEL: 1 is: 0
|
||||
MAX OF CHANNEL: 2 is: 4
|
||||
MAX OF CHANNEL: 3 is: 1
|
||||
FINAL TOTAL INTERCONNECT LENGTH: 978
|
||||
FINAL OVERLAP PENALTY: 0 FINAL VALUE OF TOTAL COST IS: 978
|
||||
MAX NUMBER OF ATTEMPTED FLIPS PER T: 55
|
||||
|
||||
|
||||
cost_scale_factor:3.90616
|
||||
|
||||
Number of Feed Thrus: 0
|
||||
Number of Implicit Feed Thrus: 0
|
||||
|
||||
Statistics:
|
||||
Number of Standard Cells: 10
|
||||
Number of Pads: 0
|
||||
Number of Nets: 15
|
||||
Number of Pins: 46
|
||||
Usage statistics not available
|
||||
17
tests/long/70.twolf/ref/alpha/linux/o3-timing/smred.pin
Normal file
17
tests/long/70.twolf/ref/alpha/linux/o3-timing/smred.pin
Normal file
|
|
@ -0,0 +1,17 @@
|
|||
$COUNT_1/$AND2_1/$ND2_1$Z 1 $COUNT_1/$AND2_1/$ND2_1 00#Z 17 52 2 1 0
|
||||
$COUNT_1/$AND2_1/$ND2_1$Z 1 ACOUNT_1 00#A 15 26 2 -1 0
|
||||
B7 2 $COUNT_1/$FJK3_2 00#K 25 78 3 -1 0
|
||||
B7 2 $COUNT_1/$FJK3_2 00#J 23 78 3 -1 0
|
||||
B7 3 $COUNT_1/$AND2_2/$ND2_1 00#A 9 26 2 -1 0
|
||||
B7 3 ACOUNT_1 01#Z 17 26 2 -1 0
|
||||
B6 5 $COUNT_1/$FJK3_1 00#K 25 26 2 -1 0
|
||||
B6 5 $COUNT_1/$FJK3_1 00#J 23 26 2 -1 0
|
||||
B6 5 $COUNT_1/$AND2_3/$IV_1 01#Z 7 26 2 -1 0
|
||||
$COUNT_1/$FJK3_1$Q 6 $COUNT_1/$FJK3_1 01#Q 81 26 2 -1 0
|
||||
$COUNT_1/$FJK3_1$Q 6 $COUNT_1/$AND2_1/$ND2_1 00#B 19 52 2 1 0
|
||||
$COUNT_1/$FJK3_2$Q 7 $COUNT_1/$FJK3_2 00#Q 81 52 2 1 0
|
||||
$COUNT_1/$FJK3_2$Q 7 $COUNT_1/$AND2_2/$ND2_1 01#B 11 26 2 -1 0
|
||||
$COUNT_1/$AND2_3/$ND2_1$Z 8 $COUNT_1/$AND2_3/$ND2_1 00#Z 5 52 2 1 0
|
||||
$COUNT_1/$AND2_3/$ND2_1$Z 8 $COUNT_1/$AND2_3/$IV_1 00#A 5 26 2 -1 0
|
||||
$COUNT_1/$AND2_4/$ND2_1$Z 9 $COUNT_1/$AND2_4/$ND2_1 00#Z 7 52 2 1 0
|
||||
$COUNT_1/$AND2_4/$ND2_1$Z 9 $COUNT_1/$AND2_4/$IV_1 00#A 3 26 2 -1 0
|
||||
11
tests/long/70.twolf/ref/alpha/linux/o3-timing/smred.pl1
Normal file
11
tests/long/70.twolf/ref/alpha/linux/o3-timing/smred.pl1
Normal file
|
|
@ -0,0 +1,11 @@
|
|||
$COUNT_1/$AND2_4/$IV_1 0 0 4 26 0 1
|
||||
$COUNT_1/$AND2_3/$IV_1 4 0 8 26 2 1
|
||||
$COUNT_1/$AND2_2/$ND2_1 8 0 14 26 0 1
|
||||
ACOUNT_1 14 0 18 26 2 1
|
||||
twfeed1 18 0 22 26 0 1
|
||||
$COUNT_1/$FJK3_1 22 0 86 26 0 1
|
||||
$COUNT_1/$AND2_3/$ND2_1 0 52 6 78 0 2
|
||||
$COUNT_1/$AND2_4/$ND2_1 6 52 12 78 2 2
|
||||
$COUNT_1/$AND2_2/$IV_1 12 52 16 78 2 2
|
||||
$COUNT_1/$AND2_1/$ND2_1 16 52 22 78 2 2
|
||||
$COUNT_1/$FJK3_2 22 52 86 78 0 2
|
||||
2
tests/long/70.twolf/ref/alpha/linux/o3-timing/smred.pl2
Normal file
2
tests/long/70.twolf/ref/alpha/linux/o3-timing/smred.pl2
Normal file
|
|
@ -0,0 +1,2 @@
|
|||
1 0 0 86 26 0 0
|
||||
2 0 52 86 78 0 0
|
||||
18
tests/long/70.twolf/ref/alpha/linux/o3-timing/smred.sav
Normal file
18
tests/long/70.twolf/ref/alpha/linux/o3-timing/smred.sav
Normal file
|
|
@ -0,0 +1,18 @@
|
|||
0.009592
|
||||
121
|
||||
0
|
||||
1
|
||||
0.000000
|
||||
0.500000
|
||||
3.906156
|
||||
1
|
||||
1 1 2 37 13
|
||||
2 2 0 34 65
|
||||
3 2 2 63 65
|
||||
4 1 0 59 13
|
||||
5 1 2 32 13
|
||||
6 2 0 23 65
|
||||
7 1 2 12 13
|
||||
8 2 0 6 65
|
||||
9 1 0 70 13
|
||||
10 2 0 70 65
|
||||
19
tests/long/70.twolf/ref/alpha/linux/o3-timing/smred.sv2
Normal file
19
tests/long/70.twolf/ref/alpha/linux/o3-timing/smred.sv2
Normal file
|
|
@ -0,0 +1,19 @@
|
|||
0.001000
|
||||
123
|
||||
0
|
||||
2
|
||||
0.000000
|
||||
0.500000
|
||||
3.906156
|
||||
1
|
||||
1 1 2 16 13
|
||||
2 2 2 19 65
|
||||
3 2 2 14 65
|
||||
4 1 0 11 13
|
||||
5 1 2 6 13
|
||||
6 2 0 3 65
|
||||
7 1 0 2 13
|
||||
8 2 2 9 65
|
||||
9 1 0 50 13
|
||||
10 2 0 54 65
|
||||
11 1 0 84 13
|
||||
29
tests/long/70.twolf/ref/alpha/linux/o3-timing/smred.twf
Normal file
29
tests/long/70.twolf/ref/alpha/linux/o3-timing/smred.twf
Normal file
|
|
@ -0,0 +1,29 @@
|
|||
net 1
|
||||
segment channel 2
|
||||
pin1 1 pin2 7 0 0
|
||||
net 2
|
||||
segment channel 3
|
||||
pin1 41 pin2 42 0 0
|
||||
segment channel 2
|
||||
pin1 12 pin2 3 0 0
|
||||
net 3
|
||||
segment channel 2
|
||||
pin1 35 pin2 36 0 0
|
||||
segment channel 2
|
||||
pin1 19 pin2 35 0 0
|
||||
net 4
|
||||
segment channel 2
|
||||
pin1 5 pin2 38 0 0
|
||||
net 5
|
||||
net 7
|
||||
segment channel 2
|
||||
pin1 14 pin2 43 0 0
|
||||
net 8
|
||||
segment channel 2
|
||||
pin1 23 pin2 17 0 0
|
||||
net 9
|
||||
net 11
|
||||
segment channel 2
|
||||
pin1 25 pin2 31 0 0
|
||||
net 14
|
||||
net 15
|
||||
|
|
@ -1,3 +1 @@
|
|||
warn: Entering event queue @ 0. Starting simulation...
|
||||
warn: cycle 0: fault (page_table_fault) detected @ PC 0x000000
|
||||
warn: Increasing stack 0x11ff92000:0x11ff9b000 to 0x11ff90000:0x11ff9b000 because of access to 0x11ff91ff0
|
||||
|
|
|
|||
|
|
@ -1,13 +1,14 @@
|
|||
Hello world!
|
||||
M5 Simulator System
|
||||
|
||||
Copyright (c) 2001-2006
|
||||
The Regents of The University of Michigan
|
||||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Sep 5 2006 15:28:48
|
||||
M5 started Tue Sep 5 15:42:12 2006
|
||||
M5 executing on zizzer.eecs.umich.edu
|
||||
command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/o3-timing tests/run.py quick/00.hello/alpha/linux/o3-timing
|
||||
Exiting @ tick 6870 because target called exit()
|
||||
TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988
|
||||
Standard Cell Placement and Global Routing Program
|
||||
Authors: Carl Sechen, Bill Swartz
|
||||
Yale University
|
||||
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
|
||||
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
|
||||
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45
|
||||
46 47 48 49 50 51 52 53 54 55 56 57 58 59 60
|
||||
61 62 63 64 65 66 67 68 69 70 71 72 73 74 75
|
||||
76 77 78 79 80 81 82 83 84 85 86 87 88 89 90
|
||||
91 92 93 94 95 96 97 98 99 100 101 102 103 104 105
|
||||
106 107 108 109 110 111 112 113 114 115 116 117 118 119 120
|
||||
122 123 124
|
||||
|
|
@ -7,11 +7,9 @@ max_tick=0
|
|||
output_file=cout
|
||||
progress_interval=0
|
||||
|
||||
[debug]
|
||||
break_cycles=
|
||||
|
||||
[exetrace]
|
||||
intel_format=false
|
||||
legion_lockstep=false
|
||||
pc_symbol=true
|
||||
print_cpseq=false
|
||||
print_cycle=true
|
||||
|
|
@ -53,352 +51,49 @@ mem_mode=atomic
|
|||
physmem=system.physmem
|
||||
|
||||
[system.cpu]
|
||||
type=DerivO3CPU
|
||||
children=dcache fuPool icache l2cache toL2Bus workload
|
||||
BTBEntries=4096
|
||||
BTBTagSize=16
|
||||
LFSTSize=1024
|
||||
LQEntries=32
|
||||
RASSize=16
|
||||
SQEntries=32
|
||||
SSITSize=1024
|
||||
activity=0
|
||||
backComSize=5
|
||||
choiceCtrBits=2
|
||||
choicePredictorSize=8192
|
||||
type=AtomicSimpleCPU
|
||||
children=workload
|
||||
clock=1
|
||||
commitToDecodeDelay=1
|
||||
commitToFetchDelay=1
|
||||
commitToIEWDelay=1
|
||||
commitToRenameDelay=1
|
||||
commitWidth=8
|
||||
decodeToFetchDelay=1
|
||||
decodeToRenameDelay=1
|
||||
decodeWidth=8
|
||||
cpu_id=0
|
||||
defer_registration=false
|
||||
dispatchWidth=8
|
||||
fetchToDecodeDelay=1
|
||||
fetchTrapLatency=1
|
||||
fetchWidth=8
|
||||
forwardComSize=5
|
||||
fuPool=system.cpu.fuPool
|
||||
function_trace=false
|
||||
function_trace_start=0
|
||||
globalCtrBits=2
|
||||
globalHistoryBits=13
|
||||
globalPredictorSize=8192
|
||||
iewToCommitDelay=1
|
||||
iewToDecodeDelay=1
|
||||
iewToFetchDelay=1
|
||||
iewToRenameDelay=1
|
||||
instShiftAmt=2
|
||||
issueToExecuteDelay=1
|
||||
issueWidth=8
|
||||
localCtrBits=2
|
||||
localHistoryBits=11
|
||||
localHistoryTableSize=2048
|
||||
localPredictorSize=2048
|
||||
max_insts_all_threads=0
|
||||
max_insts_any_thread=0
|
||||
max_loads_all_threads=0
|
||||
max_loads_any_thread=0
|
||||
mem=system.cpu.dcache
|
||||
numIQEntries=64
|
||||
numPhysFloatRegs=256
|
||||
numPhysIntRegs=256
|
||||
numROBEntries=192
|
||||
numRobs=1
|
||||
numThreads=1
|
||||
predType=tournament
|
||||
renameToDecodeDelay=1
|
||||
renameToFetchDelay=1
|
||||
renameToIEWDelay=2
|
||||
renameToROBDelay=1
|
||||
renameWidth=8
|
||||
squashWidth=8
|
||||
phase=0
|
||||
progress_interval=0
|
||||
simulate_stalls=false
|
||||
system=system
|
||||
trapLatency=13
|
||||
wbDepth=1
|
||||
wbWidth=8
|
||||
width=1
|
||||
workload=system.cpu.workload
|
||||
dcache_port=system.cpu.dcache.cpu_side
|
||||
icache_port=system.cpu.icache.cpu_side
|
||||
|
||||
[system.cpu.dcache]
|
||||
type=BaseCache
|
||||
adaptive_compression=false
|
||||
assoc=2
|
||||
block_size=64
|
||||
compressed_bus=false
|
||||
compression_latency=0
|
||||
do_copy=false
|
||||
hash_delay=1
|
||||
hit_latency=1
|
||||
latency=1
|
||||
lifo=false
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
prefetch_access=false
|
||||
prefetch_cache_check_push=true
|
||||
prefetch_data_accesses_only=false
|
||||
prefetch_degree=1
|
||||
prefetch_latency=10
|
||||
prefetch_miss=false
|
||||
prefetch_past_page=false
|
||||
prefetch_policy=none
|
||||
prefetch_serial_squash=false
|
||||
prefetch_use_cpu_id=true
|
||||
prefetcher_size=100
|
||||
prioritizeRequests=false
|
||||
protocol=Null
|
||||
repl=Null
|
||||
size=262144
|
||||
split=false
|
||||
split_size=0
|
||||
store_compressed=false
|
||||
subblock_size=0
|
||||
tgts_per_mshr=5
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu.dcache_port
|
||||
mem_side=system.cpu.toL2Bus.port[1]
|
||||
|
||||
[system.cpu.fuPool]
|
||||
type=FUPool
|
||||
children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7
|
||||
FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7
|
||||
|
||||
[system.cpu.fuPool.FUList0]
|
||||
type=FUDesc
|
||||
children=opList0
|
||||
count=6
|
||||
opList=system.cpu.fuPool.FUList0.opList0
|
||||
|
||||
[system.cpu.fuPool.FUList0.opList0]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=IntAlu
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList1]
|
||||
type=FUDesc
|
||||
children=opList0 opList1
|
||||
count=2
|
||||
opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
|
||||
|
||||
[system.cpu.fuPool.FUList1.opList0]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=IntMult
|
||||
opLat=3
|
||||
|
||||
[system.cpu.fuPool.FUList1.opList1]
|
||||
type=OpDesc
|
||||
issueLat=19
|
||||
opClass=IntDiv
|
||||
opLat=20
|
||||
|
||||
[system.cpu.fuPool.FUList2]
|
||||
type=FUDesc
|
||||
children=opList0 opList1 opList2
|
||||
count=4
|
||||
opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
|
||||
|
||||
[system.cpu.fuPool.FUList2.opList0]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=FloatAdd
|
||||
opLat=2
|
||||
|
||||
[system.cpu.fuPool.FUList2.opList1]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=FloatCmp
|
||||
opLat=2
|
||||
|
||||
[system.cpu.fuPool.FUList2.opList2]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=FloatCvt
|
||||
opLat=2
|
||||
|
||||
[system.cpu.fuPool.FUList3]
|
||||
type=FUDesc
|
||||
children=opList0 opList1 opList2
|
||||
count=2
|
||||
opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
|
||||
|
||||
[system.cpu.fuPool.FUList3.opList0]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=FloatMult
|
||||
opLat=4
|
||||
|
||||
[system.cpu.fuPool.FUList3.opList1]
|
||||
type=OpDesc
|
||||
issueLat=12
|
||||
opClass=FloatDiv
|
||||
opLat=12
|
||||
|
||||
[system.cpu.fuPool.FUList3.opList2]
|
||||
type=OpDesc
|
||||
issueLat=24
|
||||
opClass=FloatSqrt
|
||||
opLat=24
|
||||
|
||||
[system.cpu.fuPool.FUList4]
|
||||
type=FUDesc
|
||||
children=opList0
|
||||
count=0
|
||||
opList=system.cpu.fuPool.FUList4.opList0
|
||||
|
||||
[system.cpu.fuPool.FUList4.opList0]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=MemRead
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5]
|
||||
type=FUDesc
|
||||
children=opList0
|
||||
count=0
|
||||
opList=system.cpu.fuPool.FUList5.opList0
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList0]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=MemWrite
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList6]
|
||||
type=FUDesc
|
||||
children=opList0 opList1
|
||||
count=4
|
||||
opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1
|
||||
|
||||
[system.cpu.fuPool.FUList6.opList0]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=MemRead
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList6.opList1]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=MemWrite
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList7]
|
||||
type=FUDesc
|
||||
children=opList0
|
||||
count=1
|
||||
opList=system.cpu.fuPool.FUList7.opList0
|
||||
|
||||
[system.cpu.fuPool.FUList7.opList0]
|
||||
type=OpDesc
|
||||
issueLat=3
|
||||
opClass=IprAccess
|
||||
opLat=3
|
||||
|
||||
[system.cpu.icache]
|
||||
type=BaseCache
|
||||
adaptive_compression=false
|
||||
assoc=2
|
||||
block_size=64
|
||||
compressed_bus=false
|
||||
compression_latency=0
|
||||
do_copy=false
|
||||
hash_delay=1
|
||||
hit_latency=1
|
||||
latency=1
|
||||
lifo=false
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
prefetch_access=false
|
||||
prefetch_cache_check_push=true
|
||||
prefetch_data_accesses_only=false
|
||||
prefetch_degree=1
|
||||
prefetch_latency=10
|
||||
prefetch_miss=false
|
||||
prefetch_past_page=false
|
||||
prefetch_policy=none
|
||||
prefetch_serial_squash=false
|
||||
prefetch_use_cpu_id=true
|
||||
prefetcher_size=100
|
||||
prioritizeRequests=false
|
||||
protocol=Null
|
||||
repl=Null
|
||||
size=131072
|
||||
split=false
|
||||
split_size=0
|
||||
store_compressed=false
|
||||
subblock_size=0
|
||||
tgts_per_mshr=5
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu.icache_port
|
||||
mem_side=system.cpu.toL2Bus.port[0]
|
||||
|
||||
[system.cpu.l2cache]
|
||||
type=BaseCache
|
||||
adaptive_compression=false
|
||||
assoc=2
|
||||
block_size=64
|
||||
compressed_bus=false
|
||||
compression_latency=0
|
||||
do_copy=false
|
||||
hash_delay=1
|
||||
hit_latency=1
|
||||
latency=1
|
||||
lifo=false
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
prefetch_access=false
|
||||
prefetch_cache_check_push=true
|
||||
prefetch_data_accesses_only=false
|
||||
prefetch_degree=1
|
||||
prefetch_latency=10
|
||||
prefetch_miss=false
|
||||
prefetch_past_page=false
|
||||
prefetch_policy=none
|
||||
prefetch_serial_squash=false
|
||||
prefetch_use_cpu_id=true
|
||||
prefetcher_size=100
|
||||
prioritizeRequests=false
|
||||
protocol=Null
|
||||
repl=Null
|
||||
size=2097152
|
||||
split=false
|
||||
split_size=0
|
||||
store_compressed=false
|
||||
subblock_size=0
|
||||
tgts_per_mshr=5
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu.toL2Bus.port[2]
|
||||
mem_side=system.membus.port[1]
|
||||
|
||||
[system.cpu.toL2Bus]
|
||||
type=Bus
|
||||
bus_id=0
|
||||
port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
|
||||
dcache_port=system.membus.port[2]
|
||||
icache_port=system.membus.port[1]
|
||||
|
||||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
cmd=hello
|
||||
cmd=twolf smred
|
||||
cwd=build/ALPHA_SE/tests/opt/long/70.twolf/alpha/linux/simple-atomic
|
||||
egid=100
|
||||
env=
|
||||
executable=tests/test-progs/hello/bin/alpha/linux/hello
|
||||
euid=100
|
||||
executable=/dist/m5/cpu2000/binaries/alpha/tru64/twolf
|
||||
gid=100
|
||||
input=cin
|
||||
output=cout
|
||||
pid=100
|
||||
ppid=99
|
||||
system=system
|
||||
uid=100
|
||||
|
||||
[system.membus]
|
||||
type=Bus
|
||||
bus_id=0
|
||||
port=system.physmem.port system.cpu.l2cache.mem_side
|
||||
clock=1000
|
||||
responder_set=false
|
||||
width=64
|
||||
port=system.physmem.port system.cpu.icache_port system.cpu.dcache_port
|
||||
|
||||
[system.physmem]
|
||||
type=PhysicalMemory
|
||||
|
|
@ -409,6 +104,7 @@ port=system.membus.port[0]
|
|||
|
||||
[trace]
|
||||
bufsize=0
|
||||
cycle=0
|
||||
dump_on_exit=false
|
||||
file=cout
|
||||
flags=
|
||||
|
|
|
|||
|
|
@ -19,345 +19,48 @@ mem_mode=atomic
|
|||
[system.membus]
|
||||
type=Bus
|
||||
bus_id=0
|
||||
clock=1000
|
||||
width=64
|
||||
responder_set=false
|
||||
|
||||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
cmd=hello
|
||||
executable=tests/test-progs/hello/bin/alpha/linux/hello
|
||||
cmd=twolf smred
|
||||
executable=/dist/m5/cpu2000/binaries/alpha/tru64/twolf
|
||||
input=cin
|
||||
output=cout
|
||||
env=
|
||||
cwd=build/ALPHA_SE/tests/opt/long/70.twolf/alpha/linux/simple-atomic
|
||||
system=system
|
||||
|
||||
[system.cpu.dcache]
|
||||
type=BaseCache
|
||||
size=262144
|
||||
assoc=2
|
||||
block_size=64
|
||||
latency=1
|
||||
mshrs=10
|
||||
tgts_per_mshr=5
|
||||
write_buffers=8
|
||||
prioritizeRequests=false
|
||||
do_copy=false
|
||||
protocol=null
|
||||
trace_addr=0
|
||||
hash_delay=1
|
||||
repl=null
|
||||
compressed_bus=false
|
||||
store_compressed=false
|
||||
adaptive_compression=false
|
||||
compression_latency=0
|
||||
block_size=64
|
||||
max_miss_count=0
|
||||
addr_range=[0,18446744073709551615]
|
||||
split=false
|
||||
split_size=0
|
||||
lifo=false
|
||||
two_queue=false
|
||||
prefetch_miss=false
|
||||
prefetch_access=false
|
||||
prefetcher_size=100
|
||||
prefetch_past_page=false
|
||||
prefetch_serial_squash=false
|
||||
prefetch_latency=10
|
||||
prefetch_degree=1
|
||||
prefetch_policy=none
|
||||
prefetch_cache_check_push=true
|
||||
prefetch_use_cpu_id=true
|
||||
prefetch_data_accesses_only=false
|
||||
hit_latency=1
|
||||
|
||||
[system.cpu.fuPool.FUList0.opList0]
|
||||
type=OpDesc
|
||||
opClass=IntAlu
|
||||
opLat=1
|
||||
issueLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList0]
|
||||
type=FUDesc
|
||||
opList=system.cpu.fuPool.FUList0.opList0
|
||||
count=6
|
||||
|
||||
[system.cpu.fuPool.FUList1.opList0]
|
||||
type=OpDesc
|
||||
opClass=IntMult
|
||||
opLat=3
|
||||
issueLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList1.opList1]
|
||||
type=OpDesc
|
||||
opClass=IntDiv
|
||||
opLat=20
|
||||
issueLat=19
|
||||
|
||||
[system.cpu.fuPool.FUList1]
|
||||
type=FUDesc
|
||||
opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
|
||||
count=2
|
||||
|
||||
[system.cpu.fuPool.FUList2.opList0]
|
||||
type=OpDesc
|
||||
opClass=FloatAdd
|
||||
opLat=2
|
||||
issueLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList2.opList1]
|
||||
type=OpDesc
|
||||
opClass=FloatCmp
|
||||
opLat=2
|
||||
issueLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList2.opList2]
|
||||
type=OpDesc
|
||||
opClass=FloatCvt
|
||||
opLat=2
|
||||
issueLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList2]
|
||||
type=FUDesc
|
||||
opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
|
||||
count=4
|
||||
|
||||
[system.cpu.fuPool.FUList3.opList0]
|
||||
type=OpDesc
|
||||
opClass=FloatMult
|
||||
opLat=4
|
||||
issueLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList3.opList1]
|
||||
type=OpDesc
|
||||
opClass=FloatDiv
|
||||
opLat=12
|
||||
issueLat=12
|
||||
|
||||
[system.cpu.fuPool.FUList3.opList2]
|
||||
type=OpDesc
|
||||
opClass=FloatSqrt
|
||||
opLat=24
|
||||
issueLat=24
|
||||
|
||||
[system.cpu.fuPool.FUList3]
|
||||
type=FUDesc
|
||||
opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
|
||||
count=2
|
||||
|
||||
[system.cpu.fuPool.FUList4.opList0]
|
||||
type=OpDesc
|
||||
opClass=MemRead
|
||||
opLat=1
|
||||
issueLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList4]
|
||||
type=FUDesc
|
||||
opList=system.cpu.fuPool.FUList4.opList0
|
||||
count=0
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList0]
|
||||
type=OpDesc
|
||||
opClass=MemWrite
|
||||
opLat=1
|
||||
issueLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5]
|
||||
type=FUDesc
|
||||
opList=system.cpu.fuPool.FUList5.opList0
|
||||
count=0
|
||||
|
||||
[system.cpu.fuPool.FUList6.opList0]
|
||||
type=OpDesc
|
||||
opClass=MemRead
|
||||
opLat=1
|
||||
issueLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList6.opList1]
|
||||
type=OpDesc
|
||||
opClass=MemWrite
|
||||
opLat=1
|
||||
issueLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList6]
|
||||
type=FUDesc
|
||||
opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1
|
||||
count=4
|
||||
|
||||
[system.cpu.fuPool.FUList7.opList0]
|
||||
type=OpDesc
|
||||
opClass=IprAccess
|
||||
opLat=3
|
||||
issueLat=3
|
||||
|
||||
[system.cpu.fuPool.FUList7]
|
||||
type=FUDesc
|
||||
opList=system.cpu.fuPool.FUList7.opList0
|
||||
count=1
|
||||
|
||||
[system.cpu.fuPool]
|
||||
type=FUPool
|
||||
FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7
|
||||
uid=100
|
||||
euid=100
|
||||
gid=100
|
||||
egid=100
|
||||
pid=100
|
||||
ppid=99
|
||||
|
||||
[system.cpu]
|
||||
type=DerivO3CPU
|
||||
clock=1
|
||||
numThreads=1
|
||||
activity=0
|
||||
workload=system.cpu.workload
|
||||
mem=system.cpu.dcache
|
||||
checker=null
|
||||
type=AtomicSimpleCPU
|
||||
max_insts_any_thread=0
|
||||
max_insts_all_threads=0
|
||||
max_loads_any_thread=0
|
||||
max_loads_all_threads=0
|
||||
cachePorts=200
|
||||
decodeToFetchDelay=1
|
||||
renameToFetchDelay=1
|
||||
iewToFetchDelay=1
|
||||
commitToFetchDelay=1
|
||||
fetchWidth=8
|
||||
renameToDecodeDelay=1
|
||||
iewToDecodeDelay=1
|
||||
commitToDecodeDelay=1
|
||||
fetchToDecodeDelay=1
|
||||
decodeWidth=8
|
||||
iewToRenameDelay=1
|
||||
commitToRenameDelay=1
|
||||
decodeToRenameDelay=1
|
||||
renameWidth=8
|
||||
commitToIEWDelay=1
|
||||
renameToIEWDelay=2
|
||||
issueToExecuteDelay=1
|
||||
dispatchWidth=8
|
||||
issueWidth=8
|
||||
wbWidth=8
|
||||
wbDepth=1
|
||||
fuPool=system.cpu.fuPool
|
||||
iewToCommitDelay=1
|
||||
renameToROBDelay=1
|
||||
commitWidth=8
|
||||
squashWidth=8
|
||||
trapLatency=13
|
||||
backComSize=5
|
||||
forwardComSize=5
|
||||
predType=tournament
|
||||
localPredictorSize=2048
|
||||
localCtrBits=2
|
||||
localHistoryTableSize=2048
|
||||
localHistoryBits=11
|
||||
globalPredictorSize=8192
|
||||
globalCtrBits=2
|
||||
globalHistoryBits=13
|
||||
choicePredictorSize=8192
|
||||
choiceCtrBits=2
|
||||
BTBEntries=4096
|
||||
BTBTagSize=16
|
||||
RASSize=16
|
||||
LQEntries=32
|
||||
SQEntries=32
|
||||
LFSTSize=1024
|
||||
SSITSize=1024
|
||||
numPhysIntRegs=256
|
||||
numPhysFloatRegs=256
|
||||
numIQEntries=64
|
||||
numROBEntries=192
|
||||
smtNumFetchingThreads=1
|
||||
smtFetchPolicy=SingleThread
|
||||
smtLSQPolicy=Partitioned
|
||||
smtLSQThreshold=100
|
||||
smtIQPolicy=Partitioned
|
||||
smtIQThreshold=100
|
||||
smtROBPolicy=Partitioned
|
||||
smtROBThreshold=100
|
||||
smtCommitPolicy=RoundRobin
|
||||
instShiftAmt=2
|
||||
progress_interval=0
|
||||
system=system
|
||||
cpu_id=0
|
||||
workload=system.cpu.workload
|
||||
clock=1
|
||||
phase=0
|
||||
defer_registration=false
|
||||
width=1
|
||||
function_trace=false
|
||||
function_trace_start=0
|
||||
|
||||
[system.cpu.icache]
|
||||
type=BaseCache
|
||||
size=131072
|
||||
assoc=2
|
||||
block_size=64
|
||||
latency=1
|
||||
mshrs=10
|
||||
tgts_per_mshr=5
|
||||
write_buffers=8
|
||||
prioritizeRequests=false
|
||||
do_copy=false
|
||||
protocol=null
|
||||
trace_addr=0
|
||||
hash_delay=1
|
||||
repl=null
|
||||
compressed_bus=false
|
||||
store_compressed=false
|
||||
adaptive_compression=false
|
||||
compression_latency=0
|
||||
block_size=64
|
||||
max_miss_count=0
|
||||
addr_range=[0,18446744073709551615]
|
||||
split=false
|
||||
split_size=0
|
||||
lifo=false
|
||||
two_queue=false
|
||||
prefetch_miss=false
|
||||
prefetch_access=false
|
||||
prefetcher_size=100
|
||||
prefetch_past_page=false
|
||||
prefetch_serial_squash=false
|
||||
prefetch_latency=10
|
||||
prefetch_degree=1
|
||||
prefetch_policy=none
|
||||
prefetch_cache_check_push=true
|
||||
prefetch_use_cpu_id=true
|
||||
prefetch_data_accesses_only=false
|
||||
hit_latency=1
|
||||
|
||||
[system.cpu.l2cache]
|
||||
type=BaseCache
|
||||
size=2097152
|
||||
assoc=2
|
||||
block_size=64
|
||||
latency=1
|
||||
mshrs=10
|
||||
tgts_per_mshr=5
|
||||
write_buffers=8
|
||||
prioritizeRequests=false
|
||||
do_copy=false
|
||||
protocol=null
|
||||
trace_addr=0
|
||||
hash_delay=1
|
||||
repl=null
|
||||
compressed_bus=false
|
||||
store_compressed=false
|
||||
adaptive_compression=false
|
||||
compression_latency=0
|
||||
block_size=64
|
||||
max_miss_count=0
|
||||
addr_range=[0,18446744073709551615]
|
||||
split=false
|
||||
split_size=0
|
||||
lifo=false
|
||||
two_queue=false
|
||||
prefetch_miss=false
|
||||
prefetch_access=false
|
||||
prefetcher_size=100
|
||||
prefetch_past_page=false
|
||||
prefetch_serial_squash=false
|
||||
prefetch_latency=10
|
||||
prefetch_degree=1
|
||||
prefetch_policy=none
|
||||
prefetch_cache_check_push=true
|
||||
prefetch_use_cpu_id=true
|
||||
prefetch_data_accesses_only=false
|
||||
hit_latency=1
|
||||
|
||||
[system.cpu.toL2Bus]
|
||||
type=Bus
|
||||
bus_id=0
|
||||
simulate_stalls=false
|
||||
|
||||
[trace]
|
||||
flags=
|
||||
start=0
|
||||
cycle=0
|
||||
bufsize=0
|
||||
file=cout
|
||||
dump_on_exit=false
|
||||
|
|
@ -396,8 +99,9 @@ print_cpseq=false
|
|||
print_reg_delta=false
|
||||
pc_symbol=true
|
||||
intel_format=false
|
||||
legion_lockstep=false
|
||||
trace_system=client
|
||||
|
||||
[debug]
|
||||
break_cycles=
|
||||
[statsreset]
|
||||
reset_cycle=0
|
||||
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
276
tests/long/70.twolf/ref/alpha/linux/simple-atomic/smred.out
Normal file
276
tests/long/70.twolf/ref/alpha/linux/simple-atomic/smred.out
Normal file
|
|
@ -0,0 +1,276 @@
|
|||
|
||||
TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988
|
||||
Standard Cell Placement and Global Routing Program
|
||||
Authors: Carl Sechen, Bill Swartz
|
||||
Yale University
|
||||
|
||||
|
||||
NOTE: Restart file .rs2 not used
|
||||
|
||||
TimberWolf will perform a global route step
|
||||
rowSep: 1.000000
|
||||
feedThruWidth: 4
|
||||
|
||||
******************
|
||||
BLOCK DATA
|
||||
block:1 desire:85
|
||||
block:2 desire:85
|
||||
Total Desired Length: 170
|
||||
total cell length: 168
|
||||
total block length: 168
|
||||
block x-span:84 block y-span:78
|
||||
implicit feed thru range: -84
|
||||
Using default value of bin.penalty.control:1.000000
|
||||
numBins automatically set to:5
|
||||
binWidth = average_cell_width + 0 sigma= 17
|
||||
average_cell_width is:16
|
||||
standard deviation of cell length is:23.6305
|
||||
TimberWolfSC starting from the beginning
|
||||
|
||||
|
||||
|
||||
THIS IS THE ROUTE COST OF THE ORIGINAL PLACEMENT: 645
|
||||
The number of nets with 1 pin is 4
|
||||
The number of nets with 2 pin is 9
|
||||
The number of nets with 3 pin is 0
|
||||
The number of nets with 4 pin is 2
|
||||
The number of nets with 5 pin is 0
|
||||
The number of nets with 6 pin is 0
|
||||
The number of nets with 7 pin is 0
|
||||
The number of nets with 8 pin is 0
|
||||
The number of nets with 9 pin is 0
|
||||
The number of nets with 10 pin or more is 0
|
||||
|
||||
New Cost Function: Initial Horizontal Cost:242
|
||||
New Cost Function: FEEDS:0 MISSING_ROWS:-46
|
||||
|
||||
bdxlen:86 bdylen:78
|
||||
l:0 t:78 r:86 b:0
|
||||
|
||||
|
||||
|
||||
THIS IS THE ROUTE COST OF THE CURRENT PLACEMENT: 645
|
||||
|
||||
|
||||
|
||||
THIS IS THE PENALTY OF THE CURRENT PLACEMENT: 44
|
||||
|
||||
The rand generator seed was at utemp() : 1
|
||||
|
||||
|
||||
tempfile[0][0] = 0.982500 tempfile[0][1] = 90.000000
|
||||
tempfile[1][0] = 0.915000 tempfile[1][1] = 20.000000
|
||||
tempfile[2][0] = 0.700000 tempfile[2][1] = 10.000000
|
||||
tempfile[3][0] = 0.100000 tempfile[3][1] = 0.000000
|
||||
|
||||
I T fds Wire Penalty P_lim Epct binC rowC acc s/p early FDs MRs
|
||||
1 500 0 929 592 160 30.0 1.0 3.0 84.2 34.7 0.0 0 40
|
||||
2 491 0 876 106 726 0.0 0.8 2.5 80.0 18.5 0.0 0 46
|
||||
3 482 0 822 273 372 0.0 0.5 1.5 80.8 21.2 0.0 0 46
|
||||
4 474 0 826 53 247 0.0 0.5 0.9 65.0 21.9 0.0 0 48
|
||||
5 465 8 987 73 190 0.0 0.5 0.5 50.0 38.3 0.0 0 46
|
||||
6 457 8 851 67 226 0.0 0.5 0.5 53.8 42.9 0.0 0 52
|
||||
7 449 8 1067 108 190 0.0 0.5 0.5 46.2 53.8 0.0 0 50
|
||||
8 441 8 918 106 171 0.0 0.5 0.5 47.1 40.4 0.0 0 48
|
||||
9 434 8 812 101 197 0.0 0.5 0.5 53.6 21.0 0.0 0 48
|
||||
10 426 8 1038 121 181 0.0 0.5 0.5 43.6 27.1 0.0 0 48
|
||||
11 419 8 898 93 187 0.0 0.5 0.5 45.3 47.8 0.0 0 50
|
||||
12 411 4 857 94 240 0.0 0.5 0.5 62.7 51.6 0.0 0 44
|
||||
13 404 8 1043 88 185 0.0 0.5 0.5 54.0 52.8 0.0 0 50
|
||||
14 397 8 767 94 154 0.0 0.5 0.5 33.8 35.0 0.0 0 50
|
||||
15 390 8 862 89 183 0.0 0.5 0.5 55.6 29.0 0.0 0 46
|
||||
16 383 4 798 79 173 0.0 0.5 0.5 57.5 35.3 0.0 0 52
|
||||
17 376 8 827 100 152 0.0 0.5 0.5 35.3 81.8 0.0 0 50
|
||||
18 370 8 878 101 208 0.0 0.5 0.5 44.7 46.2 0.0 0 48
|
||||
19 363 4 921 67 167 0.0 0.5 0.5 57.1 34.7 0.0 0 48
|
||||
20 357 8 933 93 154 0.0 0.5 0.5 46.5 43.6 0.0 0 52
|
||||
21 351 8 930 89 147 0.0 0.5 0.5 39.4 36.5 0.0 0 52
|
||||
22 345 8 951 79 142 0.0 0.5 0.5 32.8 51.3 0.0 0 50
|
||||
23 339 8 1046 87 207 0.0 0.5 0.5 52.8 61.0 0.0 0 48
|
||||
24 333 4 989 96 185 0.0 0.5 0.5 45.3 43.3 0.0 0 42
|
||||
25 327 4 577 86 157 0.0 0.5 0.5 31.1 55.3 0.0 0 52
|
||||
26 321 8 776 97 174 0.0 0.5 0.5 47.9 62.5 0.0 0 52
|
||||
27 315 8 850 81 188 0.0 0.5 0.5 45.0 55.2 0.0 0 50
|
||||
28 310 8 898 97 148 0.0 0.5 0.5 43.0 45.8 0.0 0 48
|
||||
29 304 8 889 65 173 0.0 0.5 0.5 32.5 41.3 0.0 0 50
|
||||
30 299 8 858 81 153 0.0 0.5 0.5 44.3 29.2 0.0 0 46
|
||||
31 294 8 871 82 187 0.0 0.5 0.5 45.7 47.7 0.0 0 48
|
||||
32 289 8 782 109 173 0.0 0.5 0.5 35.2 57.4 0.0 0 48
|
||||
33 284 8 743 98 189 0.0 0.6 0.5 41.8 64.3 0.0 0 52
|
||||
34 279 8 943 90 147 0.0 0.5 0.5 38.6 32.8 0.0 0 48
|
||||
35 274 8 907 57 166 0.0 0.5 0.5 33.6 51.0 0.0 0 48
|
||||
36 269 8 900 70 148 0.0 0.5 0.5 45.0 41.4 0.0 0 50
|
||||
37 264 4 875 106 133 0.0 0.5 0.5 31.7 55.3 0.0 0 52
|
||||
38 260 8 1023 145 149 0.0 0.6 0.5 28.7 65.0 0.0 0 52
|
||||
39 255 8 801 151 173 0.0 0.9 0.5 41.7 41.2 0.0 0 48
|
||||
40 251 8 741 104 159 0.0 0.8 0.5 36.2 47.5 0.0 0 48
|
||||
41 246 8 828 108 149 0.0 0.5 0.5 34.6 50.9 0.0 0 50
|
||||
42 242 8 947 128 132 0.0 0.7 0.5 34.2 39.0 0.0 0 50
|
||||
43 238 8 917 101 142 0.0 0.8 0.5 34.4 50.9 0.0 0 48
|
||||
44 234 8 761 86 129 0.0 0.5 0.5 42.0 36.4 0.0 0 52
|
||||
45 229 8 979 106 137 0.0 0.5 0.5 29.2 55.3 0.0 0 50
|
||||
46 225 8 806 74 130 0.0 0.7 0.5 33.1 65.4 0.0 0 52
|
||||
47 221 8 971 125 114 0.0 0.5 0.5 31.9 45.6 0.0 0 52
|
||||
48 218 8 869 125 104 0.0 0.9 0.5 30.0 56.0 0.0 0 48
|
||||
49 214 8 999 153 140 0.0 0.8 0.5 30.4 46.4 0.0 0 52
|
||||
50 210 8 798 192 139 0.0 1.0 0.5 28.9 50.0 0.0 0 52
|
||||
51 206 8 860 125 157 0.0 1.2 0.5 31.5 26.9 0.0 0 52
|
||||
52 203 8 893 186 127 5.9 0.9 0.5 26.4 42.3 0.0 0 46
|
||||
53 199 8 863 126 141 0.0 1.2 0.5 32.5 44.4 0.0 0 44
|
||||
54 196 8 788 97 133 0.0 0.9 0.5 37.5 40.0 0.0 0 50
|
||||
55 192 8 926 119 116 0.0 0.6 0.5 26.1 55.3 0.0 0 52
|
||||
56 189 8 789 162 107 0.0 0.8 0.5 25.2 40.4 0.0 0 48
|
||||
57 186 8 878 107 128 0.0 1.1 0.5 23.1 34.0 0.0 0 52
|
||||
58 182 8 775 105 122 0.0 0.8 0.5 25.5 57.4 0.0 0 50
|
||||
59 179 8 747 94 129 0.0 0.7 0.5 34.3 37.3 0.0 0 50
|
||||
60 176 8 845 96 138 0.0 0.6 0.5 28.3 41.7 0.0 0 52
|
||||
61 173 8 961 121 110 0.0 0.6 0.5 29.0 52.6 0.0 0 48
|
||||
62 170 4 911 110 109 0.0 0.9 0.5 33.5 33.3 0.0 0 48
|
||||
63 167 8 656 109 109 0.0 0.8 0.5 21.9 44.7 0.0 0 52
|
||||
64 164 8 934 117 105 0.0 0.8 0.5 15.5 50.0 0.0 0 52
|
||||
65 161 8 972 125 95 0.0 0.8 0.5 24.4 50.0 0.0 0 50
|
||||
66 158 8 894 125 101 0.0 0.9 0.5 27.2 35.9 0.0 0 52
|
||||
67 155 8 798 146 129 0.0 1.0 0.5 22.8 58.7 0.0 0 52
|
||||
68 153 8 901 183 92 0.0 1.1 0.5 23.6 34.5 0.0 0 52
|
||||
69 150 8 977 197 103 0.0 1.4 0.5 23.6 36.8 0.0 0 52
|
||||
70 147 8 905 262 93 0.0 1.5 0.5 20.3 63.4 0.0 0 52
|
||||
71 145 8 995 148 122 0.0 1.9 0.5 20.9 35.3 0.0 0 52
|
||||
72 142 8 934 230 99 0.0 1.6 0.5 20.0 65.9 0.0 0 52
|
||||
73 140 8 862 173 100 0.0 1.8 0.5 26.8 46.8 0.0 0 52
|
||||
74 137 8 924 139 90 0.0 1.7 0.5 16.8 42.5 0.0 0 52
|
||||
75 135 8 888 168 113 0.0 1.6 0.5 22.9 40.4 0.0 0 52
|
||||
76 133 8 712 212 84 0.0 1.6 0.5 13.4 46.9 0.0 0 52
|
||||
77 130 8 868 210 91 0.0 1.7 0.5 17.7 51.2 0.0 0 52
|
||||
78 128 8 952 307 92 0.0 1.9 0.5 19.7 44.9 0.0 0 50
|
||||
79 126 8 801 157 107 0.0 2.2 0.5 15.8 39.0 0.0 0 52
|
||||
80 123 8 849 147 93 0.0 2.1 0.5 15.6 51.4 0.0 0 52
|
||||
81 121 8 799 154 86 0.0 1.9 0.5 12.2 50.0 0.0 0 52
|
||||
82 119 8 941 213 82 0.0 1.8 0.5 19.5 41.2 0.0 0 50
|
||||
83 117 8 751 268 94 0.0 2.0 0.5 20.8 42.6 0.0 0 50
|
||||
84 115 8 828 198 102 0.0 2.2 0.5 15.5 59.5 0.0 0 52
|
||||
85 113 8 898 266 123 0.0 2.2 0.5 13.2 85.2 0.0 0 52
|
||||
86 111 8 943 190 93 0.0 2.4 0.5 19.5 45.1 0.0 0 52
|
||||
87 109 8 864 183 65 0.0 2.4 0.5 14.9 31.8 0.0 0 52
|
||||
88 107 8 793 203 93 0.0 2.4 0.5 11.8 35.3 0.0 0 52
|
||||
89 105 8 752 162 74 1.2 2.4 0.5 13.1 21.4 0.0 0 52
|
||||
90 103 8 801 149 77 0.0 2.3 0.5 9.7 58.3 0.0 0 52
|
||||
91 102 8 901 230 99 0.0 2.2 0.5 16.0 25.5 0.0 0 52
|
||||
92 100 8 826 201 87 0.0 2.4 0.5 12.8 45.7 0.0 0 52
|
||||
93 98 8 810 196 83 0.0 2.5 0.5 14.0 24.4 0.0 0 52
|
||||
94 96 8 857 209 68 1.0 2.5 0.5 11.5 27.0 5.1 0 52
|
||||
95 95 8 771 174 91 0.0 2.6 0.5 10.5 26.5 0.0 0 52
|
||||
96 93 8 955 210 59 0.0 2.6 0.5 10.0 36.7 0.7 0 52
|
||||
97 91 8 833 206 53 0.0 2.7 0.5 10.2 19.4 1.4 0 52
|
||||
98 90 8 888 229 86 0.0 2.8 0.5 8.1 36.0 0.0 0 52
|
||||
99 88 8 794 186 91 1.0 2.9 0.5 8.3 25.0 0.5 0 52
|
||||
100 81 8 756 170 72 1.0 2.9 0.5 6.0 23.8 7.0 0 52
|
||||
101 74 8 791 176 67 0.0 2.9 0.5 4.4 58.3 4.0 0 52
|
||||
102 67 8 813 213 43 0.0 3.0 0.5 7.0 150.0 4.2 0 52
|
||||
103 62 8 779 245 39 0.0 3.1 0.5 3.2 16.7 13.0 0 52
|
||||
104 56 8 767 303 63 0.0 3.2 0.5 4.1 20.0 0.7 0 52
|
||||
105 52 8 757 270 57 0.0 3.5 0.5 6.4 3.7 0.5 0 52
|
||||
106 47 8 763 283 41 0.0 3.7 0.5 4.5 0.0 0.0 0 52
|
||||
107 43 8 768 283 36 0.0 3.7 0.5 2.9 18.2 3.6 0 52
|
||||
108 39 8 804 283 25 0.0 3.7 0.5 3.1 0.0 6.2 0 52
|
||||
109 36 8 781 283 24 0.0 3.7 0.5 3.6 6.7 6.7 0 52
|
||||
110 33 8 738 298 42 0.0 3.7 0.5 3.3 15.4 3.5 0 52
|
||||
111 30 8 761 298 36 0.0 3.7 0.5 2.2 0.0 4.3 0 52
|
||||
112 27 8 769 298 37 0.0 3.7 0.5 0.9 0.0 2.2 0 52
|
||||
113 25 8 745 298 31 0.0 3.7 0.5 1.5 0.0 6.6 0 52
|
||||
114 23 8 753 298 16 0.0 3.7 0.5 1.3 0.0 2.8 0 52
|
||||
115 21 8 745 298 11 0.0 3.7 0.5 1.5 0.0 14.0 0 52
|
||||
116 19 8 747 298 21 0.0 3.7 0.5 2.1 0.0 5.8 0 52
|
||||
117 13 8 737 298 12 0.0 3.7 0.5 1.0 0.0 10.0 0 52
|
||||
118 9 8 736 298 4 0.0 3.7 0.5 1.5 0.0 18.5 0 52
|
||||
119 0 8 739 298 0 0.0 3.7 0.5 1.8 0.0 18.0 0 52
|
||||
120 0 8 732 298 0 0.0 3.7 0.5 1.2 0.0 21.8 0 52
|
||||
121 0 8 732 19 -1 0.0 0.0 0.5 0.0 100.0 54.8
|
||||
|
||||
Initial Wiring Cost: 645 Final Wiring Cost: 732
|
||||
############## Percent Wire Cost Reduction: -13
|
||||
|
||||
|
||||
Initial Wire Length: 645 Final Wire Length: 732
|
||||
************** Percent Wire Length Reduction: -13
|
||||
|
||||
|
||||
Initial Horiz. Wire: 216 Final Horiz. Wire: 147
|
||||
$$$$$$$$$$$ Percent H-Wire Length Reduction: 32
|
||||
|
||||
|
||||
Initial Vert. Wire: 429 Final Vert. Wire: 585
|
||||
@@@@@@@@@@@ Percent V-Wire Length Reduction: -36
|
||||
|
||||
Before Feeds are Added:
|
||||
BLOCK TOTAL CELL LENGTHS OVER/UNDER TARGET
|
||||
1 82 -20
|
||||
2 86 -16
|
||||
|
||||
LONGEST Block is:2 Its length is:86
|
||||
BLOCK TOTAL CELL LENGTHS OVER/UNDER TARGET
|
||||
1 86 -16
|
||||
2 86 -16
|
||||
|
||||
LONGEST Block is:1 Its length is:86
|
||||
Added: 1 feed-through cells
|
||||
|
||||
Removed the cell overlaps --- Will do neighbor interchanges only now
|
||||
|
||||
TOTAL INTERCONNECT LENGTH: 994
|
||||
OVERLAP PENALTY: 0
|
||||
|
||||
initialRowControl: 1.650
|
||||
finalRowControl: 0.300
|
||||
iter T Wire accept
|
||||
122 0.001 976 16%
|
||||
123 0.001 971 0%
|
||||
124 0.001 971 0%
|
||||
Total Feed-Alignment Movement (Pass 1): 0
|
||||
Total Feed-Alignment Movement (Pass 2): 0
|
||||
Total Feed-Alignment Movement (Pass 3): 0
|
||||
Total Feed-Alignment Movement (Pass 4): 0
|
||||
Total Feed-Alignment Movement (Pass 5): 0
|
||||
Total Feed-Alignment Movement (Pass 6): 0
|
||||
Total Feed-Alignment Movement (Pass 7): 0
|
||||
Total Feed-Alignment Movement (Pass 8): 0
|
||||
|
||||
The rand generator seed was at globroute() : 987654321
|
||||
|
||||
|
||||
Total Number of Net Segments: 9
|
||||
Number of Switchable Net Segments: 0
|
||||
|
||||
Number of channels: 3
|
||||
|
||||
|
||||
|
||||
THIS IS THE ORIGINAL NUMBER OF TRACKS: 5
|
||||
|
||||
|
||||
no. of accepted flips: 0
|
||||
no. of attempted flips: 0
|
||||
THIS IS THE NUMBER OF TRACKS: 5
|
||||
|
||||
|
||||
|
||||
FINAL NUMBER OF ROUTING TRACKS: 5
|
||||
|
||||
MAX OF CHANNEL: 1 is: 0
|
||||
MAX OF CHANNEL: 2 is: 4
|
||||
MAX OF CHANNEL: 3 is: 1
|
||||
FINAL TOTAL INTERCONNECT LENGTH: 978
|
||||
FINAL OVERLAP PENALTY: 0 FINAL VALUE OF TOTAL COST IS: 978
|
||||
MAX NUMBER OF ATTEMPTED FLIPS PER T: 55
|
||||
|
||||
|
||||
cost_scale_factor:3.90616
|
||||
|
||||
Number of Feed Thrus: 0
|
||||
Number of Implicit Feed Thrus: 0
|
||||
|
||||
Statistics:
|
||||
Number of Standard Cells: 10
|
||||
Number of Pads: 0
|
||||
Number of Nets: 15
|
||||
Number of Pins: 46
|
||||
Usage statistics not available
|
||||
17
tests/long/70.twolf/ref/alpha/linux/simple-atomic/smred.pin
Normal file
17
tests/long/70.twolf/ref/alpha/linux/simple-atomic/smred.pin
Normal file
|
|
@ -0,0 +1,17 @@
|
|||
$COUNT_1/$AND2_1/$ND2_1$Z 1 $COUNT_1/$AND2_1/$ND2_1 00#Z 17 52 2 1 0
|
||||
$COUNT_1/$AND2_1/$ND2_1$Z 1 ACOUNT_1 00#A 15 26 2 -1 0
|
||||
B7 2 $COUNT_1/$FJK3_2 00#K 25 78 3 -1 0
|
||||
B7 2 $COUNT_1/$FJK3_2 00#J 23 78 3 -1 0
|
||||
B7 3 $COUNT_1/$AND2_2/$ND2_1 00#A 9 26 2 -1 0
|
||||
B7 3 ACOUNT_1 01#Z 17 26 2 -1 0
|
||||
B6 5 $COUNT_1/$FJK3_1 00#K 25 26 2 -1 0
|
||||
B6 5 $COUNT_1/$FJK3_1 00#J 23 26 2 -1 0
|
||||
B6 5 $COUNT_1/$AND2_3/$IV_1 01#Z 7 26 2 -1 0
|
||||
$COUNT_1/$FJK3_1$Q 6 $COUNT_1/$FJK3_1 01#Q 81 26 2 -1 0
|
||||
$COUNT_1/$FJK3_1$Q 6 $COUNT_1/$AND2_1/$ND2_1 00#B 19 52 2 1 0
|
||||
$COUNT_1/$FJK3_2$Q 7 $COUNT_1/$FJK3_2 00#Q 81 52 2 1 0
|
||||
$COUNT_1/$FJK3_2$Q 7 $COUNT_1/$AND2_2/$ND2_1 01#B 11 26 2 -1 0
|
||||
$COUNT_1/$AND2_3/$ND2_1$Z 8 $COUNT_1/$AND2_3/$ND2_1 00#Z 5 52 2 1 0
|
||||
$COUNT_1/$AND2_3/$ND2_1$Z 8 $COUNT_1/$AND2_3/$IV_1 00#A 5 26 2 -1 0
|
||||
$COUNT_1/$AND2_4/$ND2_1$Z 9 $COUNT_1/$AND2_4/$ND2_1 00#Z 7 52 2 1 0
|
||||
$COUNT_1/$AND2_4/$ND2_1$Z 9 $COUNT_1/$AND2_4/$IV_1 00#A 3 26 2 -1 0
|
||||
11
tests/long/70.twolf/ref/alpha/linux/simple-atomic/smred.pl1
Normal file
11
tests/long/70.twolf/ref/alpha/linux/simple-atomic/smred.pl1
Normal file
|
|
@ -0,0 +1,11 @@
|
|||
$COUNT_1/$AND2_4/$IV_1 0 0 4 26 0 1
|
||||
$COUNT_1/$AND2_3/$IV_1 4 0 8 26 2 1
|
||||
$COUNT_1/$AND2_2/$ND2_1 8 0 14 26 0 1
|
||||
ACOUNT_1 14 0 18 26 2 1
|
||||
twfeed1 18 0 22 26 0 1
|
||||
$COUNT_1/$FJK3_1 22 0 86 26 0 1
|
||||
$COUNT_1/$AND2_3/$ND2_1 0 52 6 78 0 2
|
||||
$COUNT_1/$AND2_4/$ND2_1 6 52 12 78 2 2
|
||||
$COUNT_1/$AND2_2/$IV_1 12 52 16 78 2 2
|
||||
$COUNT_1/$AND2_1/$ND2_1 16 52 22 78 2 2
|
||||
$COUNT_1/$FJK3_2 22 52 86 78 0 2
|
||||
|
|
@ -0,0 +1,2 @@
|
|||
1 0 0 86 26 0 0
|
||||
2 0 52 86 78 0 0
|
||||
18
tests/long/70.twolf/ref/alpha/linux/simple-atomic/smred.sav
Normal file
18
tests/long/70.twolf/ref/alpha/linux/simple-atomic/smred.sav
Normal file
|
|
@ -0,0 +1,18 @@
|
|||
0.009592
|
||||
121
|
||||
0
|
||||
1
|
||||
0.000000
|
||||
0.500000
|
||||
3.906156
|
||||
1
|
||||
1 1 2 37 13
|
||||
2 2 0 34 65
|
||||
3 2 2 63 65
|
||||
4 1 0 59 13
|
||||
5 1 2 32 13
|
||||
6 2 0 23 65
|
||||
7 1 2 12 13
|
||||
8 2 0 6 65
|
||||
9 1 0 70 13
|
||||
10 2 0 70 65
|
||||
19
tests/long/70.twolf/ref/alpha/linux/simple-atomic/smred.sv2
Normal file
19
tests/long/70.twolf/ref/alpha/linux/simple-atomic/smred.sv2
Normal file
|
|
@ -0,0 +1,19 @@
|
|||
0.001000
|
||||
123
|
||||
0
|
||||
2
|
||||
0.000000
|
||||
0.500000
|
||||
3.906156
|
||||
1
|
||||
1 1 2 16 13
|
||||
2 2 2 19 65
|
||||
3 2 2 14 65
|
||||
4 1 0 11 13
|
||||
5 1 2 6 13
|
||||
6 2 0 3 65
|
||||
7 1 0 2 13
|
||||
8 2 2 9 65
|
||||
9 1 0 50 13
|
||||
10 2 0 54 65
|
||||
11 1 0 84 13
|
||||
29
tests/long/70.twolf/ref/alpha/linux/simple-atomic/smred.twf
Normal file
29
tests/long/70.twolf/ref/alpha/linux/simple-atomic/smred.twf
Normal file
|
|
@ -0,0 +1,29 @@
|
|||
net 1
|
||||
segment channel 2
|
||||
pin1 1 pin2 7 0 0
|
||||
net 2
|
||||
segment channel 3
|
||||
pin1 41 pin2 42 0 0
|
||||
segment channel 2
|
||||
pin1 12 pin2 3 0 0
|
||||
net 3
|
||||
segment channel 2
|
||||
pin1 35 pin2 36 0 0
|
||||
segment channel 2
|
||||
pin1 19 pin2 35 0 0
|
||||
net 4
|
||||
segment channel 2
|
||||
pin1 5 pin2 38 0 0
|
||||
net 5
|
||||
net 7
|
||||
segment channel 2
|
||||
pin1 14 pin2 43 0 0
|
||||
net 8
|
||||
segment channel 2
|
||||
pin1 23 pin2 17 0 0
|
||||
net 9
|
||||
net 11
|
||||
segment channel 2
|
||||
pin1 25 pin2 31 0 0
|
||||
net 14
|
||||
net 15
|
||||
|
|
@ -1,3 +1 @@
|
|||
warn: Entering event queue @ 0. Starting simulation...
|
||||
warn: cycle 0: fault (page_table_fault) detected @ PC 0x000000
|
||||
warn: Increasing stack 0x11ff92000:0x11ff9b000 to 0x11ff90000:0x11ff9b000 because of access to 0x11ff91ff0
|
||||
|
|
|
|||
|
|
@ -1,13 +1,14 @@
|
|||
Hello world!
|
||||
M5 Simulator System
|
||||
|
||||
Copyright (c) 2001-2006
|
||||
The Regents of The University of Michigan
|
||||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Sep 5 2006 15:28:48
|
||||
M5 started Tue Sep 5 15:42:12 2006
|
||||
M5 executing on zizzer.eecs.umich.edu
|
||||
command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/o3-timing tests/run.py quick/00.hello/alpha/linux/o3-timing
|
||||
Exiting @ tick 6870 because target called exit()
|
||||
TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988
|
||||
Standard Cell Placement and Global Routing Program
|
||||
Authors: Carl Sechen, Bill Swartz
|
||||
Yale University
|
||||
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
|
||||
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
|
||||
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45
|
||||
46 47 48 49 50 51 52 53 54 55 56 57 58 59 60
|
||||
61 62 63 64 65 66 67 68 69 70 71 72 73 74 75
|
||||
76 77 78 79 80 81 82 83 84 85 86 87 88 89 90
|
||||
91 92 93 94 95 96 97 98 99 100 101 102 103 104 105
|
||||
106 107 108 109 110 111 112 113 114 115 116 117 118 119 120
|
||||
122 123 124
|
||||
|
|
@ -7,11 +7,9 @@ max_tick=0
|
|||
output_file=cout
|
||||
progress_interval=0
|
||||
|
||||
[debug]
|
||||
break_cycles=
|
||||
|
||||
[exetrace]
|
||||
intel_format=false
|
||||
legion_lockstep=false
|
||||
pc_symbol=true
|
||||
print_cpseq=false
|
||||
print_cycle=true
|
||||
|
|
@ -53,73 +51,20 @@ mem_mode=atomic
|
|||
physmem=system.physmem
|
||||
|
||||
[system.cpu]
|
||||
type=DerivO3CPU
|
||||
children=dcache fuPool icache l2cache toL2Bus workload
|
||||
BTBEntries=4096
|
||||
BTBTagSize=16
|
||||
LFSTSize=1024
|
||||
LQEntries=32
|
||||
RASSize=16
|
||||
SQEntries=32
|
||||
SSITSize=1024
|
||||
activity=0
|
||||
backComSize=5
|
||||
choiceCtrBits=2
|
||||
choicePredictorSize=8192
|
||||
type=TimingSimpleCPU
|
||||
children=dcache icache l2cache toL2Bus workload
|
||||
clock=1
|
||||
commitToDecodeDelay=1
|
||||
commitToFetchDelay=1
|
||||
commitToIEWDelay=1
|
||||
commitToRenameDelay=1
|
||||
commitWidth=8
|
||||
decodeToFetchDelay=1
|
||||
decodeToRenameDelay=1
|
||||
decodeWidth=8
|
||||
cpu_id=0
|
||||
defer_registration=false
|
||||
dispatchWidth=8
|
||||
fetchToDecodeDelay=1
|
||||
fetchTrapLatency=1
|
||||
fetchWidth=8
|
||||
forwardComSize=5
|
||||
fuPool=system.cpu.fuPool
|
||||
function_trace=false
|
||||
function_trace_start=0
|
||||
globalCtrBits=2
|
||||
globalHistoryBits=13
|
||||
globalPredictorSize=8192
|
||||
iewToCommitDelay=1
|
||||
iewToDecodeDelay=1
|
||||
iewToFetchDelay=1
|
||||
iewToRenameDelay=1
|
||||
instShiftAmt=2
|
||||
issueToExecuteDelay=1
|
||||
issueWidth=8
|
||||
localCtrBits=2
|
||||
localHistoryBits=11
|
||||
localHistoryTableSize=2048
|
||||
localPredictorSize=2048
|
||||
max_insts_all_threads=0
|
||||
max_insts_any_thread=0
|
||||
max_loads_all_threads=0
|
||||
max_loads_any_thread=0
|
||||
mem=system.cpu.dcache
|
||||
numIQEntries=64
|
||||
numPhysFloatRegs=256
|
||||
numPhysIntRegs=256
|
||||
numROBEntries=192
|
||||
numRobs=1
|
||||
numThreads=1
|
||||
predType=tournament
|
||||
renameToDecodeDelay=1
|
||||
renameToFetchDelay=1
|
||||
renameToIEWDelay=2
|
||||
renameToROBDelay=1
|
||||
renameWidth=8
|
||||
squashWidth=8
|
||||
phase=0
|
||||
progress_interval=0
|
||||
system=system
|
||||
trapLatency=13
|
||||
wbDepth=1
|
||||
wbWidth=8
|
||||
workload=system.cpu.workload
|
||||
dcache_port=system.cpu.dcache.cpu_side
|
||||
icache_port=system.cpu.icache.cpu_side
|
||||
|
|
@ -131,7 +76,6 @@ assoc=2
|
|||
block_size=64
|
||||
compressed_bus=false
|
||||
compression_latency=0
|
||||
do_copy=false
|
||||
hash_delay=1
|
||||
hit_latency=1
|
||||
latency=1
|
||||
|
|
@ -164,143 +108,6 @@ write_buffers=8
|
|||
cpu_side=system.cpu.dcache_port
|
||||
mem_side=system.cpu.toL2Bus.port[1]
|
||||
|
||||
[system.cpu.fuPool]
|
||||
type=FUPool
|
||||
children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7
|
||||
FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7
|
||||
|
||||
[system.cpu.fuPool.FUList0]
|
||||
type=FUDesc
|
||||
children=opList0
|
||||
count=6
|
||||
opList=system.cpu.fuPool.FUList0.opList0
|
||||
|
||||
[system.cpu.fuPool.FUList0.opList0]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=IntAlu
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList1]
|
||||
type=FUDesc
|
||||
children=opList0 opList1
|
||||
count=2
|
||||
opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
|
||||
|
||||
[system.cpu.fuPool.FUList1.opList0]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=IntMult
|
||||
opLat=3
|
||||
|
||||
[system.cpu.fuPool.FUList1.opList1]
|
||||
type=OpDesc
|
||||
issueLat=19
|
||||
opClass=IntDiv
|
||||
opLat=20
|
||||
|
||||
[system.cpu.fuPool.FUList2]
|
||||
type=FUDesc
|
||||
children=opList0 opList1 opList2
|
||||
count=4
|
||||
opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
|
||||
|
||||
[system.cpu.fuPool.FUList2.opList0]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=FloatAdd
|
||||
opLat=2
|
||||
|
||||
[system.cpu.fuPool.FUList2.opList1]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=FloatCmp
|
||||
opLat=2
|
||||
|
||||
[system.cpu.fuPool.FUList2.opList2]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=FloatCvt
|
||||
opLat=2
|
||||
|
||||
[system.cpu.fuPool.FUList3]
|
||||
type=FUDesc
|
||||
children=opList0 opList1 opList2
|
||||
count=2
|
||||
opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
|
||||
|
||||
[system.cpu.fuPool.FUList3.opList0]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=FloatMult
|
||||
opLat=4
|
||||
|
||||
[system.cpu.fuPool.FUList3.opList1]
|
||||
type=OpDesc
|
||||
issueLat=12
|
||||
opClass=FloatDiv
|
||||
opLat=12
|
||||
|
||||
[system.cpu.fuPool.FUList3.opList2]
|
||||
type=OpDesc
|
||||
issueLat=24
|
||||
opClass=FloatSqrt
|
||||
opLat=24
|
||||
|
||||
[system.cpu.fuPool.FUList4]
|
||||
type=FUDesc
|
||||
children=opList0
|
||||
count=0
|
||||
opList=system.cpu.fuPool.FUList4.opList0
|
||||
|
||||
[system.cpu.fuPool.FUList4.opList0]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=MemRead
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5]
|
||||
type=FUDesc
|
||||
children=opList0
|
||||
count=0
|
||||
opList=system.cpu.fuPool.FUList5.opList0
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList0]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=MemWrite
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList6]
|
||||
type=FUDesc
|
||||
children=opList0 opList1
|
||||
count=4
|
||||
opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1
|
||||
|
||||
[system.cpu.fuPool.FUList6.opList0]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=MemRead
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList6.opList1]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=MemWrite
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList7]
|
||||
type=FUDesc
|
||||
children=opList0
|
||||
count=1
|
||||
opList=system.cpu.fuPool.FUList7.opList0
|
||||
|
||||
[system.cpu.fuPool.FUList7.opList0]
|
||||
type=OpDesc
|
||||
issueLat=3
|
||||
opClass=IprAccess
|
||||
opLat=3
|
||||
|
||||
[system.cpu.icache]
|
||||
type=BaseCache
|
||||
adaptive_compression=false
|
||||
|
|
@ -308,7 +115,6 @@ assoc=2
|
|||
block_size=64
|
||||
compressed_bus=false
|
||||
compression_latency=0
|
||||
do_copy=false
|
||||
hash_delay=1
|
||||
hit_latency=1
|
||||
latency=1
|
||||
|
|
@ -348,7 +154,6 @@ assoc=2
|
|||
block_size=64
|
||||
compressed_bus=false
|
||||
compression_latency=0
|
||||
do_copy=false
|
||||
hash_delay=1
|
||||
hit_latency=1
|
||||
latency=1
|
||||
|
|
@ -384,20 +189,33 @@ mem_side=system.membus.port[1]
|
|||
[system.cpu.toL2Bus]
|
||||
type=Bus
|
||||
bus_id=0
|
||||
clock=1000
|
||||
responder_set=false
|
||||
width=64
|
||||
port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
|
||||
|
||||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
cmd=hello
|
||||
cmd=twolf smred
|
||||
cwd=build/ALPHA_SE/tests/opt/long/70.twolf/alpha/linux/simple-timing
|
||||
egid=100
|
||||
env=
|
||||
executable=tests/test-progs/hello/bin/alpha/linux/hello
|
||||
euid=100
|
||||
executable=/dist/m5/cpu2000/binaries/alpha/tru64/twolf
|
||||
gid=100
|
||||
input=cin
|
||||
output=cout
|
||||
pid=100
|
||||
ppid=99
|
||||
system=system
|
||||
uid=100
|
||||
|
||||
[system.membus]
|
||||
type=Bus
|
||||
bus_id=0
|
||||
clock=1000
|
||||
responder_set=false
|
||||
width=64
|
||||
port=system.physmem.port system.cpu.l2cache.mem_side
|
||||
|
||||
[system.physmem]
|
||||
|
|
@ -409,6 +227,7 @@ port=system.membus.port[0]
|
|||
|
||||
[trace]
|
||||
bufsize=0
|
||||
cycle=0
|
||||
dump_on_exit=false
|
||||
file=cout
|
||||
flags=
|
||||
|
|
|
|||
|
|
@ -19,19 +19,54 @@ mem_mode=atomic
|
|||
[system.membus]
|
||||
type=Bus
|
||||
bus_id=0
|
||||
clock=1000
|
||||
width=64
|
||||
responder_set=false
|
||||
|
||||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
cmd=hello
|
||||
executable=tests/test-progs/hello/bin/alpha/linux/hello
|
||||
cmd=twolf smred
|
||||
executable=/dist/m5/cpu2000/binaries/alpha/tru64/twolf
|
||||
input=cin
|
||||
output=cout
|
||||
env=
|
||||
cwd=build/ALPHA_SE/tests/opt/long/70.twolf/alpha/linux/simple-timing
|
||||
system=system
|
||||
uid=100
|
||||
euid=100
|
||||
gid=100
|
||||
egid=100
|
||||
pid=100
|
||||
ppid=99
|
||||
|
||||
[system.cpu.dcache]
|
||||
[system.cpu]
|
||||
type=TimingSimpleCPU
|
||||
max_insts_any_thread=0
|
||||
max_insts_all_threads=0
|
||||
max_loads_any_thread=0
|
||||
max_loads_all_threads=0
|
||||
progress_interval=0
|
||||
system=system
|
||||
cpu_id=0
|
||||
workload=system.cpu.workload
|
||||
clock=1
|
||||
phase=0
|
||||
defer_registration=false
|
||||
// width not specified
|
||||
function_trace=false
|
||||
function_trace_start=0
|
||||
// simulate_stalls not specified
|
||||
|
||||
[system.cpu.toL2Bus]
|
||||
type=Bus
|
||||
bus_id=0
|
||||
clock=1000
|
||||
width=64
|
||||
responder_set=false
|
||||
|
||||
[system.cpu.icache]
|
||||
type=BaseCache
|
||||
size=262144
|
||||
size=131072
|
||||
assoc=2
|
||||
block_size=64
|
||||
latency=1
|
||||
|
|
@ -39,7 +74,6 @@ mshrs=10
|
|||
tgts_per_mshr=5
|
||||
write_buffers=8
|
||||
prioritizeRequests=false
|
||||
do_copy=false
|
||||
protocol=null
|
||||
trace_addr=0
|
||||
hash_delay=1
|
||||
|
|
@ -68,214 +102,9 @@ prefetch_use_cpu_id=true
|
|||
prefetch_data_accesses_only=false
|
||||
hit_latency=1
|
||||
|
||||
[system.cpu.fuPool.FUList0.opList0]
|
||||
type=OpDesc
|
||||
opClass=IntAlu
|
||||
opLat=1
|
||||
issueLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList0]
|
||||
type=FUDesc
|
||||
opList=system.cpu.fuPool.FUList0.opList0
|
||||
count=6
|
||||
|
||||
[system.cpu.fuPool.FUList1.opList0]
|
||||
type=OpDesc
|
||||
opClass=IntMult
|
||||
opLat=3
|
||||
issueLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList1.opList1]
|
||||
type=OpDesc
|
||||
opClass=IntDiv
|
||||
opLat=20
|
||||
issueLat=19
|
||||
|
||||
[system.cpu.fuPool.FUList1]
|
||||
type=FUDesc
|
||||
opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
|
||||
count=2
|
||||
|
||||
[system.cpu.fuPool.FUList2.opList0]
|
||||
type=OpDesc
|
||||
opClass=FloatAdd
|
||||
opLat=2
|
||||
issueLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList2.opList1]
|
||||
type=OpDesc
|
||||
opClass=FloatCmp
|
||||
opLat=2
|
||||
issueLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList2.opList2]
|
||||
type=OpDesc
|
||||
opClass=FloatCvt
|
||||
opLat=2
|
||||
issueLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList2]
|
||||
type=FUDesc
|
||||
opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
|
||||
count=4
|
||||
|
||||
[system.cpu.fuPool.FUList3.opList0]
|
||||
type=OpDesc
|
||||
opClass=FloatMult
|
||||
opLat=4
|
||||
issueLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList3.opList1]
|
||||
type=OpDesc
|
||||
opClass=FloatDiv
|
||||
opLat=12
|
||||
issueLat=12
|
||||
|
||||
[system.cpu.fuPool.FUList3.opList2]
|
||||
type=OpDesc
|
||||
opClass=FloatSqrt
|
||||
opLat=24
|
||||
issueLat=24
|
||||
|
||||
[system.cpu.fuPool.FUList3]
|
||||
type=FUDesc
|
||||
opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
|
||||
count=2
|
||||
|
||||
[system.cpu.fuPool.FUList4.opList0]
|
||||
type=OpDesc
|
||||
opClass=MemRead
|
||||
opLat=1
|
||||
issueLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList4]
|
||||
type=FUDesc
|
||||
opList=system.cpu.fuPool.FUList4.opList0
|
||||
count=0
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList0]
|
||||
type=OpDesc
|
||||
opClass=MemWrite
|
||||
opLat=1
|
||||
issueLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5]
|
||||
type=FUDesc
|
||||
opList=system.cpu.fuPool.FUList5.opList0
|
||||
count=0
|
||||
|
||||
[system.cpu.fuPool.FUList6.opList0]
|
||||
type=OpDesc
|
||||
opClass=MemRead
|
||||
opLat=1
|
||||
issueLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList6.opList1]
|
||||
type=OpDesc
|
||||
opClass=MemWrite
|
||||
opLat=1
|
||||
issueLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList6]
|
||||
type=FUDesc
|
||||
opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1
|
||||
count=4
|
||||
|
||||
[system.cpu.fuPool.FUList7.opList0]
|
||||
type=OpDesc
|
||||
opClass=IprAccess
|
||||
opLat=3
|
||||
issueLat=3
|
||||
|
||||
[system.cpu.fuPool.FUList7]
|
||||
type=FUDesc
|
||||
opList=system.cpu.fuPool.FUList7.opList0
|
||||
count=1
|
||||
|
||||
[system.cpu.fuPool]
|
||||
type=FUPool
|
||||
FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7
|
||||
|
||||
[system.cpu]
|
||||
type=DerivO3CPU
|
||||
clock=1
|
||||
numThreads=1
|
||||
activity=0
|
||||
workload=system.cpu.workload
|
||||
mem=system.cpu.dcache
|
||||
checker=null
|
||||
max_insts_any_thread=0
|
||||
max_insts_all_threads=0
|
||||
max_loads_any_thread=0
|
||||
max_loads_all_threads=0
|
||||
cachePorts=200
|
||||
decodeToFetchDelay=1
|
||||
renameToFetchDelay=1
|
||||
iewToFetchDelay=1
|
||||
commitToFetchDelay=1
|
||||
fetchWidth=8
|
||||
renameToDecodeDelay=1
|
||||
iewToDecodeDelay=1
|
||||
commitToDecodeDelay=1
|
||||
fetchToDecodeDelay=1
|
||||
decodeWidth=8
|
||||
iewToRenameDelay=1
|
||||
commitToRenameDelay=1
|
||||
decodeToRenameDelay=1
|
||||
renameWidth=8
|
||||
commitToIEWDelay=1
|
||||
renameToIEWDelay=2
|
||||
issueToExecuteDelay=1
|
||||
dispatchWidth=8
|
||||
issueWidth=8
|
||||
wbWidth=8
|
||||
wbDepth=1
|
||||
fuPool=system.cpu.fuPool
|
||||
iewToCommitDelay=1
|
||||
renameToROBDelay=1
|
||||
commitWidth=8
|
||||
squashWidth=8
|
||||
trapLatency=13
|
||||
backComSize=5
|
||||
forwardComSize=5
|
||||
predType=tournament
|
||||
localPredictorSize=2048
|
||||
localCtrBits=2
|
||||
localHistoryTableSize=2048
|
||||
localHistoryBits=11
|
||||
globalPredictorSize=8192
|
||||
globalCtrBits=2
|
||||
globalHistoryBits=13
|
||||
choicePredictorSize=8192
|
||||
choiceCtrBits=2
|
||||
BTBEntries=4096
|
||||
BTBTagSize=16
|
||||
RASSize=16
|
||||
LQEntries=32
|
||||
SQEntries=32
|
||||
LFSTSize=1024
|
||||
SSITSize=1024
|
||||
numPhysIntRegs=256
|
||||
numPhysFloatRegs=256
|
||||
numIQEntries=64
|
||||
numROBEntries=192
|
||||
smtNumFetchingThreads=1
|
||||
smtFetchPolicy=SingleThread
|
||||
smtLSQPolicy=Partitioned
|
||||
smtLSQThreshold=100
|
||||
smtIQPolicy=Partitioned
|
||||
smtIQThreshold=100
|
||||
smtROBPolicy=Partitioned
|
||||
smtROBThreshold=100
|
||||
smtCommitPolicy=RoundRobin
|
||||
instShiftAmt=2
|
||||
defer_registration=false
|
||||
function_trace=false
|
||||
function_trace_start=0
|
||||
|
||||
[system.cpu.icache]
|
||||
[system.cpu.dcache]
|
||||
type=BaseCache
|
||||
size=131072
|
||||
size=262144
|
||||
assoc=2
|
||||
block_size=64
|
||||
latency=1
|
||||
|
|
@ -283,7 +112,6 @@ mshrs=10
|
|||
tgts_per_mshr=5
|
||||
write_buffers=8
|
||||
prioritizeRequests=false
|
||||
do_copy=false
|
||||
protocol=null
|
||||
trace_addr=0
|
||||
hash_delay=1
|
||||
|
|
@ -322,7 +150,6 @@ mshrs=10
|
|||
tgts_per_mshr=5
|
||||
write_buffers=8
|
||||
prioritizeRequests=false
|
||||
do_copy=false
|
||||
protocol=null
|
||||
trace_addr=0
|
||||
hash_delay=1
|
||||
|
|
@ -351,13 +178,10 @@ prefetch_use_cpu_id=true
|
|||
prefetch_data_accesses_only=false
|
||||
hit_latency=1
|
||||
|
||||
[system.cpu.toL2Bus]
|
||||
type=Bus
|
||||
bus_id=0
|
||||
|
||||
[trace]
|
||||
flags=
|
||||
start=0
|
||||
cycle=0
|
||||
bufsize=0
|
||||
file=cout
|
||||
dump_on_exit=false
|
||||
|
|
@ -396,8 +220,9 @@ print_cpseq=false
|
|||
print_reg_delta=false
|
||||
pc_symbol=true
|
||||
intel_format=false
|
||||
legion_lockstep=false
|
||||
trace_system=client
|
||||
|
||||
[debug]
|
||||
break_cycles=
|
||||
[statsreset]
|
||||
reset_cycle=0
|
||||
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
276
tests/long/70.twolf/ref/alpha/linux/simple-timing/smred.out
Normal file
276
tests/long/70.twolf/ref/alpha/linux/simple-timing/smred.out
Normal file
|
|
@ -0,0 +1,276 @@
|
|||
|
||||
TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988
|
||||
Standard Cell Placement and Global Routing Program
|
||||
Authors: Carl Sechen, Bill Swartz
|
||||
Yale University
|
||||
|
||||
|
||||
NOTE: Restart file .rs2 not used
|
||||
|
||||
TimberWolf will perform a global route step
|
||||
rowSep: 1.000000
|
||||
feedThruWidth: 4
|
||||
|
||||
******************
|
||||
BLOCK DATA
|
||||
block:1 desire:85
|
||||
block:2 desire:85
|
||||
Total Desired Length: 170
|
||||
total cell length: 168
|
||||
total block length: 168
|
||||
block x-span:84 block y-span:78
|
||||
implicit feed thru range: -84
|
||||
Using default value of bin.penalty.control:1.000000
|
||||
numBins automatically set to:5
|
||||
binWidth = average_cell_width + 0 sigma= 17
|
||||
average_cell_width is:16
|
||||
standard deviation of cell length is:23.6305
|
||||
TimberWolfSC starting from the beginning
|
||||
|
||||
|
||||
|
||||
THIS IS THE ROUTE COST OF THE ORIGINAL PLACEMENT: 645
|
||||
The number of nets with 1 pin is 4
|
||||
The number of nets with 2 pin is 9
|
||||
The number of nets with 3 pin is 0
|
||||
The number of nets with 4 pin is 2
|
||||
The number of nets with 5 pin is 0
|
||||
The number of nets with 6 pin is 0
|
||||
The number of nets with 7 pin is 0
|
||||
The number of nets with 8 pin is 0
|
||||
The number of nets with 9 pin is 0
|
||||
The number of nets with 10 pin or more is 0
|
||||
|
||||
New Cost Function: Initial Horizontal Cost:242
|
||||
New Cost Function: FEEDS:0 MISSING_ROWS:-46
|
||||
|
||||
bdxlen:86 bdylen:78
|
||||
l:0 t:78 r:86 b:0
|
||||
|
||||
|
||||
|
||||
THIS IS THE ROUTE COST OF THE CURRENT PLACEMENT: 645
|
||||
|
||||
|
||||
|
||||
THIS IS THE PENALTY OF THE CURRENT PLACEMENT: 44
|
||||
|
||||
The rand generator seed was at utemp() : 1
|
||||
|
||||
|
||||
tempfile[0][0] = 0.982500 tempfile[0][1] = 90.000000
|
||||
tempfile[1][0] = 0.915000 tempfile[1][1] = 20.000000
|
||||
tempfile[2][0] = 0.700000 tempfile[2][1] = 10.000000
|
||||
tempfile[3][0] = 0.100000 tempfile[3][1] = 0.000000
|
||||
|
||||
I T fds Wire Penalty P_lim Epct binC rowC acc s/p early FDs MRs
|
||||
1 500 0 929 592 160 30.0 1.0 3.0 84.2 34.7 0.0 0 40
|
||||
2 491 0 876 106 726 0.0 0.8 2.5 80.0 18.5 0.0 0 46
|
||||
3 482 0 822 273 372 0.0 0.5 1.5 80.8 21.2 0.0 0 46
|
||||
4 474 0 826 53 247 0.0 0.5 0.9 65.0 21.9 0.0 0 48
|
||||
5 465 8 987 73 190 0.0 0.5 0.5 50.0 38.3 0.0 0 46
|
||||
6 457 8 851 67 226 0.0 0.5 0.5 53.8 42.9 0.0 0 52
|
||||
7 449 8 1067 108 190 0.0 0.5 0.5 46.2 53.8 0.0 0 50
|
||||
8 441 8 918 106 171 0.0 0.5 0.5 47.1 40.4 0.0 0 48
|
||||
9 434 8 812 101 197 0.0 0.5 0.5 53.6 21.0 0.0 0 48
|
||||
10 426 8 1038 121 181 0.0 0.5 0.5 43.6 27.1 0.0 0 48
|
||||
11 419 8 898 93 187 0.0 0.5 0.5 45.3 47.8 0.0 0 50
|
||||
12 411 4 857 94 240 0.0 0.5 0.5 62.7 51.6 0.0 0 44
|
||||
13 404 8 1043 88 185 0.0 0.5 0.5 54.0 52.8 0.0 0 50
|
||||
14 397 8 767 94 154 0.0 0.5 0.5 33.8 35.0 0.0 0 50
|
||||
15 390 8 862 89 183 0.0 0.5 0.5 55.6 29.0 0.0 0 46
|
||||
16 383 4 798 79 173 0.0 0.5 0.5 57.5 35.3 0.0 0 52
|
||||
17 376 8 827 100 152 0.0 0.5 0.5 35.3 81.8 0.0 0 50
|
||||
18 370 8 878 101 208 0.0 0.5 0.5 44.7 46.2 0.0 0 48
|
||||
19 363 4 921 67 167 0.0 0.5 0.5 57.1 34.7 0.0 0 48
|
||||
20 357 8 933 93 154 0.0 0.5 0.5 46.5 43.6 0.0 0 52
|
||||
21 351 8 930 89 147 0.0 0.5 0.5 39.4 36.5 0.0 0 52
|
||||
22 345 8 951 79 142 0.0 0.5 0.5 32.8 51.3 0.0 0 50
|
||||
23 339 8 1046 87 207 0.0 0.5 0.5 52.8 61.0 0.0 0 48
|
||||
24 333 4 989 96 185 0.0 0.5 0.5 45.3 43.3 0.0 0 42
|
||||
25 327 4 577 86 157 0.0 0.5 0.5 31.1 55.3 0.0 0 52
|
||||
26 321 8 776 97 174 0.0 0.5 0.5 47.9 62.5 0.0 0 52
|
||||
27 315 8 850 81 188 0.0 0.5 0.5 45.0 55.2 0.0 0 50
|
||||
28 310 8 898 97 148 0.0 0.5 0.5 43.0 45.8 0.0 0 48
|
||||
29 304 8 889 65 173 0.0 0.5 0.5 32.5 41.3 0.0 0 50
|
||||
30 299 8 858 81 153 0.0 0.5 0.5 44.3 29.2 0.0 0 46
|
||||
31 294 8 871 82 187 0.0 0.5 0.5 45.7 47.7 0.0 0 48
|
||||
32 289 8 782 109 173 0.0 0.5 0.5 35.2 57.4 0.0 0 48
|
||||
33 284 8 743 98 189 0.0 0.6 0.5 41.8 64.3 0.0 0 52
|
||||
34 279 8 943 90 147 0.0 0.5 0.5 38.6 32.8 0.0 0 48
|
||||
35 274 8 907 57 166 0.0 0.5 0.5 33.6 51.0 0.0 0 48
|
||||
36 269 8 900 70 148 0.0 0.5 0.5 45.0 41.4 0.0 0 50
|
||||
37 264 4 875 106 133 0.0 0.5 0.5 31.7 55.3 0.0 0 52
|
||||
38 260 8 1023 145 149 0.0 0.6 0.5 28.7 65.0 0.0 0 52
|
||||
39 255 8 801 151 173 0.0 0.9 0.5 41.7 41.2 0.0 0 48
|
||||
40 251 8 741 104 159 0.0 0.8 0.5 36.2 47.5 0.0 0 48
|
||||
41 246 8 828 108 149 0.0 0.5 0.5 34.6 50.9 0.0 0 50
|
||||
42 242 8 947 128 132 0.0 0.7 0.5 34.2 39.0 0.0 0 50
|
||||
43 238 8 917 101 142 0.0 0.8 0.5 34.4 50.9 0.0 0 48
|
||||
44 234 8 761 86 129 0.0 0.5 0.5 42.0 36.4 0.0 0 52
|
||||
45 229 8 979 106 137 0.0 0.5 0.5 29.2 55.3 0.0 0 50
|
||||
46 225 8 806 74 130 0.0 0.7 0.5 33.1 65.4 0.0 0 52
|
||||
47 221 8 971 125 114 0.0 0.5 0.5 31.9 45.6 0.0 0 52
|
||||
48 218 8 869 125 104 0.0 0.9 0.5 30.0 56.0 0.0 0 48
|
||||
49 214 8 999 153 140 0.0 0.8 0.5 30.4 46.4 0.0 0 52
|
||||
50 210 8 798 192 139 0.0 1.0 0.5 28.9 50.0 0.0 0 52
|
||||
51 206 8 860 125 157 0.0 1.2 0.5 31.5 26.9 0.0 0 52
|
||||
52 203 8 893 186 127 5.9 0.9 0.5 26.4 42.3 0.0 0 46
|
||||
53 199 8 863 126 141 0.0 1.2 0.5 32.5 44.4 0.0 0 44
|
||||
54 196 8 788 97 133 0.0 0.9 0.5 37.5 40.0 0.0 0 50
|
||||
55 192 8 926 119 116 0.0 0.6 0.5 26.1 55.3 0.0 0 52
|
||||
56 189 8 789 162 107 0.0 0.8 0.5 25.2 40.4 0.0 0 48
|
||||
57 186 8 878 107 128 0.0 1.1 0.5 23.1 34.0 0.0 0 52
|
||||
58 182 8 775 105 122 0.0 0.8 0.5 25.5 57.4 0.0 0 50
|
||||
59 179 8 747 94 129 0.0 0.7 0.5 34.3 37.3 0.0 0 50
|
||||
60 176 8 845 96 138 0.0 0.6 0.5 28.3 41.7 0.0 0 52
|
||||
61 173 8 961 121 110 0.0 0.6 0.5 29.0 52.6 0.0 0 48
|
||||
62 170 4 911 110 109 0.0 0.9 0.5 33.5 33.3 0.0 0 48
|
||||
63 167 8 656 109 109 0.0 0.8 0.5 21.9 44.7 0.0 0 52
|
||||
64 164 8 934 117 105 0.0 0.8 0.5 15.5 50.0 0.0 0 52
|
||||
65 161 8 972 125 95 0.0 0.8 0.5 24.4 50.0 0.0 0 50
|
||||
66 158 8 894 125 101 0.0 0.9 0.5 27.2 35.9 0.0 0 52
|
||||
67 155 8 798 146 129 0.0 1.0 0.5 22.8 58.7 0.0 0 52
|
||||
68 153 8 901 183 92 0.0 1.1 0.5 23.6 34.5 0.0 0 52
|
||||
69 150 8 977 197 103 0.0 1.4 0.5 23.6 36.8 0.0 0 52
|
||||
70 147 8 905 262 93 0.0 1.5 0.5 20.3 63.4 0.0 0 52
|
||||
71 145 8 995 148 122 0.0 1.9 0.5 20.9 35.3 0.0 0 52
|
||||
72 142 8 934 230 99 0.0 1.6 0.5 20.0 65.9 0.0 0 52
|
||||
73 140 8 862 173 100 0.0 1.8 0.5 26.8 46.8 0.0 0 52
|
||||
74 137 8 924 139 90 0.0 1.7 0.5 16.8 42.5 0.0 0 52
|
||||
75 135 8 888 168 113 0.0 1.6 0.5 22.9 40.4 0.0 0 52
|
||||
76 133 8 712 212 84 0.0 1.6 0.5 13.4 46.9 0.0 0 52
|
||||
77 130 8 868 210 91 0.0 1.7 0.5 17.7 51.2 0.0 0 52
|
||||
78 128 8 952 307 92 0.0 1.9 0.5 19.7 44.9 0.0 0 50
|
||||
79 126 8 801 157 107 0.0 2.2 0.5 15.8 39.0 0.0 0 52
|
||||
80 123 8 849 147 93 0.0 2.1 0.5 15.6 51.4 0.0 0 52
|
||||
81 121 8 799 154 86 0.0 1.9 0.5 12.2 50.0 0.0 0 52
|
||||
82 119 8 941 213 82 0.0 1.8 0.5 19.5 41.2 0.0 0 50
|
||||
83 117 8 751 268 94 0.0 2.0 0.5 20.8 42.6 0.0 0 50
|
||||
84 115 8 828 198 102 0.0 2.2 0.5 15.5 59.5 0.0 0 52
|
||||
85 113 8 898 266 123 0.0 2.2 0.5 13.2 85.2 0.0 0 52
|
||||
86 111 8 943 190 93 0.0 2.4 0.5 19.5 45.1 0.0 0 52
|
||||
87 109 8 864 183 65 0.0 2.4 0.5 14.9 31.8 0.0 0 52
|
||||
88 107 8 793 203 93 0.0 2.4 0.5 11.8 35.3 0.0 0 52
|
||||
89 105 8 752 162 74 1.2 2.4 0.5 13.1 21.4 0.0 0 52
|
||||
90 103 8 801 149 77 0.0 2.3 0.5 9.7 58.3 0.0 0 52
|
||||
91 102 8 901 230 99 0.0 2.2 0.5 16.0 25.5 0.0 0 52
|
||||
92 100 8 826 201 87 0.0 2.4 0.5 12.8 45.7 0.0 0 52
|
||||
93 98 8 810 196 83 0.0 2.5 0.5 14.0 24.4 0.0 0 52
|
||||
94 96 8 857 209 68 1.0 2.5 0.5 11.5 27.0 5.1 0 52
|
||||
95 95 8 771 174 91 0.0 2.6 0.5 10.5 26.5 0.0 0 52
|
||||
96 93 8 955 210 59 0.0 2.6 0.5 10.0 36.7 0.7 0 52
|
||||
97 91 8 833 206 53 0.0 2.7 0.5 10.2 19.4 1.4 0 52
|
||||
98 90 8 888 229 86 0.0 2.8 0.5 8.1 36.0 0.0 0 52
|
||||
99 88 8 794 186 91 1.0 2.9 0.5 8.3 25.0 0.5 0 52
|
||||
100 81 8 756 170 72 1.0 2.9 0.5 6.0 23.8 7.0 0 52
|
||||
101 74 8 791 176 67 0.0 2.9 0.5 4.4 58.3 4.0 0 52
|
||||
102 67 8 813 213 43 0.0 3.0 0.5 7.0 150.0 4.2 0 52
|
||||
103 62 8 779 245 39 0.0 3.1 0.5 3.2 16.7 13.0 0 52
|
||||
104 56 8 767 303 63 0.0 3.2 0.5 4.1 20.0 0.7 0 52
|
||||
105 52 8 757 270 57 0.0 3.5 0.5 6.4 3.7 0.5 0 52
|
||||
106 47 8 763 283 41 0.0 3.7 0.5 4.5 0.0 0.0 0 52
|
||||
107 43 8 768 283 36 0.0 3.7 0.5 2.9 18.2 3.6 0 52
|
||||
108 39 8 804 283 25 0.0 3.7 0.5 3.1 0.0 6.2 0 52
|
||||
109 36 8 781 283 24 0.0 3.7 0.5 3.6 6.7 6.7 0 52
|
||||
110 33 8 738 298 42 0.0 3.7 0.5 3.3 15.4 3.5 0 52
|
||||
111 30 8 761 298 36 0.0 3.7 0.5 2.2 0.0 4.3 0 52
|
||||
112 27 8 769 298 37 0.0 3.7 0.5 0.9 0.0 2.2 0 52
|
||||
113 25 8 745 298 31 0.0 3.7 0.5 1.5 0.0 6.6 0 52
|
||||
114 23 8 753 298 16 0.0 3.7 0.5 1.3 0.0 2.8 0 52
|
||||
115 21 8 745 298 11 0.0 3.7 0.5 1.5 0.0 14.0 0 52
|
||||
116 19 8 747 298 21 0.0 3.7 0.5 2.1 0.0 5.8 0 52
|
||||
117 13 8 737 298 12 0.0 3.7 0.5 1.0 0.0 10.0 0 52
|
||||
118 9 8 736 298 4 0.0 3.7 0.5 1.5 0.0 18.5 0 52
|
||||
119 0 8 739 298 0 0.0 3.7 0.5 1.8 0.0 18.0 0 52
|
||||
120 0 8 732 298 0 0.0 3.7 0.5 1.2 0.0 21.8 0 52
|
||||
121 0 8 732 19 -1 0.0 0.0 0.5 0.0 100.0 54.8
|
||||
|
||||
Initial Wiring Cost: 645 Final Wiring Cost: 732
|
||||
############## Percent Wire Cost Reduction: -13
|
||||
|
||||
|
||||
Initial Wire Length: 645 Final Wire Length: 732
|
||||
************** Percent Wire Length Reduction: -13
|
||||
|
||||
|
||||
Initial Horiz. Wire: 216 Final Horiz. Wire: 147
|
||||
$$$$$$$$$$$ Percent H-Wire Length Reduction: 32
|
||||
|
||||
|
||||
Initial Vert. Wire: 429 Final Vert. Wire: 585
|
||||
@@@@@@@@@@@ Percent V-Wire Length Reduction: -36
|
||||
|
||||
Before Feeds are Added:
|
||||
BLOCK TOTAL CELL LENGTHS OVER/UNDER TARGET
|
||||
1 82 -20
|
||||
2 86 -16
|
||||
|
||||
LONGEST Block is:2 Its length is:86
|
||||
BLOCK TOTAL CELL LENGTHS OVER/UNDER TARGET
|
||||
1 86 -16
|
||||
2 86 -16
|
||||
|
||||
LONGEST Block is:1 Its length is:86
|
||||
Added: 1 feed-through cells
|
||||
|
||||
Removed the cell overlaps --- Will do neighbor interchanges only now
|
||||
|
||||
TOTAL INTERCONNECT LENGTH: 994
|
||||
OVERLAP PENALTY: 0
|
||||
|
||||
initialRowControl: 1.650
|
||||
finalRowControl: 0.300
|
||||
iter T Wire accept
|
||||
122 0.001 976 16%
|
||||
123 0.001 971 0%
|
||||
124 0.001 971 0%
|
||||
Total Feed-Alignment Movement (Pass 1): 0
|
||||
Total Feed-Alignment Movement (Pass 2): 0
|
||||
Total Feed-Alignment Movement (Pass 3): 0
|
||||
Total Feed-Alignment Movement (Pass 4): 0
|
||||
Total Feed-Alignment Movement (Pass 5): 0
|
||||
Total Feed-Alignment Movement (Pass 6): 0
|
||||
Total Feed-Alignment Movement (Pass 7): 0
|
||||
Total Feed-Alignment Movement (Pass 8): 0
|
||||
|
||||
The rand generator seed was at globroute() : 987654321
|
||||
|
||||
|
||||
Total Number of Net Segments: 9
|
||||
Number of Switchable Net Segments: 0
|
||||
|
||||
Number of channels: 3
|
||||
|
||||
|
||||
|
||||
THIS IS THE ORIGINAL NUMBER OF TRACKS: 5
|
||||
|
||||
|
||||
no. of accepted flips: 0
|
||||
no. of attempted flips: 0
|
||||
THIS IS THE NUMBER OF TRACKS: 5
|
||||
|
||||
|
||||
|
||||
FINAL NUMBER OF ROUTING TRACKS: 5
|
||||
|
||||
MAX OF CHANNEL: 1 is: 0
|
||||
MAX OF CHANNEL: 2 is: 4
|
||||
MAX OF CHANNEL: 3 is: 1
|
||||
FINAL TOTAL INTERCONNECT LENGTH: 978
|
||||
FINAL OVERLAP PENALTY: 0 FINAL VALUE OF TOTAL COST IS: 978
|
||||
MAX NUMBER OF ATTEMPTED FLIPS PER T: 55
|
||||
|
||||
|
||||
cost_scale_factor:3.90616
|
||||
|
||||
Number of Feed Thrus: 0
|
||||
Number of Implicit Feed Thrus: 0
|
||||
|
||||
Statistics:
|
||||
Number of Standard Cells: 10
|
||||
Number of Pads: 0
|
||||
Number of Nets: 15
|
||||
Number of Pins: 46
|
||||
Usage statistics not available
|
||||
Some files were not shown because too many files have changed in this diff Show more
Loading…
Reference in a new issue