Commit graph

3712 commits

Author SHA1 Message Date
Gabe Black
dc105934f3 Change to use -return_value.value like other implementations.
--HG--
extra : convert_revision : 513422c1c8c24f3662e6a423d13ee033424aa44b
2006-12-06 05:47:19 -05:00
Gabe Black
bf5f6c6430 Some changes for misc regs which were changed into unofficial integer registers, and moved the flattenIndex function into the register file.
--HG--
extra : convert_revision : 6b797c793a6c12c61a23f0f78a1ea1c88609553e
2006-12-06 05:46:44 -05:00
Gabe Black
5ad1731a12 Reorganize the includes and add an include for misc.hh.
--HG--
extra : convert_revision : 484b2d07a1e8b3879c35d80bf16b73fd0cc9be1f
2006-12-06 05:45:18 -05:00
Gabe Black
643cb6dd81 Added some debug output, and made sure not to accidentally ask for the result of a store conditional.
--HG--
extra : convert_revision : d36ff9e2343fdf78a3bc16a1348975fdba5c55e2
2006-12-06 05:44:31 -05:00
Gabe Black
a36a59e8d7 Some basic fix ups, and CWP is no longer set explicitly.
--HG--
extra : convert_revision : 1dde5594a2bcfd9fb5ad974360b3dc035f1624e5
2006-12-06 05:43:25 -05:00
Gabe Black
c541be3a48 Changed the integer register file to work with flattened indices.
--HG--
extra : convert_revision : c5153c3c712e5d18b5233e1fd205806adcb30654
2006-12-06 05:42:09 -05:00
Gabe Black
4d8a0541dd Change MIPS's setSyscallReturn to use a thread context.
--HG--
extra : convert_revision : 618f8404ec5380615e28170d761b2fcdf9c07d96
2006-12-06 05:41:08 -05:00
Gabe Black
a3f351ab59 Added basic flatten function for mips.
--HG--
extra : convert_revision : 2c32851584001734d139f36c4d58c5e61067fcfc
2006-12-06 05:40:11 -05:00
Gabe Black
12c5bd2305 Move the SyscallReturn class into sim/syscallreturn.hh. Also move some miscregs into the integer register file so they get renamed.
src/arch/alpha/syscallreturn.hh:
src/arch/mips/syscallreturn.hh:
src/sim/syscallreturn.hh:
    Move the SyscallReturn class into sim/syscallreturn.hh
src/arch/sparc/faults.cc:
src/arch/sparc/isa/operands.isa:
src/arch/sparc/isa_traits.hh:
src/arch/sparc/miscregfile.cc:
src/arch/sparc/miscregfile.hh:
src/arch/sparc/process.cc:
src/arch/sparc/sparc_traits.hh:
    Move some miscregs into the integer register file so they get renamed.

--HG--
extra : convert_revision : df5b94fa1e7fdca34816084e0a423d6fdf86c79b
2006-12-05 01:55:02 -05:00
Gabe Black
f2daf210f1 Initial changes to get O3 working with SPARC
src/arch/sparc/process.cc:
    MachineBytes doesn't exist any more.
src/arch/sparc/regfile.cc:
    Add in the miscRegFile for good measure.
src/cpu/o3/isa_specific.hh:
    Add in a section for SPARC
src/cpu/o3/sparc/cpu.cc:
src/cpu/o3/sparc/cpu.hh:
src/cpu/o3/sparc/cpu_builder.cc:
src/cpu/o3/sparc/cpu_impl.hh:
src/cpu/o3/sparc/dyn_inst.cc:
src/cpu/o3/sparc/dyn_inst.hh:
src/cpu/o3/sparc/dyn_inst_impl.hh:
src/cpu/o3/sparc/impl.hh:
src/cpu/o3/sparc/params.hh:
src/cpu/o3/sparc/thread_context.cc:
src/cpu/o3/sparc/thread_context.hh:
    Sparc version of this file.

--HG--
extra : convert_revision : 34bb5218f802d0a1328132a518cdd769fb59b6a4
2006-11-24 22:06:33 -05:00
Gabe Black
5f446e36b6 Merge zower:/eecshome/m5/newmem
into  ewok.(none):/home/gblack/m5/newmemo3

--HG--
extra : convert_revision : e8d6ce19a83fe526112c1dd61c48196eb8c0951f
2006-11-24 14:08:44 -05:00
Gabe Black
d0f4a4c441 Merge zizzer:/bk/newmem
into  zower.eecs.umich.edu:/eecshome/m5/newmem

--HG--
extra : convert_revision : 7dbd30ce5579dd62d5f54bb5d75cf12346bc5d1d
2006-11-24 14:08:43 -05:00
Gabe Black
c6ddab95df Rename this function.
--HG--
extra : convert_revision : 57ea1e1d3b75e35abb3310d392ec70086fff699a
2006-11-24 14:01:18 -05:00
Gabe Black
7708217167 Fix weird type modifier.
--HG--
extra : convert_revision : 7372b7a92b3c9d05388acb43ba58ada18464fa24
2006-11-24 14:00:45 -05:00
Gabe Black
96a6af98e2 Fix an include problem.
--HG--
extra : convert_revision : 89be55bd3f4f9b452a680a98b69ce42b80546769
2006-11-24 14:00:00 -05:00
Steve Reinhardt
28f8318252 Add no-op versions of ivlb and ivle back in for backwards compatibility.
--HG--
extra : convert_revision : 383b72c130b20f3d7cde4e08fa36a481f3c0bf7c
2006-11-24 12:32:33 -05:00
Steve Reinhardt
3dbb70dd25 Merge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/newmem
into  zizzer.eecs.umich.edu:/z/stever/bk/newmem-head

--HG--
extra : convert_revision : 154bc605c62b1e51c32e65916d4c2eda3a3f22fd
2006-11-23 10:46:24 -05:00
Gabe Black
68ae846f3e Use the right constant.
--HG--
extra : convert_revision : f93182ed41057025cc10df443b24e82fbe783df6
2006-11-23 01:27:41 -05:00
Gabe Black
de445b5e96 Fixes to the isa description.
src/arch/sparc/isa/base.isa:
    Fix a constant.
src/arch/sparc/isa/decoder.isa:
    Made carry calculation more consistent.
src/arch/sparc/isa/operands.isa:
    Use the right constant.

--HG--
extra : convert_revision : 25b3a09ff20d4b8e1a95ee8a983d14ef3cfe73bb
2006-11-23 00:36:42 -05:00
Gabe Black
758c780651 Moved some constants from isa_traits.hh to the reg file headers.
--HG--
extra : convert_revision : 378b2d9791e6282539900a2261ad2275d726b4be
2006-11-22 23:49:44 -05:00
Gabe Black
f85082e0a0 Added a parameter to set memory to zero. This is to support Legion, and once we can make our own hypervisor binary, we probably won't need it.
--HG--
extra : convert_revision : 168883e4a5d3760962cd9759a6f41c66f5a6402a
2006-11-22 23:09:27 -05:00
Ron Dreslinski
28fd4ab39f Do a functional access to levels above on a read as a temporary solution for L2's in FS
Fix a small writeback bug when missing in the L2 in atomic mode

src/mem/bus.cc:
    Fix a comment to make sense
src/mem/cache/cache_impl.hh:
    Do a functional access to levels above on a read as a temporary solution for L2's in FS
    Also fix a small writeback miss in L2 issue
src/mem/cache/coherence/simple_coherence.hh:
src/mem/cache/coherence/uni_coherence.cc:
src/mem/cache/coherence/uni_coherence.hh:
    Do a functional access to levels above on a read as a temporary solution for L2's in FS
tests/quick/00.hello/ref/alpha/linux/o3-timing/m5stats.txt:
tests/quick/00.hello/ref/alpha/linux/simple-timing/m5stats.txt:
tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/m5stats.txt:
    Update ref's for writeback changes

--HG--
extra : convert_revision : 937febd577b16b7fd97a5a68acaf53541828a251
2006-11-22 20:20:38 -05:00
Gabe Black
0a99750ebf Merge zizzer:/bk/sparcfs
into  zower.eecs.umich.edu:/eecshome/m5/newmem

--HG--
extra : convert_revision : 75f3398e38e18eb1f8248e23708d7a8d8cce0fc5
2006-11-22 15:45:32 -05:00
Gabe Black
04e6a3a07b Fix an assert to correctly make sure a request falls entirely inside a memory.
--HG--
extra : convert_revision : 71cf02edffbc7029666c0d9c97b67e1d32332758
2006-11-20 18:11:19 -05:00
Gabe Black
c1aeb7229e Add in checks of more Legion based state, and put in more sophisticated formatting functions.
--HG--
extra : convert_revision : e3aa5919a6480aa01924c832a86fa1e8ddf5ba0d
2006-11-20 18:09:55 -05:00
Gabe Black
b4a31cb8b5 Make sure only real bits of pstate can be set.
--HG--
extra : convert_revision : 8707bbed2aeb80613f86503e92b63853767adaa9
2006-11-20 18:08:50 -05:00
Gabe Black
a0287c1e2d Set the pstate.priv bit to 1 in hyperpriveleged mode. The description in the manual of what happens during a trap says it should be 0, and other places say it doesn't matter.
--HG--
extra : convert_revision : 9ecb6af06657e936a208cbeb8e4a18305869b949
2006-11-20 18:07:58 -05:00
Gabe Black
cd2727694d Add in rom/rams for the nvram, hypervisor description, and partition description.
--HG--
extra : convert_revision : a49de5fcfbea307c971964b8a68b95eb5d9a2bf4
2006-11-20 17:59:35 -05:00
Kevin Lim
719416b60f Fix typo.
--HG--
extra : convert_revision : 2dd830c6b3b5df894608b7596250b0181a3dfdf0
2006-11-20 11:44:27 -05:00
Steve Reinhardt
6fa5c7af95 Merge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/newmem
into  zizzer.eecs.umich.edu:/z/stever/bk/newmem-head

--HG--
extra : convert_revision : c2b7784377d85df5b8ee39c891cd3da9907410d8
2006-11-19 18:38:12 -05:00
Kevin Lim
a2113fd3dc Update Virtual and Physical ports.
src/cpu/o3/alpha/cpu_impl.hh:
    Handle the PhysicalPort and VirtualPort in the ThreadState.
src/cpu/o3/cpu.cc:
    Initialize the thread context.
src/cpu/o3/thread_context.hh:
    Add new function to initialize thread context.
src/cpu/o3/thread_context_impl.hh:
    Use code now put into function.
src/cpu/simple_thread.cc:
    Move code to ThreadState and use the new helper function.
src/cpu/simple_thread.hh:
    Remove init() in this derived class; use init() from ThreadState base class.
src/cpu/thread_state.cc:
    Move setting up of Physical and Virtual ports here.  Change getMemFuncPort() to connectToMemFunc(), which connects a port to a functional port of the memory object below the CPU.
src/cpu/thread_state.hh:
    Update functions.

--HG--
extra : convert_revision : ff254715ef0b259dc80d08f13543b63e4024ca8d
2006-11-19 17:43:03 -05:00
Ron Dreslinski
a00e13b1fe Merge zizzer:/bk/newmem
into  zazzer.eecs.umich.edu:/z/rdreslin/m5bk/newmemcleanest

--HG--
extra : convert_revision : 1fc55d7d5707bb7c63790aab306ca5ea8ade5fab
2006-11-17 22:01:18 -05:00
Ron Dreslinski
cd0b65508e Make an initialization pass for the thread context and set the [phys,virt]Port correctly
src/cpu/simple/atomic.cc:
src/cpu/simple/timing.cc:
    Call the thread context initialization

--HG--
extra : convert_revision : d7dc2a8b893dc670077b7f6150d4b710a1778620
2006-11-17 21:55:28 -05:00
Nathan Binkert
f028865d35 add warn_once which will print any given warning message
only once.

--HG--
extra : convert_revision : b64bb495c1bd0c4beb3db6ca28fad5af4d05ef8e
2006-11-16 13:18:21 -08:00
Nathan Binkert
bd8cc37650 Implement a single config file to encompass all of the SPEC
CPU2000 stuff, and use it in all of the tests that currently
use SPEC

--HG--
extra : convert_revision : 8cd26a597e51a90b6d2810d344a075f5aa0f011b
2006-11-16 13:10:38 -08:00
Nathan Binkert
4c2e65c94e implement RUSAGE_CHILDREN for getrusage since it's trivial
--HG--
extra : convert_revision : bc12b3b2e9ee02f42c437cbc20680ea00e19a801
2006-11-16 13:08:29 -08:00
Nathan Binkert
31d829d388 Implement current working directory for LiveProcesses
--HG--
extra : convert_revision : a2d3cf29ab65c61af27d82a8c421a41a19fd5aeb
2006-11-16 12:43:11 -08:00
Gabe Black
74654ddd1f Merge zower.eecs.umich.edu:/home/gblack/m5/newmemmemops
into  zower.eecs.umich.edu:/eecshome/m5/newmem

--HG--
extra : convert_revision : 74b2352b8f088e38cd1ecf3a8233b45df0476d93
2006-11-16 14:42:44 -05:00
Gabe Black
14ebaa1ecc Merge zizzer.eecs.umich.edu:/bk/newmem/
into  zower.eecs.umich.edu:/home/gblack/m5/newmemmemops

--HG--
extra : convert_revision : c49b760eac758dbde30867cb638fcb3b790f4721
2006-11-16 14:41:56 -05:00
Gabe Black
cd5b33b9ff Fixes for SPARC_FS
configs/common/FSConfig.py:
    Make a SPARC system create an IO bus.
src/python/m5/objects/T1000.py:
    Create a T1000 platform
src/arch/sparc/miscregfile.cc:
    Initialize the strand status register to the value legion provides.
src/cpu/exetrace.cc:
    Truncate an ExtMachInst to a MachInst before comparing with Legion.

--HG--
extra : convert_revision : e4189b572a5297e8362f5bd26d87b74736c8e5f1
2006-11-16 12:34:10 -05:00
Ron Dreslinski
dbdf2f14ae Add L2 cache option to fs.py --l2cache
--HG--
extra : convert_revision : 5bdd1129c3b23e91d441e7b83f6a824ef7740fab
2006-11-15 18:22:15 -05:00
Ron Dreslinski
4fbbb74a5c Merge zizzer:/bk/newmem
into  zazzer.eecs.umich.edu:/z/rdreslin/m5bk/newmemcleanest

--HG--
extra : convert_revision : 8d61b474428d494b1a5382e4cf95934ad54e35dd
2006-11-14 18:41:37 -05:00
Kevin Lim
069c7c30d1 Various fixes to delete packet and request a little better.
src/cpu/simple/timing.cc:
    Various updates for deleting requests more properly.

    The major change is moving the deletion of the fetch request/packet to after the instruction has executed and completed.  This should fix a few bugs because Ron's memory system didn't expect a call for a functional access while a timing access was being processed.

--HG--
extra : convert_revision : c7cf114bb1ff3cdaa7b0a40ed4c5302dc9d3a522
2006-11-14 17:22:32 -05:00
Ron Dreslinski
7cd05a998d Merge zizzer:/bk/newmem
into  zazzer.eecs.umich.edu:/z/rdreslin/m5bk/newmemcleanest

--HG--
extra : convert_revision : b216fcdb2632dce68ac18932b0c13408eb1aeaf4
2006-11-14 17:19:57 -05:00
Ron Dreslinski
c32f3056f9 Fix bugs around uni-coherence invalidates being propogated properly.
src/mem/bus.cc:
    Make it so that invalidates being sent from the responder up don't call the responder
    but they should also not Panic.
src/mem/packet.hh:
    If we don't have data in the packet, don't call deleteData:
    Example: InvalidateRequests never have data.

--HG--
extra : convert_revision : 18766bc9f3bb4d852ac651d094254d347abd1634
2006-11-14 17:15:05 -05:00
Gabe Black
ac2c7967f6 Merge zizzer.eecs.umich.edu:/bk/newmem/
into  zeep.eecs.umich.edu:/home/gblack/m5/newmemmemops

--HG--
extra : convert_revision : 966246877ac1f1e6c2675d413b0b405cccfecbeb
2006-11-14 15:23:23 -05:00
Gabe Black
079dd45417 Merge 141.212.106.238:/home/gblack/m5/newmemmemops
into  zizzer.eecs.umich.edu:/.automount/wexford/x/gblack/m5/newmem

--HG--
extra : convert_revision : 8e805b9bbd5c64c2e5951384b3c6ef712062d08c
2006-11-14 15:14:28 -05:00
Gabe Black
bc4d15ddd1 Create a stub t1000 platform.
--HG--
extra : convert_revision : 7e27b23b66c743b4625a1dd9d8d6ba61bff45168
2006-11-14 15:14:27 -05:00
Lisa Hsu
2f6a9454d1 Merge zizzer:/bk/newmem
into  zed.eecs.umich.edu:/z/hsul/work/sparc/m5

--HG--
extra : convert_revision : 6abd919711966eaaa157483557a3f953b02dde01
2006-11-14 13:00:05 -05:00
Lisa Hsu
ee777f35c2 interrupts.hh:
make a likewise updateIntrInfo for Sparc that's blank so it doesn't fart on build

src/arch/sparc/interrupts.hh:
    make a likewise updateIntrInfo for Sparc that's blank so it doesn't fart on build

--HG--
extra : convert_revision : 5f469d0cf897479b42703104cd801a8ef923fcae
2006-11-14 12:59:57 -05:00