Add in checks of more Legion based state, and put in more sophisticated formatting functions.
--HG-- extra : convert_revision : e3aa5919a6480aa01924c832a86fa1e8ddf5ba0d
This commit is contained in:
Gabe Black
parent
b4a31cb8b5
commit
c1aeb7229e
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@ -66,6 +66,56 @@ SharedData *shared_data = NULL;
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// Methods for the InstRecord object
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//
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#if THE_ISA == SPARC_ISA
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inline char * genCenteredLabel(int length, char * buffer, char * label)
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{
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int labelLength = strlen(label);
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assert(labelLength <= length);
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int leftPad = (length - labelLength) / 2;
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int rightPad = length - leftPad - labelLength;
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char format[64];
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sprintf(format, "%%%ds%%s%%%ds", leftPad, rightPad);
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sprintf(buffer, format, "", label, "");
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return buffer;
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}
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inline void printRegPair(ostream & os, char const * title, uint64_t a, uint64_t b)
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{
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ccprintf(os, " %16s | %#018x %s %#-018x \n",
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title, a, (a == b) ? "|" : "X", b);
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}
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inline void printColumnLabels(ostream & os)
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{
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static char * regLabel = genCenteredLabel(16, new char[17], "Register");
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static char * m5Label = genCenteredLabel(18, new char[18], "M5");
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static char * legionLabel = genCenteredLabel(18, new char[18], "Legion");
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ccprintf(os, " %s | %s | %s \n", regLabel, m5Label, legionLabel);
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ccprintf(os, "--------------------+-----------------------+-----------------------\n");
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}
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inline void printSectionHeader(ostream & os, char * name)
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{
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char sectionString[70];
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genCenteredLabel(69, sectionString, name);
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ccprintf(os, "====================================================================\n");
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ccprintf(os, "%69s\n", sectionString);
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ccprintf(os, "====================================================================\n");
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}
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inline void printLevelHeader(ostream & os, int level)
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{
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char sectionString[70];
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char levelName[70];
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sprintf(levelName, "Trap stack level %d", level);
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genCenteredLabel(69, sectionString, levelName);
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ccprintf(os, "====================================================================\n");
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ccprintf(os, "%69s\n", sectionString);
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ccprintf(os, "====================================================================\n");
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}
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#endif
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void
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Trace::InstRecord::dump(ostream &outs)
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@ -237,14 +287,34 @@ Trace::InstRecord::dump(ostream &outs)
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bool diffPC = false;
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bool diffInst = false;
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bool diffRegs = false;
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bool diffTpc = false;
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bool diffTnpc = false;
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bool diffTstate = false;
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bool diffTt = false;
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bool diffTba = false;
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bool diffHpstate = false;
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bool diffHtstate = false;
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bool diffHtba = false;
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bool diffPstate = false;
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bool diffY = false;
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bool diffCcr = false;
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bool diffTl = false;
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bool diffGl = false;
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bool diffAsi = false;
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bool diffPil = false;
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bool diffCwp = false;
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bool diffCansave = false;
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bool diffCanrestore = false;
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bool diffOtherwin = false;
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bool diffCleanwin = false;
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Addr m5Pc, lgnPc;
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if(!staticInst->isMicroOp() || staticInst->isLastMicroOp()) {
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while (!compared) {
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m5Pc = PC & TheISA::PAddrImplMask;
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lgnPc = shared_data->pc & TheISA::PAddrImplMask;
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if (shared_data->flags == OWN_M5) {
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m5Pc = PC & TheISA::PAddrImplMask;
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lgnPc = shared_data->pc & TheISA::PAddrImplMask;
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if (lgnPc != m5Pc)
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diffPC = true;
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if (shared_data->instruction !=
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@ -256,8 +326,71 @@ Trace::InstRecord::dump(ostream &outs)
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diffRegs = true;
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}
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}
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uint64_t oldTl = thread->readMiscReg(MISCREG_TL);
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if (oldTl != shared_data->tl)
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diffTl = true;
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for (int i = 1; i <= MaxTL; i++) {
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thread->setMiscReg(MISCREG_TL, i);
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if (thread->readMiscReg(MISCREG_TPC) !=
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shared_data->tpc[i])
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diffTpc = true;
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if (thread->readMiscReg(MISCREG_TNPC) !=
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shared_data->tnpc[i])
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diffTnpc = true;
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if (thread->readMiscReg(MISCREG_TSTATE) !=
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shared_data->tstate[i])
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diffTstate = true;
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if (thread->readMiscReg(MISCREG_TT) !=
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shared_data->tt[i])
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diffTt = true;
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if (thread->readMiscReg(MISCREG_HTSTATE) !=
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shared_data->htstate[i])
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diffHtstate = true;
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}
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thread->setMiscReg(MISCREG_TL, oldTl);
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if (diffPC || diffInst || diffRegs ) {
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if(shared_data->tba != thread->readMiscReg(MISCREG_TBA))
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diffTba = true;
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//When the hpstate register is read by an instruction,
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//legion has bit 11 set. When it's in storage, it doesn't.
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//Since we don't directly support seperate interpretations
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//of the registers like that, the bit is always set to 1 and
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//we just don't compare it. It's not supposed to matter
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//anyway.
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if((shared_data->hpstate | (1 << 11)) != thread->readMiscReg(MISCREG_HPSTATE))
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diffHpstate = true;
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if(shared_data->htba != thread->readMiscReg(MISCREG_HTBA))
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diffHtba = true;
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if(shared_data->pstate != thread->readMiscReg(MISCREG_PSTATE))
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diffPstate = true;
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if(shared_data->y != thread->readMiscReg(MISCREG_Y))
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diffY = true;
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if(shared_data->ccr != thread->readMiscReg(MISCREG_CCR))
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diffCcr = true;
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if(shared_data->gl != thread->readMiscReg(MISCREG_GL))
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diffGl = true;
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if(shared_data->asi != thread->readMiscReg(MISCREG_ASI))
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diffAsi = true;
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if(shared_data->pil != thread->readMiscReg(MISCREG_PIL))
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diffPil = true;
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if(shared_data->cwp != thread->readMiscReg(MISCREG_CWP))
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diffCwp = true;
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if(shared_data->cansave != thread->readMiscReg(MISCREG_CANSAVE))
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diffCansave = true;
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if(shared_data->canrestore !=
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thread->readMiscReg(MISCREG_CANRESTORE))
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diffCanrestore = true;
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if(shared_data->otherwin != thread->readMiscReg(MISCREG_OTHERWIN))
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diffOtherwin = true;
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if(shared_data->cleanwin != thread->readMiscReg(MISCREG_CLEANWIN))
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diffCleanwin = true;
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if (diffPC || diffInst || diffRegs || diffTpc || diffTnpc ||
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diffTstate || diffTt || diffHpstate ||
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diffHtstate || diffHtba || diffPstate || diffY ||
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diffCcr || diffTl || diffGl || diffAsi || diffPil ||
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diffCwp || diffCansave || diffCanrestore ||
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diffOtherwin || diffCleanwin) {
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outs << "Differences found between M5 and Legion:";
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if (diffPC)
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outs << " [PC]";
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@ -265,6 +398,44 @@ Trace::InstRecord::dump(ostream &outs)
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outs << " [Instruction]";
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if (diffRegs)
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outs << " [IntRegs]";
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if (diffTpc)
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outs << " [Tpc]";
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if (diffTnpc)
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outs << " [Tnpc]";
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if (diffTstate)
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outs << " [Tstate]";
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if (diffTt)
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outs << " [Tt]";
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if (diffHpstate)
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outs << " [Hpstate]";
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if (diffHtstate)
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outs << " [Htstate]";
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if (diffHtba)
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outs << " [Htba]";
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if (diffPstate)
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outs << " [Pstate]";
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if (diffY)
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outs << " [Y]";
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if (diffCcr)
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outs << " [Ccr]";
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if (diffTl)
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outs << " [Tl]";
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if (diffGl)
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outs << " [Gl]";
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if (diffAsi)
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outs << " [Asi]";
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if (diffPil)
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outs << " [Pil]";
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if (diffCwp)
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outs << " [Cwp]";
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if (diffCansave)
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outs << " [Cansave]";
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if (diffCanrestore)
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outs << " [Canrestore]";
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if (diffOtherwin)
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outs << " [Otherwin]";
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if (diffCleanwin)
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outs << " [Cleanwin]";
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outs << endl << endl;
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outs << right << setfill(' ') << setw(15)
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@ -280,29 +451,106 @@ Trace::InstRecord::dump(ostream &outs)
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<< staticInst->disassemble(m5Pc, debugSymbolTable)
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<< endl;
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StaticInstPtr legionInst = StaticInst::decode(makeExtMI(shared_data->instruction, thread));
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StaticInstPtr legionInst =
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StaticInst::decode(makeExtMI(shared_data->instruction,
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thread));
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outs << setfill(' ') << setw(15)
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<< " Legion Inst: "
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<< "0x" << setw(8) << setfill('0') << hex
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<< shared_data->instruction
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<< legionInst->disassemble(lgnPc, debugSymbolTable)
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<< endl;
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<< endl << endl;
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printSectionHeader(outs, "General State");
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printColumnLabels(outs);
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printRegPair(outs, "HPstate",
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thread->readMiscReg(MISCREG_HPSTATE),
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shared_data->hpstate | (1 << 11));
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printRegPair(outs, "Htba",
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thread->readMiscReg(MISCREG_HTBA),
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shared_data->htba);
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printRegPair(outs, "Pstate",
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thread->readMiscReg(MISCREG_PSTATE),
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shared_data->pstate);
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printRegPair(outs, "Y",
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thread->readMiscReg(MISCREG_Y),
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shared_data->y);
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printRegPair(outs, "Ccr",
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thread->readMiscReg(MISCREG_CCR),
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shared_data->ccr);
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printRegPair(outs, "Tl",
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thread->readMiscReg(MISCREG_TL),
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shared_data->tl);
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printRegPair(outs, "Gl",
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thread->readMiscReg(MISCREG_GL),
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shared_data->gl);
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printRegPair(outs, "Asi",
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thread->readMiscReg(MISCREG_ASI),
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shared_data->asi);
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printRegPair(outs, "Pil",
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thread->readMiscReg(MISCREG_PIL),
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shared_data->pil);
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printRegPair(outs, "Cwp",
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thread->readMiscReg(MISCREG_CWP),
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shared_data->cwp);
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printRegPair(outs, "Cansave",
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thread->readMiscReg(MISCREG_CANSAVE),
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shared_data->cansave);
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printRegPair(outs, "Canrestore",
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thread->readMiscReg(MISCREG_CANRESTORE),
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shared_data->canrestore);
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printRegPair(outs, "Otherwin",
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thread->readMiscReg(MISCREG_OTHERWIN),
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shared_data->otherwin);
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printRegPair(outs, "Cleanwin",
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thread->readMiscReg(MISCREG_CLEANWIN),
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shared_data->cleanwin);
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outs << endl;
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for (int i = 1; i <= MaxTL; i++) {
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printLevelHeader(outs, i);
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printColumnLabels(outs);
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thread->setMiscReg(MISCREG_TL, i);
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printRegPair(outs, "Tpc",
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thread->readMiscReg(MISCREG_TPC),
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shared_data->tpc[i]);
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printRegPair(outs, "Tnpc",
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thread->readMiscReg(MISCREG_TNPC),
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shared_data->tnpc[i]);
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printRegPair(outs, "Tstate",
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thread->readMiscReg(MISCREG_TSTATE),
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shared_data->tstate[i]);
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printRegPair(outs, "Tt",
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thread->readMiscReg(MISCREG_TT),
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shared_data->tt[i]);
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printRegPair(outs, "Htstate",
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thread->readMiscReg(MISCREG_HTSTATE),
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shared_data->htstate[i]);
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}
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thread->setMiscReg(MISCREG_TL, oldTl);
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outs << endl;
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printSectionHeader(outs, "General Purpose Registers");
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static const char * regtypes[4] = {"%g", "%o", "%l", "%i"};
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for(int y = 0; y < 4; y++)
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{
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for(int x = 0; x < 8; x++)
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{
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outs << regtypes[y] << x << " " ;
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outs << "0x" << hex << setw(16) << thread->readIntReg(y*8+x);
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if (thread->readIntReg(y*8 + x) != shared_data->intregs[y*8+x])
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char label[8];
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sprintf(label, "%s%d", regtypes[y], x);
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printRegPair(outs, label,
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thread->readIntReg(y*8+x),
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shared_data->intregs[y*8+x]);
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/*outs << regtypes[y] << x << " " ;
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outs << "0x" << hex << setw(16)
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<< thread->readIntReg(y*8+x);
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if (thread->readIntReg(y*8 + x)
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!= shared_data->intregs[y*8+x])
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outs << " X ";
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else
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outs << " | ";
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outs << "0x" << setw(16) << hex << shared_data->intregs[y*8+x]
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<< endl;
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outs << "0x" << setw(16) << hex
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<< shared_data->intregs[y*8+x]
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<< endl;*/
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}
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}
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fatal("Differences found between Legion and M5\n");
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