Commit graph

63 commits

Author SHA1 Message Date
Ron Dreslinski
727dea78c4 Update configs for cpu_id
tests/configs/o3-timing-mp.py:
tests/configs/simple-atomic-mp.py:
tests/configs/simple-timing-mp.py:
    Update config for cpu_id

--HG--
extra : convert_revision : 32a1971997920473164ba12f2b121cb640bad7ac
2006-10-09 17:31:58 -04:00
Ron Dreslinski
b9fb4d4870 Make memtest work with 8 memtesters
src/mem/physical.cc:
    Update comment to match memtest use
src/python/m5/objects/PhysicalMemory.py:
    Make memtester have a way to connect functionally
tests/configs/memtest.py:
    Properly create 8 memtesters and connect them to the memory system

--HG--
extra : convert_revision : e5a2dd9c8918d58051b553b5c6a14785d48b34ca
2006-10-09 17:13:50 -04:00
Ron Dreslinski
6c7ab02682 Update the Memtester, commit a config file/test for it.
src/cpu/SConscript:
    Add memtester to the compilation environment.
    Someone who knows this better should make the MemTest a cpu model parameter.

    For now attached with the build of o3 cpu.
src/cpu/memtest/memtest.cc:
src/cpu/memtest/memtest.hh:
    Update Memtest for new mem system
src/python/m5/objects/MemTest.py:
    Update memtest python description

--HG--
extra : convert_revision : d6a63e08fda0975a7abfb23814a86a0caf53e482
2006-10-09 00:26:10 -04:00
Steve Reinhardt
d3fba5aa30 Implement Alpha LL/SC support for SimpleCPU (Atomic & Timing)
and PhysicalMemory.  *No* support for caches or O3CPU.
Note that properly setting cpu_id on all CPUs is now required
for correct operation.

src/arch/SConscript:
src/base/traceflags.py:
src/cpu/base.hh:
src/cpu/simple/atomic.cc:
src/cpu/simple/timing.cc:
src/cpu/simple/timing.hh:
src/mem/physical.cc:
src/mem/physical.hh:
src/mem/request.hh:
src/python/m5/objects/BaseCPU.py:
tests/configs/simple-atomic.py:
tests/configs/simple-timing.py:
tests/configs/tsunami-simple-atomic-dual.py:
tests/configs/tsunami-simple-atomic.py:
tests/configs/tsunami-simple-timing-dual.py:
tests/configs/tsunami-simple-timing.py:
    Implement Alpha LL/SC support for SimpleCPU (Atomic & Timing)
    and PhysicalMemory.  *No* support for caches or O3CPU.

--HG--
extra : convert_revision : 6ce982d44924cc477e049b9adf359818908e72be
2006-10-08 10:53:24 -07:00
Kevin Lim
8949d813ff Clean up configs.
configs/common/FSConfig.py:
configs/common/SysPaths.py:
configs/example/fs.py:
configs/example/se.py:
tests/configs/o3-timing-mp.py:
tests/configs/o3-timing.py:
    Clean up configs by removing FullO3Config and instead using default values.
src/python/m5/objects/FUPool.py:
    Add in default FUPool.
src/python/m5/objects/O3CPU.py:
    Use defaults better.  Also set checker parameters, and fix up a config bug.

--HG--
extra : convert_revision : 5fd0c000143f4881f10a9a575c3810dc97cb290b
2006-10-08 01:12:42 -04:00
Ron Dreslinski
212c5aefb5 Fixes for functional accesses to use the snoop path.
And small other tweaks to snooping coherence.

src/mem/cache/base_cache.hh:
    Make timing response at the time of send.
src/mem/cache/cache.hh:
src/mem/cache/cache_impl.hh:
    Update probe interface to be bi-directional for functional accesses
src/mem/packet.hh:
    Add the function to create an atomic response to a given request

--HG--
extra : convert_revision : 04075a117cf30a7df16e6d3ce485543cc77d4ca6
2006-10-05 23:28:03 -04:00
Ron Dreslinski
45f881a4ce First pass at snooping stuff that compiles and doesn't break.
Still need:
-Handle NACK's on the recieve side
-Distinguish top level caches
-Handle repsonses from caches failing the fast path
-Handle BusError and propogate it
-Fix the invalidate packet associated with snooping in the cache

src/mem/bus.cc:
    Make sure to snoop on functional accesses
src/mem/cache/base_cache.cc:
    Wait to make a request into a response until it is ready to be issued
src/mem/cache/base_cache.hh:
    Support range changes for snoops
    Set up snoop responses for cache->cache transfers
src/mem/cache/cache_impl.hh:
    Only access the cache if it wasn't satisfied by cache->cache transfer
    Handle snoop phases (detect block, then snoop)
    Fix functional access to work properly (still need to fix snoop path for functional accesses)

--HG--
extra : convert_revision : 4c25f11d7a996c1f56f4f7b55dde87a344e5fdf8
2006-10-05 21:10:03 -04:00
Steve Reinhardt
2c9dc949ce Add o3-timing configuration for ALPHA_SE "Hello world" tests.
build_opts/ALPHA_SE:
    Add O3CPU to default CPU model list.
tests/SConscript:
    Add o3-timing configuration.

--HG--
extra : convert_revision : 378feacc07cefdaf1e2df9080c9b9d5d71e4d2a1
2006-09-01 17:59:36 -04:00
Ron Dreslinski
689eb39d48 Merge zizzer:/z/m5/Bitkeeper/newmem
into  zizzer.eecs.umich.edu:/.automount/zazzer/z/rdreslin/m5bk/newmem

src/python/m5/objects/BaseCPU.py:
    Merge duplicate change

--HG--
extra : convert_revision : 214e57999ee78aadfc86e1f0b7198ff0d981ce16
2006-08-21 13:20:35 -04:00
Steve Reinhardt
4e3164617a Add caches in, fix cpu.mem param
--HG--
extra : convert_revision : 486283d83786807c72bb4601e4b9613b55d8802c
2006-08-18 00:16:23 -04:00
Ron Dreslinski
6eebfda2d9 Fix the caches not working in the regression
src/python/m5/objects/BaseCPU.py:
    Make mem parameter a MemObject, not just a PhysicalMemory
    Fix a reference not using self
tests/configs/simple-atomic.py:
    Set the mem paramter
tests/configs/simple-timing.py:
    Set the mem parameter

--HG--
extra : convert_revision : 6bd9df36831a1c5bafc9e88ab945c2ebe91db785
2006-08-16 23:46:54 -04:00
Steve Reinhardt
f3976f9cd9 More regression updates.
Get rid of caches in simple-timing config for now.

tests/SConscript:
    another line for diff to ignore
tests/configs/simple-timing.py:
    turn off caches for now
tests/quick/00.hello/ref/mips/linux/simple-atomic/m5stats.txt:
tests/quick/00.hello/ref/mips/linux/simple-atomic/stdout:
tests/quick/00.hello/ref/sparc/linux/simple-atomic/m5stats.txt:
tests/quick/00.hello/ref/sparc/linux/simple-atomic/stdout:
    update for inst/tick rate (old one was debug?)
tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.ini:
tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.out:
tests/quick/20.eio-short/ref/alpha/eio/simple-timing/m5stats.txt:
tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stderr:
tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stdout:
    works now (no caches)

--HG--
extra : convert_revision : 472030f63297346976db6274a78235c93d4eef8e
2006-08-16 18:48:15 -04:00
Steve Reinhardt
bd4ccd6e39 Finish test clean-up & reorg.
configs/common/FSConfig.py:
    Add default Machine() param
configs/example/fs.py:
configs/example/se.py:
    make it work again
src/python/m5/objects/BaseCPU.py:
    Make mem PhysicalMemory so that a Parent.any proxy works well
src/sim/process.cc:
    Increase default stack size so we don't get an
    'increasing stack' message on 'hello world'
tests/SConscript:
    Add full list of current configs.
tests/configs/simple-atomic.py:
tests/configs/simple-timing.py:
    don't need SEConfig anymore
tests/quick/00.hello/test.py:
tests/quick/20.eio-short/test.py:
    fix
tests/run.py:
    move configs to separate dir

--HG--
rename : configs/test/fs.py => configs/example/fs.py
rename : configs/test/test.py => configs/example/se.py
rename : tests/simple-atomic.py => tests/configs/simple-atomic.py
rename : tests/simple-timing.py => tests/configs/simple-timing.py
rename : tests/linux-mpboot/ref/alpha/atomic/config.ini => tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini
rename : tests/linux-mpboot/ref/alpha/atomic/config.out => tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.out
rename : tests/linux-mpboot/ref/alpha/atomic/console.system.sim_console => tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/console.system.sim_console
rename : tests/linux-mpboot/ref/alpha/atomic/m5stats.txt => tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/m5stats.txt
rename : tests/linux-mpboot/ref/alpha/atomic/stderr => tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stderr
rename : tests/linux-mpboot/ref/alpha/atomic/stdout => tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stdout
rename : tests/linux-boot/ref/alpha/atomic/config.ini => tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini
rename : tests/linux-boot/ref/alpha/atomic/config.out => tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.out
rename : tests/linux-boot/ref/alpha/atomic/console.system.sim_console => tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/console.system.sim_console
rename : tests/linux-boot/ref/alpha/atomic/m5stats.txt => tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/m5stats.txt
rename : tests/linux-boot/ref/alpha/atomic/stderr => tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stderr
rename : tests/linux-boot/ref/alpha/atomic/stdout => tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stdout
rename : tests/linux-mpboot/ref/alpha/timing/config.ini => tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini
rename : tests/linux-mpboot/ref/alpha/timing/config.out => tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.out
rename : tests/linux-mpboot/ref/alpha/timing/console.system.sim_console => tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/console.system.sim_console
rename : tests/linux-mpboot/ref/alpha/timing/m5stats.txt => tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/m5stats.txt
rename : tests/linux-mpboot/ref/alpha/timing/stderr => tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stderr
rename : tests/linux-mpboot/ref/alpha/timing/stdout => tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stdout
rename : tests/test-progs/hello/bin/mips/linux/hello_mips => tests/test-progs/hello/bin/mips/linux/hello
rename : tests/test-progs/hello/bin/sparc/bin => tests/test-progs/hello/bin/sparc/linux/hello
extra : convert_revision : d68ee6d7eefa7ba57370f3fb3c3589f86a6ea6b4
2006-08-16 14:42:44 -04:00