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Update configs for cpu_id

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tests/configs/o3-timing-mp.py:
tests/configs/simple-atomic-mp.py:
tests/configs/simple-timing-mp.py:
    Update config for cpu_id

--HG--
extra : convert_revision : 32a1971997920473164ba12f2b121cb640bad7ac
This commit is contained in:
Ron Dreslinski 2006-10-09 17:31:58 -04:00
parent c4dba7a8ed
commit 727dea78c4
3 changed files with 5 additions and 5 deletions
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4
tests/configs/o3-timing-mp.py
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@ -54,7 +54,7 @@ class L2(BaseCache):
write_buffers = 8
nb_cores = 4
cpus = [ DetailedO3CPU() for i in xrange(nb_cores) ]
cpus = [ DetailedO3CPU(cpu_id=i) for i in xrange(nb_cores) ]
# system simulated
system = System(cpu = cpus, physmem = PhysicalMemory(), membus =
@ -86,5 +86,5 @@ system.physmem.port = system.membus.port
root = Root( system = system )
root.system.mem_mode = 'timing'
root.trace.flags="Bus Cache"
#root.trace.flags="Bus Cache"
#root.trace.flags = "BusAddrRanges"

4
tests/configs/simple-atomic-mp.py
View file

@ -52,10 +52,10 @@ class L2(BaseCache):
write_buffers = 8
nb_cores = 4
cpus = [ AtomicSimpleCPU() for i in xrange(nb_cores) ]
cpus = [ AtomicSimpleCPU(cpu_id=i) for i in xrange(nb_cores) ]
# system simulated
system = System(cpu = cpus, physmem = PhysicalMemory(), membus =
system = System(cpu = cpus, physmem = PhysicalMemory(range = AddrRange('1024MB')), membus =
Bus())
# l2cache & bus

2
tests/configs/simple-timing-mp.py
View file

@ -52,7 +52,7 @@ class L2(BaseCache):
write_buffers = 8
nb_cores = 4
cpus = [ TimingSimpleCPU() for i in xrange(nb_cores) ]
cpus = [ TimingSimpleCPU(cpu_id=i) for i in xrange(nb_cores) ]
# system simulated
system = System(cpu = cpus, physmem = PhysicalMemory(), membus =