Commit graph

9197 commits

Author SHA1 Message Date
Andreas Hansson
b6aa6d55eb clang/gcc: Fix compilation issues with clang 3.0 and gcc 4.6
This patch addresses a number of minor issues that cause problems when
compiling with clang >= 3.0 and gcc >= 4.6. Most importantly, it
avoids using the deprecated ext/hash_map and instead uses
unordered_map (and similarly so for the hash_set). To make use of the
new STL containers, g++ and clang has to be invoked with "-std=c++0x",
and this is now added for all gcc versions >= 4.6, and for clang >=
3.0. For gcc >= 4.3 and <= 4.5 and clang <= 3.0 we use the tr1
unordered_map to avoid the deprecation warning.

The addition of c++0x in turn causes a few problems, as the
compiler is more stringent and adds a number of new warnings. Below,
the most important issues are enumerated:

1) the use of namespaces is more strict, e.g. for isnan, and all
   headers opening the entire namespace std are now fixed.

2) another other issue caused by the more stringent compiler is the
   narrowing of the embedded python, which used to be a char array,
   and is now unsigned char since there were values larger than 128.

3) a particularly odd issue that arose with the new c++0x behaviour is
   found in range.hh, where the operator< causes gcc to complain about
   the template type parsing (the "<" is interpreted as the beginning
   of a template argument), and the problem seems to be related to the
   begin/end members introduced for the range-type iteration, which is
   a new feature in c++11.

As a minor update, this patch also fixes the build flags for the clang
debug target that used to be shared with gcc and incorrectly use
"-ggdb".
2012-04-14 05:43:31 -04:00
Steve Reinhardt
29482e90ba SCons: restore Werror option in src/SConscript
Partial backout of cset 8b223e308b08.

Although it's great that there's currently no need
for Werror=false in the current tree, some of us
have uncommitted code that still needs this option.
2012-04-13 08:13:04 -07:00
Andreas Hansson
4bd61abb51 Stats: Update with use of std::map for ordered iteration in Ruby
This patch updates the stats to reflect the changes due to the use of
std::map instead of the hash map order-dependent iteration in Ruby.
2012-04-12 08:35:56 -04:00
Andreas Hansson
c9634d9b38 Ruby: Ensure order-dependent iteration uses an ordered map
This patch fixes a bug in Ruby that caused non-deterministic
simulation when changing the underlying hash map implementation. The
reason is order-dependent behaviour in combination with iteration over
the hash map contents. The two locations where a sorted container is
assumed are now changed to make use of a std::map instead of the
unordered hash map.

With this change, the stats changes slightly and the follow-on
changeset will update the relevant statistics.
2012-04-12 08:35:49 -04:00
Gabe Black
15ca4f2fc7 tests: Fix building unit tests.
Unit tests shouldn't build in gem5's main function because they have thier
own.
2012-04-09 23:20:30 -07:00
Brad Beckmann
3fd425124c rubytest: remove spurious printf 2012-04-06 17:51:47 -07:00
Brad Beckmann
697fd8987b regress: ruby random tester and hammer stats updates 2012-04-06 16:16:24 -07:00
Brad Beckmann
8c1494112f ruby: set SimpleTiming as the default cpu 2012-04-06 13:47:08 -07:00
Lisa Hsu
a5287efc58 slicc: Controllers attached to Sequencers no longer have to be named L1Cache. 2012-04-06 13:47:08 -07:00
Brad Beckmann
5dfa4cd3f5 sim-ruby: checkpointing fixes and dependent eventq improvements
Fixes checkpointing with respect to lost events after swapping event queues.
Also adds DPRINTFs to better understand what's going on when Ruby serializes
and unserializes.
2012-04-06 13:47:07 -07:00
Brad Beckmann
70682e36dd slicc: fixed error message when the type has no inheritance 2012-04-06 13:47:07 -07:00
Brad Beckmann
5838ed7290 MOESI_hammer: tbe allocation and dependent wakeup fixes 2012-04-06 13:47:07 -07:00
Brad Beckmann
f12961bf25 python: added __nonzero__ function to SimObject Bool params 2012-04-06 13:47:07 -07:00
Brad Beckmann
f050ebe3a8 MOESI_hammer: fixed bug with single cpu + flushes, then modified the regression tester to check this functionality 2012-04-06 13:47:06 -07:00
Brad Beckmann
0a9f4b950f rubytest: seperated read and write ports.
This patch allows the ruby tester to support protocols where the i-cache and d-cache
are managed by seperate controllers.
2012-04-06 13:47:06 -07:00
Andreas Hansson
b00949d88b MEM: Enable multiple distributed generalized memories
This patch removes the assumption on having on single instance of
PhysicalMemory, and enables a distributed memory where the individual
memories in the system are each responsible for a single contiguous
address range.

All memories inherit from an AbstractMemory that encompasses the basic
behaviuor of a random access memory, and provides untimed access
methods. What was previously called PhysicalMemory is now
SimpleMemory, and a subclass of AbstractMemory. All future types of
memory controllers should inherit from AbstractMemory.

To enable e.g. the atomic CPU and RubyPort to access the now
distributed memory, the system has a wrapper class, called
PhysicalMemory that is aware of all the memories in the system and
their associated address ranges. This class thus acts as an
infinitely-fast bus and performs address decoding for these "shortcut"
accesses. Each memory can specify that it should not be part of the
global address map (used e.g. by the functional memories by some
testers). Moreover, each memory can be configured to be reported to
the OS configuration table, useful for populating ATAG structures, and
any potential ACPI tables.

Checkpointing support currently assumes that all memories have the
same size and organisation when creating and resuming from the
checkpoint. A future patch will enable a more flexible
re-organisation.

--HG--
rename : src/mem/PhysicalMemory.py => src/mem/AbstractMemory.py
rename : src/mem/PhysicalMemory.py => src/mem/SimpleMemory.py
rename : src/mem/physical.cc => src/mem/abstract_mem.cc
rename : src/mem/physical.hh => src/mem/abstract_mem.hh
rename : src/mem/physical.cc => src/mem/simple_mem.cc
rename : src/mem/physical.hh => src/mem/simple_mem.hh
2012-04-06 13:46:31 -04:00
Tushar Krishna
dbe1608fd5 NetworkTest: remove unnecessary memory allocation 2012-04-05 17:51:26 -04:00
Nilay Vaish
4f4a710457 Config: corrects the way Ruby attaches to the DMA ports
With recent changes to the memory system, a port cannot be assigned a peer
port twice. While making use of the Ruby memory system in FS mode, DMA
ports were assigned peer twice, once for the classic memory system
and once for the Ruby memory system. This patch removes this double
assignment of peer ports.
2012-04-05 11:09:19 -05:00
Andreas Hansson
f1a6090613 Ruby: Fix the example configurations option parsing
This patch fixes the, currently broken, Ruby example scripts to
reflect the changes in the parsing of command-line options.
2012-04-05 10:45:26 -04:00
Andreas Hansson
aab2001ab7 Python: Make the All proxy traverse SimObject children as well
This patch changes the behaviour of the All proxy parameter to not
only consider the direct children, but also do a pre-order depth-first
traversal of the object tree and append all results from the
children.

This is used in a later patch to find all the memories in the system,
independent of where they are located in the hierarchy.
2012-04-05 10:44:35 -04:00
Andreas Hansson
a8e6adb0b1 Atomic: Remove the physmem_port and access memory directly
This patch removes the physmem_port from the Atomic CPU and instead
uses the system pointer to access the physmem when using the fastmem
option. The system already keeps track of the physmem and the valid
memory address ranges, and with this patch we merely make use of that
existing functionality. As a result of this change, the overloaded
getMasterPort in the Atomic CPU can be removed, thus unifying the CPUs.
2012-04-03 03:50:14 -04:00
Gabe Black
a7859f7e45 X86: Fix address size handling so real mode works properly.
Virtual (pre-segmentation) addresses are truncated based on address size, and
any non-64 bit linear address is truncated to 32 bits. This means that real
mode addresses aren't truncated down to 16 bits after their segment bases are
added in.
2012-03-31 12:27:33 -07:00
Andreas Hansson
74043c4f5c MEM: Remove legacy DRAM in preparation for memory updates
This patch removes the DRAM memory class in preparation for updates to
the memory system, with the first one introducing an abstract memory
class, and removing the assumption of a single physical memory.
2012-03-30 12:57:48 -04:00
Andreas Hansson
a128ba7cd1 Ruby: Remove the physMemPort and instead access memory directly
This patch removes the physMemPort from the RubySequencer and instead
uses the system pointer to access the physmem. The system already
keeps track of the physmem and the valid memory address ranges, and
with this patch we merely make use of that existing functionality. The
memory is modified so that it is possible to call the access functions
(atomic and functional) without going through the port, and the memory
is allowed to be unconnected, i.e. have no ports (since Ruby does not
attach it like the conventional memory system).
2012-03-30 09:42:36 -04:00
William Wang
f9d403a7b9 MEM: Introduce the master/slave port sub-classes in C++
This patch introduces the notion of a master and slave port in the C++
code, thus bringing the previous classification from the Python
classes into the corresponding simulation objects and memory objects.

The patch enables us to classify behaviours into the two bins and add
assumptions and enfore compliance, also simplifying the two
interfaces. As a starting point, isSnooping is confined to a master
port, and getAddrRanges to slave ports. More of these specilisations
are to come in later patches.

The getPort function is not getMasterPort and getSlavePort, and
returns a port reference rather than a pointer as NULL would never be
a valid return value. The default implementation of these two
functions is placed in MemObject, and calls fatal.

The one drawback with this specific patch is that it requires some
code duplication, e.g. QueuedPort becomes QueuedMasterPort and
QueuedSlavePort, and BusPort becomes BusMasterPort and BusSlavePort
(avoiding multiple inheritance). With the later introduction of the
port interfaces, moving the functionality outside the port itself, a
lot of the duplicated code will disappear again.
2012-03-30 09:40:11 -04:00
Andreas Hansson
a14013af3a CPU: Unify initMemProxies across CPUs and simulation modes
This patch unifies where initMemProxies is called, in the init()
method of each BaseCPU subclass, before TheISA::initCPU is
called. Moreover, it also ensures that initMemProxies is called in
both full-system and syscall-emulation mode, thus unifying also across
the modes. An additional check is added in the ThreadState to ensure
that initMemProxies is only called once.
2012-03-30 09:38:35 -04:00
Nilay Vaish
390cfc7be9 Config: Change the way options are added
I am not too happy with the way options are added in files se.py and fs.py
currently. This patch moves all the options to the file Options.py, functions
from which are called when required.
2012-03-28 11:01:53 -05:00
Nilay Vaish
6ca3af8ecf Config: Move setWorkCountOptions() to Simulation.py
The function is presently defined in FSConfig.py, which does not seem to be
the correct place for it.
2012-03-27 18:23:21 -05:00
Andreas Hansson
9d7c715c46 range_map: Enable const find and iteration
This patch adds const access functions to the range_map to enable its use
in a const context, similar to the STL container classes.
2012-03-26 05:37:00 -04:00
Andreas Hansson
312efd742e Power: Change bitfield name to avoid conflicts with range_map
This patch changes the name of a bitfield from W to W_FIELD to avoid
clashes with W being used as a class (typename) in the templatized
range_map. It also changes L to L_FIELD to avoid future problems. The
problem manifestes itself when the CPU includes a header that in turn
includes range_map.hh. The relevant parts of the decoder are updated.
2012-03-26 05:35:24 -04:00
Andreas Hansson
ca9790a2db Ruby: Fix Set::print for 32-bit hosts
This patch fixes a compilation error caused by a length mismatch on
32-bit hosts. The ifdef and sprintf is replaced by a csprintf.
2012-03-23 06:54:25 -04:00
Andreas Hansson
9727b1be18 MEM: Unify bus access methods and prepare for master/slave split
This patch unifies the recvFunctional, recvAtomic and recvTiming to
all be based on a similar structure: 1) extract information about the
incoming packet, 2) send it out to the appropriate snoopers, 3)
determine where it is going, and 4) forward it to the right
destination. The naming of variables across the different access
functions is now consistent as well.

Additionally, the patch introduces the member functions releaseBus and
retryWaiting to better distinguish between the two cases when we
should tell a sender to retry. The first case is when the bus goes
from busy to idle, and the second case is when it receives a retry
from a destination that did not immediatelly accept a packet.

As a very minor change, the MMU debug flag is no longer used in the bus.
2012-03-22 06:37:21 -04:00
Andreas Hansson
c2d2ea99e3 MEM: Split SimpleTimingPort into PacketQueue and ports
This patch decouples the queueing and the port interactions to
simplify the introduction of the master and slave ports. By separating
the queueing functionality from the port itself, it becomes much
easier to distinguish between master and slave ports, and still retain
the queueing ability for both (without code duplication).

As part of the split into a PacketQueue and a port, there is now also
a hierarchy of two port classes, QueuedPort and SimpleTimingPort. The
QueuedPort is useful for ports that want to leave the packet
transmission of outgoing packets to the queue and is used by both
master and slave ports. The SimpleTimingPort inherits from the
QueuedPort and adds the implemention of recvTiming and recvFunctional
through recvAtomic.

The PioPort and MessagePort are cleaned up as part of the changes.

--HG--
rename : src/mem/tport.cc => src/mem/packet_queue.cc
rename : src/mem/tport.hh => src/mem/packet_queue.hh
2012-03-22 06:36:27 -04:00
Andreas Hansson
fb395b56dd Scons: Remove Werror=False in SConscript files
This patch removes the overriding of "-Werror" in a handful of
cases. The code compiles with gcc 4.6.3 and clang 3.0 without any
warnings, and thus without any errors. There are no functional changes
introduced by this patch. In the future, rather than ypassing
"-Werror", address the warnings.
2012-03-22 06:34:50 -04:00
Andreas Hansson
12742835bc Python: Fix a conditional expression that requires Python 2.5
This patch changes a conditional expression to a conventional if/else
block, which does not require Python >= 2.5.
2012-03-21 19:02:03 -04:00
Ali Saidi
3c666083c6 ARM: Update stats for IT and conditional branch changes 2012-03-21 10:36:45 -05:00
Nathanael Premillieu
8e2a8fbb7e ARM: Fix case where cond/uncond control is mis-specified 2012-03-21 10:34:06 -05:00
Ali Saidi
ed8ed6e761 ARM: Clean up condCodes in IT blocks. 2012-03-21 10:34:06 -05:00
Geoffrey Blake
a64319f764 ARM: IT doesn't need to be serializing. 2012-03-21 10:34:06 -05:00
Andrew Lukefahr
b4e5be717d O3: Fix sizing of decode to rename skid buffer. 2012-03-21 10:34:06 -05:00
Koan-Sin Tan
0376422c0b ARM: Add RTC to PBX System 2012-03-21 10:34:05 -05:00
Brian Grayson
565c1de4a8 O3: Fix size of skid buffer between fetch and decode when widths are different 2012-03-21 10:34:05 -05:00
Ali Saidi
1981ba21ca ARM: Fix uninitialized value in ARM RTC model. 2012-03-21 10:34:05 -05:00
Tushar Krishna
c9e4bca8d8 Garnet: Stats at vnet granularity + code cleanup
This patch
(1) Moves redundant code from fixed and flexible networks to BaseGarnetNetwork.
(2) Prints network stats at vnet granularity.
2012-03-19 17:34:17 -04:00
Andreas Hansson
72538294fb gcc: Clean-up of non-C++0x compliant code, first steps
This patch cleans up a number of minor issues aiming to get closer to
compliance with the C++0x standard as interpreted by gcc and clang
(compile with std=c++0x and -pedantic-errors). In particular, the
patch cleans up enums where the last item was succeded by a comma,
namespaces closed by a curcly brace followed by a semi-colon, and the
use of the GNU-extension typeof (replaced by templated functions). It
does not address variable-length arrays, zero-size arrays, anonymous
structs, range expressions in switch statements, and the use of long
long. The generated CPU code also has a large number of issues that
remain to be fixed, mainly related to overflows in implicit constant
conversion (due to shifts).
2012-03-19 06:36:09 -04:00
Andreas Hansson
adb8621031 clang: Fix recently introduced clang compilation errors
This patch makes the code compile with clang 2.9 and 3.0 again by
making two very minor changes. Firt, it maintains a strict typing in
the forward declaration of the BaseCPUParams. Second, it adds a
FullSystemInt flag of the type unsigned int next to the boolean
FullSystem flag. The FullSystemInt variable can be used in
decode-statements (expands to switch statements) in the instruction
decoder.
2012-03-19 06:35:04 -04:00
Andreas Hansson
a444a6f8d6 scripts: Fix to ensure that port connection count is always set
This patch ensures that the port connection count is set to zero in those
cases when the port is not connected.
2012-03-19 06:34:02 -04:00
Nilay Vaish
f02eec93d6 ruby_fs.py: Add call to createInterruptController() 2012-03-16 07:47:03 -05:00
Nilay Vaish
13a5e9b7b5 FSConfig.py: fix a typo makeLinuxAlphaRubySystem 2012-03-16 07:46:45 -05:00
Marc Orr
24fe7cdf00 build: remove implicit-cache setting of scons from recent build faster patch 2012-03-16 03:29:07 -07:00