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Ruby: Remove the physMemPort and instead access memory directly

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This patch removes the physMemPort from the RubySequencer and instead
uses the system pointer to access the physmem. The system already
keeps track of the physmem and the valid memory address ranges, and
with this patch we merely make use of that existing functionality. The
memory is modified so that it is possible to call the access functions
(atomic and functional) without going through the port, and the memory
is allowed to be unconnected, i.e. have no ports (since Ruby does not
attach it like the conventional memory system).
This commit is contained in:
Andreas Hansson 2012-03-30 09:42:36 -04:00
parent f9d403a7b9
commit a128ba7cd1
12 changed files with 17 additions and 62 deletions
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4
configs/ruby/MESI_CMP_directory.py
View file

@ -96,8 +96,6 @@ def create_system(options, system, piobus, dma_devices, ruby_system):
cpu_seq = RubySequencer(version = i,
icache = l1i_cache,
dcache = l1d_cache,
physMemPort = system.physmem.port,
physmem = system.physmem,
ruby_system = ruby_system)
l1_cntrl.sequencer = cpu_seq
@ -169,8 +167,6 @@ def create_system(options, system, piobus, dma_devices, ruby_system):
# Create the Ruby objects associated with the dma controller
#
dma_seq = DMASequencer(version = i,
physMemPort = system.physmem.port,
physmem = system.physmem,
ruby_system = ruby_system)
dma_cntrl = DMA_Controller(version = i,

4
configs/ruby/MI_example.py
View file

@ -88,8 +88,6 @@ def create_system(options, system, piobus, dma_devices, ruby_system):
cpu_seq = RubySequencer(version = i,
icache = cache,
dcache = cache,
physMemPort = system.physmem.port,
physmem = system.physmem,
ruby_system = ruby_system)
l1_cntrl.sequencer = cpu_seq
@ -142,8 +140,6 @@ def create_system(options, system, piobus, dma_devices, ruby_system):
# Create the Ruby objects associated with the dma controller
#
dma_seq = DMASequencer(version = i,
physMemPort = system.physmem.port,
physmem = system.physmem,
ruby_system = ruby_system)
dma_cntrl = DMA_Controller(version = i,

4
configs/ruby/MOESI_CMP_directory.py
View file

@ -96,8 +96,6 @@ def create_system(options, system, piobus, dma_devices, ruby_system):
cpu_seq = RubySequencer(version = i,
icache = l1i_cache,
dcache = l1d_cache,
physMemPort = system.physmem.port,
physmem = system.physmem,
ruby_system = ruby_system)
l1_cntrl.sequencer = cpu_seq
@ -166,8 +164,6 @@ def create_system(options, system, piobus, dma_devices, ruby_system):
# Create the Ruby objects associated with the dma controller
#
dma_seq = DMASequencer(version = i,
physMemPort = system.physmem.port,
physmem = system.physmem,
ruby_system = ruby_system)
dma_cntrl = DMA_Controller(version = i,

4
configs/ruby/MOESI_CMP_token.py
View file

@ -118,8 +118,6 @@ def create_system(options, system, piobus, dma_devices, ruby_system):
cpu_seq = RubySequencer(version = i,
icache = l1i_cache,
dcache = l1d_cache,
physMemPort = system.physmem.port,
physmem = system.physmem,
ruby_system = ruby_system)
l1_cntrl.sequencer = cpu_seq
@ -190,8 +188,6 @@ def create_system(options, system, piobus, dma_devices, ruby_system):
# Create the Ruby objects associated with the dma controller
#
dma_seq = DMASequencer(version = i,
physMemPort = system.physmem.port,
physmem = system.physmem,
ruby_system = ruby_system)
dma_cntrl = DMA_Controller(version = i,

4
configs/ruby/MOESI_hammer.py
View file

@ -111,8 +111,6 @@ def create_system(options, system, piobus, dma_devices, ruby_system):
cpu_seq = RubySequencer(version = i,
icache = l1i_cache,
dcache = l1d_cache,
physMemPort = system.physmem.port,
physmem = system.physmem,
ruby_system = ruby_system)
l1_cntrl.sequencer = cpu_seq
@ -202,8 +200,6 @@ def create_system(options, system, piobus, dma_devices, ruby_system):
# Create the Ruby objects associated with the dma controller
#
dma_seq = DMASequencer(version = i,
physMemPort = system.physmem.port,
physmem = system.physmem,
ruby_system = ruby_system)
dma_cntrl = DMA_Controller(version = i,

2
configs/ruby/Network_test.py
View file

@ -88,8 +88,6 @@ def create_system(options, system, piobus, dma_devices, ruby_system):
cpu_seq = RubySequencer(icache = cache,
dcache = cache,
physMemPort = system.physmem.port,
physmem = system.physmem,
using_network_tester = True,
ruby_system = ruby_system)

5
configs/ruby/Ruby.py
View file

@ -97,10 +97,7 @@ def create_system(options, system, piobus = None, dma_devices = []):
# Create a port proxy for connecting the system port. This is
# independent of the protocol and kept in the protocol-agnostic
# part (i.e. here).
sys_port_proxy = RubyPortProxy(version = 0,
physMemPort = system.physmem.port,
physmem = system.physmem,
ruby_system = ruby)
sys_port_proxy = RubyPortProxy(ruby_system = ruby)
# Give the system port proxy a SimObject parent without creating a
# full-fledged controller
system.sys_port_proxy = sys_port_proxy

12
src/mem/physical.cc
View file

@ -115,12 +115,12 @@ PhysicalMemory::PhysicalMemory(const Params *p)
void
PhysicalMemory::init()
{
if (ports.empty()) {
fatal("PhysicalMemory object %s is unconnected!", name());
}
for (PortIterator pi = ports.begin(); pi != ports.end(); ++pi) {
(*pi)->sendRangeChange();
for (PortIterator p = ports.begin(); p != ports.end(); ++p) {
if (!(*p)->isConnected()) {
fatal("PhysicalMemory port %s is unconnected!\n", (*p)->name());
} else {
(*p)->sendRangeChange();
}
}
}

4
src/mem/physical.hh
View file

@ -198,9 +198,11 @@ class PhysicalMemory : public MemObject
void virtual init();
unsigned int drain(Event *de);
protected:
Tick doAtomicAccess(PacketPtr pkt);
void doFunctionalAccess(PacketPtr pkt);
protected:
virtual Tick calculateLatency(PacketPtr pkt);
public:

29
src/mem/ruby/system/RubyPort.cc
View file

@ -45,14 +45,14 @@
#include "mem/protocol/AccessPermission.hh"
#include "mem/ruby/slicc_interface/AbstractController.hh"
#include "mem/ruby/system/RubyPort.hh"
#include "sim/system.hh"
RubyPort::RubyPort(const Params *p)
: MemObject(p), m_version(p->version), m_controller(NULL),
m_mandatory_q_ptr(NULL),
pio_port(csprintf("%s-pio-port", name()), this),
m_usingRubyTester(p->using_ruby_tester), m_request_cnt(0),
physMemPort(csprintf("%s-physMemPort", name()), this),
drainEvent(NULL), physmem(p->physmem), ruby_system(p->ruby_system),
drainEvent(NULL), ruby_system(p->ruby_system), system(p->system),
waitingOnSequencer(false), access_phys_mem(p->access_phys_mem)
{
assert(m_version != -1);
@ -84,10 +84,6 @@ RubyPort::getMasterPort(const std::string &if_name, int idx)
return pio_port;
}
if (if_name == "physMemPort") {
return physMemPort;
}
// used by the x86 CPUs to connect the interrupt PIO and interrupt slave
// port
if (if_name != "master") {
@ -471,7 +467,7 @@ RubyPort::M5Port::recvFunctional(PacketPtr pkt)
// The following command performs the real functional access.
// This line should be removed once Ruby supplies the official version
// of data.
ruby_port->physMemPort.sendFunctional(pkt);
ruby_port->system->physmem->doFunctionalAccess(pkt);
}
// turn packet around to go back to requester if response expected
@ -568,10 +564,6 @@ RubyPort::getDrainCount(Event *de)
count += pio_port.drain(de);
DPRINTF(Config, "count after pio check %d\n", count);
}
if (physMemPort.isConnected()) {
count += physMemPort.drain(de);
DPRINTF(Config, "count after physmem check %d\n", count);
}
for (CpuPortIter p = slave_ports.begin(); p != slave_ports.end(); ++p) {
count += (*p)->drain(de);
@ -654,7 +646,7 @@ RubyPort::M5Port::hitCallback(PacketPtr pkt)
DPRINTF(RubyPort, "Hit callback needs response %d\n", needsResponse);
if (accessPhysMem) {
ruby_port->physMemPort.sendAtomic(pkt);
ruby_port->system->physmem->doAtomicAccess(pkt);
} else if (needsResponse) {
pkt->makeResponse();
}
@ -696,18 +688,7 @@ RubyPort::M5Port::getAddrRanges()
bool
RubyPort::M5Port::isPhysMemAddress(Addr addr)
{
AddrRangeList physMemAddrList =
ruby_port->physMemPort.getSlavePort().getAddrRanges();
for (AddrRangeIter iter = physMemAddrList.begin();
iter != physMemAddrList.end();
iter++) {
if (addr >= iter->start && addr <= iter->end) {
DPRINTF(RubyPort, "Request found in %#llx - %#llx range\n",
iter->start, iter->end);
return true;
}
}
return false;
return ruby_port->system->isMemory(addr);
}
unsigned

4
src/mem/ruby/system/RubyPort.hh
View file

@ -175,8 +175,6 @@ class RubyPort : public MemObject
uint16_t m_port_id;
uint64_t m_request_cnt;
PioPort physMemPort;
/** Vector of M5 Ports attached to this Ruby port. */
typedef std::vector<M5Port*>::iterator CpuPortIter;
std::vector<M5Port*> slave_ports;
@ -184,8 +182,8 @@ class RubyPort : public MemObject
Event *drainEvent;
PhysicalMemory* physmem;
RubySystem* ruby_system;
System* system;
//
// Based on similar code in the M5 bus. Stores pointers to those ports

3
src/mem/ruby/system/Sequencer.py
View file

@ -38,13 +38,12 @@ class RubyPort(MemObject):
master = VectorMasterPort("CPU master port")
version = Param.Int(0, "")
pio_port = MasterPort("Ruby_pio_port")
physmem = Param.PhysicalMemory("")
physMemPort = MasterPort("port to physical memory")
using_ruby_tester = Param.Bool(False, "")
using_network_tester = Param.Bool(False, "")
access_phys_mem = Param.Bool(True,
"should the rubyport atomically update phys_mem")
ruby_system = Param.RubySystem("")
system = Param.System(Parent.any, "system object")
class RubyPortProxy(RubyPort):
type = 'RubyPortProxy'