Commit graph

9197 commits

Author SHA1 Message Date
Ali Saidi
041b932428 mem: fix bug with CopyStringOut and null string termination. 2012-05-10 18:04:27 -05:00
Ali Saidi
c02dc07424 Cache: restructure code that actually isn't a loop 2012-05-10 18:04:27 -05:00
Ali Saidi
e029941bda dev: use correct delete operation in SimpleDisk 2012-05-10 18:04:27 -05:00
Ali Saidi
d9b484b41a ARM: Fix incorrect use of not operators in arm devices 2012-05-10 18:04:27 -05:00
Ali Saidi
5745665509 gem5: assert before indexing intro arrays to verify bounds 2012-05-10 18:04:27 -05:00
Ali Saidi
4f66bcdd2e gem5: fix some iterator use and erase bugs 2012-05-10 18:04:27 -05:00
Ali Saidi
5ecaf30219 gem5: fix a number of use after free issues 2012-05-10 18:04:27 -05:00
Ali Saidi
da10fbf5ca base: fix a invalid ?: operator 2012-05-10 18:04:27 -05:00
Ali Saidi
8cee4dacc8 gem5: Fix a number of incorrect case statements 2012-05-10 18:04:26 -05:00
Ali Saidi
798403b689 ARM: Update m5op assembly for thumb compilation. 2012-05-10 18:04:26 -05:00
Ali Saidi
413ba1fdaf stats: track if the stats have been enabled and prevent requesting master id
Track the point in the initialization where statistics have been registered.
After this point registering new masterIds can no longer work as some
SimObjects may have sized stats vectors based on the previous value. If someone
tries to register a masterId after this point the simulator executes fatal().
2012-05-10 18:04:26 -05:00
Ali Saidi
f6895e8bd4 Cache: Panic if you attempt to create a checkpoint with a cache in the system 2012-05-10 18:04:26 -05:00
Pritha Ghoshal
dc456d8166 IGbE: Fix writeback conditions for i8254x GbE in updated data sheet.
An older revision of the data sheet specified that txdctl.gran was 1 the granularity was
based on cache block and gran being 0 is based on descriptor count. The newer version of
the data sheet reverses this errata
2012-05-10 18:04:26 -05:00
Nathan Binkert
4a644767c5 stats: update stats for no_value -> nan
Lots of accumulated older changes too.
2012-05-09 11:52:14 -07:00
Nathan Binkert
55411f7f71 stats: use nan instead of no_value 2012-05-09 11:51:42 -07:00
Andreas Hansson
ab23e29487 MEM: Add the communication monitor
This patch adds a communication monitor MemObject that can be inserted
between a master and slave port to provide a range of statistics about
the communication passing through it. The communication monitor is
non-invasive and does not change any properties or timing of the
packets, with the exception of adding a sender state to be able to
track latency. The statistics are only collected in timing mode (not
atomic) to avoid slowing down any fast forwarding.

An example of the statistics captured by the monitor are: read/write
burst lengths, bandwidth, request-response latency, outstanding
transactions, inter transaction time, transaction count, and address
distribution. The monitor can be used in combination with periodic
resetting and dumping of stats (through schedStatEvent) to study the
behaviour over time.

In future patches, a selection of convenience scripts will be added to
aid in visualising the statistics collected by the monitor.
2012-05-09 04:37:45 -04:00
Steve Reinhardt
18e8d7ed2d scons: allow override of SWIG binary on command line 2012-05-08 07:49:57 -07:00
Andreas Hansson
692351ea34 MEM: Do not forward uncacheable to bus snoopers
This patch adds a guarding if-statement to avoid forwarding
uncacheable requests (or rather their corresponding request packets)
to bus snoopers. These packets should never have any effect on the
caches, and thus there is no need to forward them to the snoopers.
2012-05-08 05:15:52 -04:00
Andreas Hansson
15e28c5ba6 Ruby: Ensure snoop requests are sent using sendTimingSnoopReq
This patch fixes a bug that caused snoop requests to be placed in a
packet queue. Instead, the packet is now sent immediately using
sendTimingSnoopReq, thus bypassing the packet queue and any normal
responses waiting to be sent.
2012-05-04 03:30:02 -04:00
Nilay Vaish
e8f56bdf45 Regression: Move x86 fs ruby simulation from quick to long
--HG--
rename : tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/config.ini => tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/config.ini
rename : tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/ruby.stats => tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/ruby.stats
rename : tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/simerr => tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/simerr
rename : tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/simout => tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/simout
rename : tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/stats.txt => tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/stats.txt
rename : tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/system.pc.com_1.terminal => tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/system.pc.com_1.terminal
2012-05-03 23:18:13 -05:00
Jayneel Gandhi
39cbae9581 Config: Fix help msg for option --mem-size 2012-05-03 05:17:29 -05:00
Andreas Hansson
3fea59e162 MEM: Separate requests and responses for timing accesses
This patch moves send/recvTiming and send/recvTimingSnoop from the
Port base class to the MasterPort and SlavePort, and also splits them
into separate member functions for requests and responses:
send/recvTimingReq, send/recvTimingResp, and send/recvTimingSnoopReq,
send/recvTimingSnoopResp. A master port sends requests and receives
responses, and also receives snoop requests and sends snoop
responses. A slave port has the reciprocal behaviour as it receives
requests and sends responses, and sends snoop requests and receives
snoop responses.

For all MemObjects that have only master ports or slave ports (but not
both), e.g. a CPU, or a PIO device, this patch merely adds more
clarity to what kind of access is taking place. For example, a CPU
port used to call sendTiming, and will now call
sendTimingReq. Similarly, a response previously came back through
recvTiming, which is now recvTimingResp. For the modules that have
both master and slave ports, e.g. the bus, the behaviour was
previously relying on branches based on pkt->isRequest(), and this is
now replaced with a direct call to the apprioriate member function
depending on the type of access. Please note that send/recvRetry is
still shared by all the timing accessors and remains in the Port base
class for now (to maintain the current bus functionality and avoid
changing the statistics of all regressions).

The packet queue is split into a MasterPort and SlavePort version to
facilitate the use of the new timing accessors. All uses of the
PacketQueue are updated accordingly.

With this patch, the type of packet (request or response) is now well
defined for each type of access, and asserts on pkt->isRequest() and
pkt->isResponse() are now moved to the appropriate send member
functions. It is also worth noting that sendTimingSnoopReq no longer
returns a boolean, as the semantics do not alow snoop requests to be
rejected or stalled. All these assumptions are now excplicitly part of
the port interface itself.
2012-05-01 13:40:42 -04:00
Nilay Vaish
8966e6d36d Regression: Stats update for X86 Ruby FS test
The kernel originally used to generate the stats is different from the one
at use on zizzer. This patch updates the stats with the correct kernel in
use.
2012-04-30 03:47:22 -05:00
Gabe Black
2c85cf41a2 X86: Fix the IMUL_R_P_I macroop.
The disp displacement was left off the load microop so the wrong value was
used.
2012-04-29 02:26:34 -07:00
Vince Weaver
03a91b0533 X86: Fix up the open system call's flags. 2012-04-29 00:31:03 -07:00
Vince Weaver
38799e2b3f X86: Make gem5 ignore a bunch of syscalls. 2012-04-29 00:30:56 -07:00
Nilay Vaish
04a558bb41 Garnet: Correct computation of link utilization
The computation for link utilization was incorrect for the flexible network.
The utilization was being divided twice by the total time.
2012-04-28 16:57:31 -05:00
Nilay Vaish
6ea7fcc54a util/regress: Add the missing comma in the list of builds 2012-04-26 20:28:45 -05:00
Nilay Vaish
86f248e2a7 Regression: Add a test for x86 timing full system ruby simulation 2012-04-25 22:43:36 -05:00
Nilay Vaish
c3dad222e3 Ruby: Remove extra statements from Sequencer 2012-04-25 17:52:03 -05:00
Andreas Hansson
beed20d7bc MEM: Use base class Master/SlavePort pointers in the bus
This patch makes some rather trivial simplifications to the bus in
that it changes the use of BusMasterPort and BusSlavePort pointers to
simply use MasterPort and SlavePort (iterators are also updated
accordingly).

This change is a step towards a future patch that introduces a
separation of the interface and the structural port itself.
2012-04-25 10:45:23 -04:00
Andreas Hansson
4c92708b48 MEM: Add the PortId type and a corresponding id field to Port
This patch introduces the PortId type, moves the definition of
INVALID_PORT_ID to the Port class, and also gives every port an id to
reflect the fact that each element in a vector port has an
identifier/index.

Previously the bus and Ruby testers (and potentially other users of
the vector ports) added the id field in their port subclasses, and now
this functionality is always present as it is moved to the base class.
2012-04-25 10:41:23 -04:00
Andreas Hansson
79750fc575 clang/gcc: Use STL hash function for int64_t and uint64_t
This patch changes the guards for the definition of hash functions to
also exclude the int64_t and uint64_t hash functions in the case we
are using the c++0x STL <unordered_map> (and <hash>) or the TR1
version of the same header. Previously the guard only covered the hash
function for strings, but it seems there is also no need to define a
hash for the 64-bit integer types, and this has caused problems with
builds on 32-bit Ubuntu.
2012-04-25 08:57:18 -04:00
Gabe Black
312b6fe43b X86: Update stats for the slightly changed TLB behavior. 2012-04-24 00:48:57 -07:00
Gabe Black
64bf90dca3 X86: Clear out duplicate TLB entries when adding a new one.
It's possible for two page table walks to overlap which will go in the same
place in the TLB's trie. They would land on top of each other, so this change
adds some code which detects if an address already matches an entry and if so
throws away the new one.
2012-04-24 00:48:41 -07:00
Gabe Black
74ca8a3cd0 ISA: Put parser generated files in a "generated" directory.
This is to avoid collision with non-generated files.
2012-04-23 12:00:41 -07:00
Steve Reinhardt
867ff2b5f1 scons: update minimum SWIG version to 1.3.34
We should try to keep this synced with the wiki
(which I also just updated, but which was
previously inconsistent).
2012-04-23 09:25:16 -07:00
Gabe Black
80c6cdae18 base: Include cassert in trie.hh.
trie.hh uses assert, but it wasn't explicitly including cassert.
2012-04-22 05:20:44 -07:00
Gabe Black
29329e61b7 X86: Report an error if there's no kernel object, don't blindly use it.
This way the user gets a nice message instead of a less nice segfault.
2012-04-21 15:00:23 -07:00
Jayneel Gandhi
7aa57ac882 SE Config: Changed se.py to support multithreaded mode
Multithreaded programs did not run by just specifying the binary once on the
command line of SE mode.The default mode is multi-programmed mode. Added
check in SE mode to run multi-threaded programs in case only one program is
specified with multiple CPUS. Default mode is still multi-programmed mode.
2012-04-17 16:12:41 -05:00
Jayneel Gandhi
b5b9d2ad3e Config: Add command line options for disk image and memory size
Added the options to Options.py for FS mode with backward compatibility. It is
good to provide an option to specify the disk image and the memory size from
command line since a lot of disk images are created to support different
benchmark suites as well as per user needs. Change in program also leads to
change in memory requirements. These options provide the interface to provide
both disk image and memory size from the command line and gives more
flexibility.
2012-04-16 17:51:26 -05:00
Gabe Black
a5187f9d96 CPU: Tidy up some formatting and a DPRINTF in the simple CPU base class.
Put the { on the same line as the if and put a space between the if and the
open paren. Also, use the # format modifier which puts a 0x in front of hex
values automatically. If the ExtMachInst type isn't integral and actually
prints something more complicated, the # falls away harmlessly and we aren't
left with a phantom 0x followed by a bunch of unrelated text.
2012-04-15 12:35:49 -07:00
Gabe Black
8fe112d61b X86: Fix a tiny typo in the load/store microop constructor.
The parameter is _machInst, which is very similar to the member machInst. If
machInst is used to pass the parameter to a lower level constructor, what
really happens is that machInst is set to whatever it already happened to be,
effectively leaving it uninitialized.
2012-04-15 01:07:39 -07:00
Gabe Black
aacb676220 X86: Use the AddrTrie class to implement the TLB.
This change also adjusts the TlbEntry class so that it stores the number of
address bits wide a page is rather than its size in bytes. In other words,
instead of storing 4K for a 4K page, it stores 12. 12 is easy to turn into 4K,
but it's a little harder going the other way.
2012-04-14 23:24:18 -07:00
Gabe Black
d6031d72df sim: Update some comments in trie.hh that were meant to go in the last change. 2012-04-14 23:22:57 -07:00
Gabe Black
c4c27ded42 sim: A trie data structure specifically to speed up paging lookups.
This change adds a trie data structure which stores an arbitrary pointer type
based on an address and a number of relevant bits. Then lookups can be done
against the trie where the tree is traversed and the first legitimate match
found is returned.
2012-04-14 23:19:34 -07:00
Andreas Hansson
14edc6013d Ruby: Use MasterPort base-class pointers where possible
This patch simplifies future patches by changing the pointer type used
in a number of the Ruby testers to use MasterPort instead of using a
derived CpuPort class. There is no reason for using the more
specialised pointers, and there is no longer a need to do any casting.

With the latest changes to the tester, organising ports as readers and
writes, things got a bit more complicated, and the "type" now had to
be removed to be able to fall back to using MasterPort rather than
CpuPort.
2012-04-14 05:46:59 -04:00
Andreas Hansson
750f33a901 MEM: Remove the Broadcast destination from the packet
This patch simplifies the packet by removing the broadcast flag and
instead more firmly relying on (and enforcing) the semantics of
transactions in the classic memory system, i.e. request packets are
routed from a master to a slave based on the address, and when they
are created they have neither a valid source, nor destination. On
their way to the slave, the request packet is updated with a source
field for all modules that multiplex packets from multiple master
(e.g. a bus). When a request packet is turned into a response packet
(at the final slave), it moves the potentially populated source field
to the destination field, and the response packet is routed through
any multiplexing components back to the master based on the
destination field.

Modules that connect multiplexing components, such as caches and
bridges store any existing source and destination field in the sender
state as a stack (just as before).

The packet constructor is simplified in that there is no longer a need
to pass the Packet::Broadcast as the destination (this was always the
case for the classic memory system). In the case of Ruby, rather than
using the parameter to the constructor we now rely on setDest, as
there is already another three-argument constructor in the packet
class.

In many places where the packet information was printed as part of
DPRINTFs, request packets would be printed with a numeric "dest" that
would always be -1 (Broadcast) and that field is now removed from the
printing.
2012-04-14 05:45:55 -04:00
Andreas Hansson
dccca0d3a9 MEM: Separate snoops and normal memory requests/responses
This patch introduces port access methods that separates snoop
request/responses from normal memory request/responses. The
differentiation is made for functional, atomic and timing accesses and
builds on the introduction of master and slave ports.

Before the introduction of this patch, the packets belonging to the
different phases of the protocol (request -> [forwarded snoop request
-> snoop response]* -> response) all use the same port access
functions, even though the snoop packets flow in the opposite
direction to the normal packet. That is, a coherent master sends
normal request and receives responses, but receives snoop requests and
sends snoop responses (vice versa for the slave). These two distinct
phases now use different access functions, as described below.

Starting with the functional access, a master sends a request to a
slave through sendFunctional, and the request packet is turned into a
response before the call returns. In a system without cache coherence,
this is all that is needed from the functional interface. For the
cache-coherent scenario, a slave also sends snoop requests to coherent
masters through sendFunctionalSnoop, with responses returned within
the same packet pointer. This is currently used by the bus and caches,
and the LSQ of the O3 CPU. The send/recvFunctional and
send/recvFunctionalSnoop are moved from the Port super class to the
appropriate subclass.

Atomic accesses follow the same flow as functional accesses, with
request being sent from master to slave through sendAtomic. In the
case of cache-coherent ports, a slave can send snoop requests to a
master through sendAtomicSnoop. Just as for the functional access
methods, the atomic send and receive member functions are moved to the
appropriate subclasses.

The timing access methods are different from the functional and atomic
in that requests and responses are separated in time and
send/recvTiming are used for both directions. Hence, a master uses
sendTiming to send a request to a slave, and a slave uses sendTiming
to send a response back to a master, at a later point in time. Snoop
requests and responses travel in the opposite direction, similar to
what happens in functional and atomic accesses. With the introduction
of this patch, it is possible to determine the direction of packets in
the bus, and no longer necessary to look for both a master and a slave
port with the requested port id.

In contrast to the normal recvFunctional, recvAtomic and recvTiming
that are pure virtual functions, the recvFunctionalSnoop,
recvAtomicSnoop and recvTimingSnoop have a default implementation that
calls panic. This is to allow non-coherent master and slave ports to
not implement these functions.
2012-04-14 05:45:07 -04:00
Andreas Hansson
b9bc530ad2 Regression: Add ANSI colours to highlight test status
This patch adds a very basic pretty-printing of the test status
(passed or failed) to highlight failing tests even more: green for
passed, and red for failed. The printing only uses ANSI it the target
output is a tty and supports ANSI colours. Hence, any regression
scripts that are outputting to files or sending e-mails etc should
still be fine.
2012-04-14 05:44:27 -04:00