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Author SHA1 Message Date
Gabe Black
13a8752c11 Put in provisions for rd, rdpr, rdhpr, wr, wrpr, and wrhpr to disassemble properly. 
--HG--
extra : convert_revision : f2cad8a5879999438ba9b05f15a91320e7a4cc4a
 2006-11-10 15:28:58 -05:00
Gabe Black
7bf1c8981d Made the annul of unconditional conditional branches behave properly, added code to read and write the strand_sts_reg, and made restored a Priv instruction. 
--HG--
extra : convert_revision : 386512215f7243d230717c369217f8d2f9ada935
 2006-11-10 15:27:06 -05:00
Gabe Black
27b43b62b7 Fixed up the code that prints out registers to take into account microregisters. 
--HG--
extra : convert_revision : 6809de467e4500ce34447c0544caf0ba04af81e7
 2006-11-10 15:25:52 -05:00
Gabe Black
8390e46311 Tweaked debug output. 
--HG--
extra : convert_revision : cd33b7c1ebdbefd42f18c1435b2519d06d9914a6
 2006-11-10 15:25:03 -05:00
Gabe Black
cee4d1c113 Touched up faults, and made POR actually do something. 
--HG--
extra : convert_revision : 38951352edbfc423fb6767a9aac49a703578c0ac
 2006-11-10 15:24:10 -05:00
Kevin Lim
b5e68fb546 Merge ktlim@zizzer:/bk/newmem 
into  zamp.eecs.umich.edu:/z/ktlim2/clean/o3-merge/newmem

--HG--
extra : convert_revision : 0c2db1e1b5fdb91c1ac5705ab872a6bfb575a67a
 2006-11-10 12:44:15 -05:00
Kevin Lim
264f9ce374 Also include a function to form the input path. 
--HG--
extra : convert_revision : d2141e3b8c56296fbbe2c4c1ceb80616f269884a
 2006-11-10 12:39:43 -05:00
Kevin Lim
8ccd99e341 Try to setup commands properly. 
--HG--
extra : convert_revision : 9f4af3c5f52841b10e9f17c48470716703a1be67
 2006-11-10 12:28:23 -05:00
Kevin Lim
f593c8a8e2 Change up some warnings to DPRINTFs. 
--HG--
extra : convert_revision : b3e9fa094d68f608865dedfc9f3f4125a20fd748
 2006-11-10 12:25:08 -05:00
Kevin Lim
73581bf801 Merge ktlim@zizzer:/bk/newmem 
into  zamp.eecs.umich.edu:/z/ktlim2/clean/newmem-busfix

--HG--
extra : convert_revision : 56cb7fe3be5b63bd89b48ac6cb88b47d13b4c137
 2006-11-10 12:14:38 -05:00
Gabe Black
9ef51f2dba Actually finished moving the register file stuff around. 
--HG--
extra : convert_revision : 786735ecea8ff480db6b3754ac5daa562938d988
 2006-11-10 05:49:16 -05:00
Gabe Black
9731fb3fd7 Moved the Alpha float regfile into it's own regfile and got rid of constants.hh and isa_traits.cc 
--HG--
extra : convert_revision : 55afd7d21c276906520da375b3bbb563be420880
 2006-11-10 05:29:05 -05:00
Gabe Black
b4dfbf3aab Split out alpha integer register file into it's own files. 
--HG--
extra : convert_revision : 164bdcec2860c5dca3f0f11d189781b88dd717cb
 2006-11-10 04:54:25 -05:00
Gabe Black
71dc49c785 The reset function of the MiscRegFile really resets it now. This function is called from the class's constructor. 
--HG--
extra : convert_revision : 4e7a40ffe0a9a71fd1b2b171d9c0dcac50e1a1fe
 2006-11-10 04:33:41 -05:00
Gabe Black
dc6af9fbf7 Set the ASI register to be something explicitly so that simulation is deterministic. 
--HG--
extra : convert_revision : 38cd06f946fc0cc22288f71f567e77ce8fdfea99
 2006-11-10 04:14:25 -05:00
Gabe Black
1d70dda6d7 Change exetrace code for working with my trace tool to use stream io rather than sprintf which was breaking on 64 bit hosts. 
--HG--
extra : convert_revision : 184d751392dfcc8c80ac1a6c0ebc3061ff0a3f20
 2006-11-10 04:11:46 -05:00
Gabe Black
4aea5deccb Fix up instructions to read and write control registers, and got rid of the control register fields which won't work on a big endian host. 
--HG--
extra : convert_revision : 1b518873b6e1a073b58cbe27642537d5ae3a604d
 2006-11-10 04:02:39 -05:00
Gabe Black
232c3f1b27 Moved the Alpha MiscRegFile into it's own file, and got rid of the Alpha specific DepTag constants. 
--HG--
extra : convert_revision : e4af5e2fb2a6953f8837ad9bda309b7d6fa7abfb
 2006-11-09 21:30:48 -05:00
Gabe Black
50462c15aa Fix a couple uninitialized variables. 
--HG--
extra : convert_revision : d17d28a9520524e5f56bd79beb9b2be6ce76a22f
 2006-11-09 19:24:35 -05:00
Ali Saidi
cb172d0332 Get SPARC to the point that it starts running. Add ability to load the ROM bin files, cleanup lockstep printing a bit 
Since we don't have a platform yet, you need to comment out the default responder stuff in Bus.py to make it work.

SConstruct:
    Add TARGET_ISA to the list of environment variables that end up in the build_env for python
configs/common/FSConfig.py:
    add a simple SPARC system to being testing with, you'll need to change makeLinuxAlphaSystem to makeSparcSystem in fs.py for now
src/SConscript:
    add a raw file object, at least until we get more info about how to compile openboot properly
src/arch/sparc/system.cc:
src/arch/sparc/system.hh:
    add parameters for ROM files (OBP/Reset/Hypervisor), a ROM, load files into ROM
src/base/loader/object_file.cc:
src/base/loader/object_file.hh:
    add option to try raw when nothing works
src/cpu/exetrace.cc:
    cleanup lockstep printing a little bit
src/cpu/m5legion_interface.h:
    change the instruction to be 32 bits because it is
src/mem/physical.cc:
    fix assert that doesn't work if memory starts somewhere above 0
src/python/m5/objects/BaseCPU.py:
    Add if statement to choose between sparc tlbs and alpha tlbs
src/python/m5/objects/System.py:
    Add a sparc system that sets the rom addresses correctly
src/python/m5/params.py:
    add the ability to add Addr() together

--HG--
extra : convert_revision : bbbd8a56134f2dda2728091f740e2f7119b0c4af
 2006-11-09 18:22:46 -05:00
Kevin Lim
6591ebb098 Merge ktlim@zizzer:/bk/newmem 
into  zamp.eecs.umich.edu:/z/ktlim2/clean/newmem-busfix

--HG--
extra : convert_revision : dafe2d4a032b277c219ea13faf20567c20c1f2f4
 2006-11-09 15:06:00 -05:00
Kevin Lim
0ba2cc6571 Clean up config scripts to not have to worry about attaching a cache only to the TimingCPU. Now the Atomic CPU works with caches. 
configs/common/Simulation.py:
    Atomic CPU now works properly with caches, so we don't have to do extra parsing to hook up caches only to the timing CPU.

    However the O3CPU must always use caches, so a check for that must still exist.

    Also change the switch_cpus to be placed at the system level, now that Steve changed how the IntrController gets its CPU.
configs/example/fs.py:
configs/example/se.py:
    Atomic CPU now handles caches.

--HG--
extra : convert_revision : 534ded558ef96cafd76b4b5c5317bd8f4d05076e
 2006-11-09 15:05:13 -05:00
Nathan Binkert
f4aa4e43c4 Factor out all of the encumbered stuff into separate SConscript 
files so the directories can easily be deleted.
Remove the FullCPU from the ALL_CPU_LIST and only add it if
it exists.

--HG--
extra : convert_revision : b16f56bb92a0063803c5099732dc289fe4363768
 2006-11-09 08:43:35 -08:00
Kevin Lim
21f43bfc4b Be sure to populate the packet's finishTime field in the atomic timing case. 
--HG--
extra : convert_revision : ef34818eb2dea5b3a8e754bf56745a7cd2497bf0
 2006-11-09 11:37:26 -05:00
Kevin Lim
0b0d5a282a Draining fixes. 
src/cpu/o3/cpu.cc:
    Handle draining properly when CPU isn't actually being used.
src/cpu/simple/atomic.cc:
    Be sure to set status properly when draining.
src/mem/bus.cc:
    Fix for draining.

--HG--
extra : convert_revision : d9796e6693e974f022159029fc9743c49a970c8f
 2006-11-09 11:33:44 -05:00
Gabe Black
081dd9e600 Merge zizzer.eecs.umich.edu:/bk/newmem/ 
into  zeep.eecs.umich.edu:/home/gblack/m5/newmemmemops

--HG--
extra : convert_revision : 0ab912df014cf1511e960e4058bee3eea047f9f6
 2006-11-08 16:52:44 -05:00
Lisa Hsu
32f676fed2 the tests assume -1 to signify MaxTick, that's changed, so fix that here. 
--HG--
extra : convert_revision : 73ff143ba3b733f80ab867fcd72489cd1ee49d76
 2006-11-08 16:49:59 -05:00
Gabe Black
f720029e97 Merge zizzer.eecs.umich.edu:/bk/newmem/ 
into  zeep.eecs.umich.edu:/home/gblack/m5/newmemmemops

--HG--
extra : convert_revision : dc165840841bdd88e40111b98d1be493441703f0
 2006-11-08 16:18:10 -05:00
Gabe Black
5b90922ad5 Put the MIPS stacktrace into the MipsISA namespace to fit with Alpha and SPARC. 
--HG--
extra : convert_revision : 86f5585fe9ceb2ee30836d35384ebcddc1357c2a
 2006-11-08 16:15:20 -05:00
Gabe Black
42c73c6a92 Make a function to say how big gdbregs is in bytes vs. regs. 
--HG--
extra : convert_revision : 10c50c2d45a8e510d71cccde520059363116da8a
 2006-11-08 15:31:52 -05:00
Lisa Hsu
74745cfeac Merge zizzer:/bk/newmem 
into  zed.eecs.umich.edu:/z/hsul/work/m5/newmem

--HG--
extra : convert_revision : 5f4b39beba9f672ba1741cb45f4c3cf853ce574b
 2006-11-08 15:07:31 -05:00
Ali Saidi
7c3d933cd6 Merge zizzer:/bk/newmem 
into  zeep.pool:/z/saidi/work/m5.newmem

--HG--
extra : convert_revision : 643e28482e6739bd264a9c2d69c17279853aa0c5
 2006-11-08 15:06:17 -05:00
Ali Saidi
100f9bfb0b DWARF2 symbol support seems to be broken on Solaris. Use stabs+ 
align the character arrays that are used by placement-new for classes lest we have an unaligned fault on SPARC/Solaris

src/SConscript:
    DWARF2 symbol support seems to be broken on Solaris. Use stabs+
src/base/statistics.hh:
    align the character arrays that are used by placement-new for classes lest we have an unaligned fault on SPARC/Solaris

--HG--
extra : convert_revision : bc875a4fdfb4553062d3278537bc32a5ab9b6cca
 2006-11-08 15:05:54 -05:00
Lisa Hsu
64c0d82dec simplify maxtick parsing in both the python and the c++. 
configs/common/Simulation.py:
    simplify maxtick code a little bit - instead of checking for -1, just set it at MaxTick.
src/python/m5/__init__.py:
    make a new m5 param called MaxTick.
src/sim/host.hh:
    fix the M5 def. of MaxTick
src/sim/main.cc:
    Simplify the MaxTick/num_cycles parsing within main.cc

--HG--
extra : convert_revision : f800addfbc1323591c2e05b892276b439b671668
 2006-11-08 15:05:23 -05:00
Lisa Hsu
5a46f336a1 make rcS files read from the m5 source directory, not /dist. 
--HG--
extra : convert_revision : 45a2dbf5b05b19dd60fbc3a5b10e9355c8351e3b
 2006-11-08 14:10:25 -05:00
Lisa Hsu
0a0d9cd3ab change to os.path.join like nate wanted. 
--HG--
extra : convert_revision : 6e8a0153adf04f0cc07904434e4cb6a83fe900eb
 2006-11-08 14:01:23 -05:00
Gabe Black
63bbc8929d First cut at full blown SPARC faults. There are a few details that are missing. 
--HG--
extra : convert_revision : 8023db1479cb9bf99fc9edfeb521c4e5b581f895
 2006-11-08 13:58:00 -05:00
Gabe Black
67b9a2ebd8 Move the check to see if you're in user mode into the isa directory. 
--HG--
extra : convert_revision : b5b7cdf4a5e5e54228c592093516bf18d0f7dbe6
 2006-11-08 13:55:48 -05:00
Kevin Lim
344f72dd62 Remove mem parameter. Should have been removed earlier. 
src/python/m5/objects/BaseCPU.py:
    These parameters should have been removed in an earlier push.

--HG--
extra : convert_revision : 781b39ca370361e9568b1af0be96ff5848b1f3f4
 2006-11-08 13:04:36 -05:00
Kevin Lim
e174ec1815 Merge ktlim@zizzer:/bk/newmem 
into  zamp.eecs.umich.edu:/z/ktlim2/clean/newmem-busfix

--HG--
extra : convert_revision : 29426cebe81ac077c1a83f50e914ff6955ce81d4
 2006-11-08 11:41:10 -05:00
Kevin Lim
99a8f00bb3 Update refs. 
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.out:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.out:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.out:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.out:
    Update config.
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stderr:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stderr:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stderr:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stderr:
    Update ref.

--HG--
extra : convert_revision : ca4fe7ff5bf9fcd112b703b88a5196a312c594ab
 2006-11-08 11:40:59 -05:00
Gabe Black
770b575c30 Sorted faults by the trap type constant, expanded their names, added in new faults for ua2005, and commented out ones which are apparently dropped. 
--HG--
extra : convert_revision : 32bd0c3a75d7c036ad4a3cb0bc1c32e0b6cb3d87
 2006-11-08 10:27:38 -05:00
Gabe Black
9375caa3f1 Fix for slightly mangled merge. 
--HG--
extra : convert_revision : 1dea04ca222dd423c3d462114bc1c65afa52825d
 2006-11-08 08:25:37 -05:00
Gabe Black
b82fa633bb Merge zeep.eecs.umich.edu:/home/gblack/m5/newmem 
into  zeep.eecs.umich.edu:/home/gblack/m5/newmemmemops

src/arch/sparc/faults.hh:
    Hand merged.

--HG--
extra : convert_revision : 1bcefe47fa98e878a0dfbcfa5869b5b171927911
 2006-11-08 08:19:52 -05:00
Gabe Black
635df9ba17 Major clean up of the fault code. 
--HG--
extra : convert_revision : eb7e016a127417cbb0e1e2c733b17f82469c2f24
 2006-11-08 08:12:19 -05:00
Gabe Black
f0c4d36649 The new global level is computed with min, not max. 
--HG--
extra : convert_revision : 6339c82d3655694445c3eb43e467b9aa6b4c8224
 2006-11-08 04:18:15 -05:00
Gabe Black
8cb7ac0900 Changed the getReg and setReg functions so that they work like netbsd. Apparently, gdb expects to do single stepping on its own, so those functions panic for SPARC. acc still needs to be implemented. 
--HG--
extra : convert_revision : c6e98e37b8ab3d6f8d6b3cd2c961faa65b08a179
 2006-11-08 02:13:47 -05:00
Gabe Black
f1a55570d3 Put the ProcessInfo and StackTrace objects into the ISA namespaces. 
--HG--
extra : convert_revision : 1626703583f02a1c9823874290462c1b6bdb6c3c
 2006-11-08 00:52:04 -05:00
Gabe Black
16a012e80d Stubs for SPARC's tlbs 
--HG--
extra : convert_revision : ba08da78693cc6f59f7358134f121f471910dbf6
 2006-11-08 00:32:40 -05:00
Gabe Black
746ceb93fd Replaced getArg with a SPARC implementation. 
--HG--
extra : convert_revision : ba31171a81b6c46de2997de2701d35fcf8c614b7
 2006-11-08 00:32:04 -05:00