dev/ns_gige.cc:
Make all DPRINTF statements take one line. If they need two lines,
break them up into separate statements. This makes grep much more
effective since *every* line will be prefixed by the cycle that the
trace message is from and the object that caused the message.
normalize some debugging statements so that searching is easier
(e.g. always say rxState, not rx state or receive state)
break into the debugger when a packet is dropped since we don't really
like dropping packets.
--HG--
extra : convert_revision : 9cf309ca2143a6b8c8215ac5dd6a31aae60173cd
whether or not the state machine is enabled rather than tracking the
specific instance of trying to halt the state machine.
dev/ns_gige.cc:
change back to tracking the state machine's enableness instead of
whether or not it is trying to halt. Also fix a major bug that
would cause the NIC to drop packets when the rx state machine was
idle, but enabled.
Fix a couple other bugs in the state machine where the idle interrupt
would happen at the wrong time.
Add a warning to deal with improper values of intrTick
dev/ns_gige.hh:
We need to keep track of whether the state machine is enabled
or not separately from the control register since the bits don't
always reflect the truth.
--HG--
extra : convert_revision : 20056b225fa62a0744473babfd693506aa5f29b2
machine too. The fifo may have been full and we want
to get another packet into it if we can.
--HG--
extra : convert_revision : 8f57294bd18f5eccb900118f2de83a4ccfd20dbb
and actually default to only storing a max of 96 bytes per
packet since that should be plenty to fit all of the headers in.
--HG--
extra : convert_revision : 0c4a6571d80536477ed166e695d957e39da0334e
argh!
dev/ns_gige.cc:
Exit the state machine so that we don't come right back where
we started and enter an infinite loop.
--HG--
extra : convert_revision : a5f2b5b5a692de6c80e4b02d7f9bc5d27fe17252
ticks for the most commonly accessed devices.
dev/baddev.cc:
Get rid of the constant cache access latency.
For unimportant devices, don't add any latency.
dev/ide_ctrl.cc:
dev/ide_ctrl.hh:
dev/ns_gige.cc:
dev/pciconfigall.cc:
dev/pciconfigall.hh:
dev/tsunami_cchip.cc:
dev/tsunami_cchip.hh:
dev/tsunami_io.cc:
dev/tsunami_io.hh:
dev/tsunami_pchip.cc:
dev/tsunami_pchip.hh:
dev/uart.cc:
dev/uart.hh:
make the cache access latency a parameter that is based on bus
ticks.
dev/io_device.cc:
dev/io_device.hh:
add an io latency variable
dev/ns_gige.hh:
this moved to io_device.hh
--HG--
extra : convert_revision : 4883130feeaef48abee492eddf0b8eb40eb94789
dev/ns_gige.cc:
make tx/rx fifo sizes a param. the default is 128K for each. also, make the state machine not move onto txFragRead if there is no room in the txfifo for data.
dev/ns_gige.hh:
make tx/rx fifo size a param
--HG--
extra : convert_revision : ed91eb31c2b21d4cdc6de87d8641df6197be5209
second translation (which is superfluous) doesn't work properly when
system memory is higher than 128MB
--HG--
extra : convert_revision : 9cdf6925689d376953b1aa071bcd1e2f06419202
dev/ns_gige.cc:
tell all outgoing dma events that this request is from the NIC
--HG--
extra : convert_revision : 62af17a2728a0ff729e7723dc29bd0d130ca5fe3
dev/ns_gige.cc:
transmit side checksum offloading doesn't need pseudo header generation, it just takes the pseudo header checksum and uses it.
--HG--
extra : convert_revision : 9741bd650415c18ed37b06a453b23610d028135b
Both rx/tx interrupts are now scheduled for the future to give the
linux kernel time to get out of its loop.
--HG--
extra : convert_revision : 8fee0a25fde0ce0545c924f8547bed460602e006
base/loader/elf_object.cc:
EM_ALPHA value isn't official, so perhaps we shouldn't use it
dev/alpha_console.cc:
dev/alpha_console.hh:
this change allows the use of old console code
--HG--
extra : convert_revision : cfacd64ae7fd2595158ca1a83ebcdb66ee7e119b
base/traceflags.py:
removed TsunamiUart/TlaserUart and added a plain Uart
dev/alpha_console.cc:
updated for new simconsole
dev/platform.hh:
added a uart member to platform
dev/simconsole.cc:
dev/simconsole.hh:
removed lots of legacy code, it should all be ours now.
converted tabs to 8 spaces
added our copyright
dev/tsunami.cc:
uses simconsole.hh rather than console.hh
dev/tsunami_cchip.cc:
dev/tsunami_io.cc:
never needed console.hh
dev/tsunami_io.hh:
this does need eventq.hh and it just happend to be working whenn console.hh was
included everywhere
dev/tsunamireg.h:
added a couple more 8250/16550 uart defines
dev/uart.cc:
new uart code, rewritten to support both tlaser and tsunami (both a 8250 and 8530
uart).
dev/uart.hh:
updated for new uart, legacy code removed
--HG--
rename : dev/console.cc => dev/simconsole.cc
rename : dev/console.hh => dev/simconsole.hh
rename : dev/tsunami_uart.cc => dev/uart.cc
rename : dev/tsunami_uart.hh => dev/uart.hh
extra : convert_revision : e663352d49d4c2d3c95643030cf73c0e85ba2f08
base/intmath.hh:
only need FloorLog2(size_t) on a mac, so ifdefed for this
dev/alpha_console.cc:
Actually allocate the alphaAccess struct.
--HG--
extra : convert_revision : 1f50b1a025c8ee728a9f3d2c603ea38347234f54
dev/alpha_console.cc:
rather than acessing a byte array for alpha access, access the members
**this requires an updated console**
dev/pcidev.cc:
correctly type all the pci data and store in in little endian no
matter what system we are on
dev/tsunami_uart.cc:
correct a bug with the data type.
kern/linux/linux_system.cc:
system type in hwprb needs to be endian happy as well.
--HG--
extra : convert_revision : 8de9bb69365b5d30fceaf4fa342a1639f92d7a83
base/traceflags.py:
added some more traceflags for ethernet to break it up better
dev/etherpkt.hh:
since we are not network host order, must reverse bytes for these typechecks.
also, overload isTcp/UdpPkt to take an argument so you don't have to reget the ip header if you've already got one.
dev/ns_gige.cc:
1) add some functions that reverse Endianness so we can generate adn evaluate checksum adn dprintf data accurately/more understandably
2) forget about the implementation of fifo fill/drain thresholds, it's not used by the driver much, nor does it matter with use sending/receiving in whole packets anyway.
get rid of teh associated variables.
3) get rid of txFifoCnt the variable, it's redundant and unnecessary, just use txFifoAvail.
4) change io_enable to ioEnable, just to be picky.
5) modify some DPRINTF's to be clearer, also added a lot, and spread them into better traceflag categories
6) fix the device bug! it's the intrTick = 0 at teh beginning of cpuInterrupt().
7) clear some bools in regsReset() so they don't holdover wrong state
8) fix pseudo header generation for Tcp checksumming to account for network order
dev/ns_gige.hh:
change io_enable to ioEnable, get rid of fill/drain thresh related variables and txFifoCnt, which is redundant
--HG--
extra : convert_revision : c538b75731f3c9e04354f57e6df9a40aeca5096d
base/inifile.cc:
Added mac os support and fixed a bug, on error we need to exit the
child process not return
base/intmath.hh:
gcc on macos wanted a seperate function for the size_t type
base/loader/elf_object.cc:
I'm not sure why this works under linux because it seems to return
the wrong value.
base/stats/text.cc:
added define/include for mac os x
cpu/exec_context.hh:
cpu/simple_cpu/simple_cpu.cc:
added endian conversion code
dev/alpha_console.cc:
rather than accessing a charecter array of varying size depending on
the access, lets actually do this properly.
dev/alpha_console.hh:
get rid of now nolonger used consoleData
dev/disk_image.cc:
We have to byte swap the data is some cases, added function to do that
dev/ethertap.cc:
added preproc directive for mac os
--HG--
extra : convert_revision : 2b5685765cfa2844926d7397f363d2788e3d640a
tests
dev/ide_ctrl.cc:
Formatting
dev/ide_disk.cc:
Remove some junk, add an assert to serialize, and add missing serialize
for command register.
--HG--
extra : convert_revision : 8f99857e32f278dd4e6f23deffc8047c6411d5b2
dev/ide_ctrl.cc:
generalize these #defs
dev/ide_ctrl.hh:
put these in pcireg.h
dev/ns_gige.cc:
do i need io_enable? and assert will fail if i actually need to implement it, which may give clue as to wehtehr i need to implmeent the mem_enable and bm_enable stuff.
dev/ns_gige.hh:
implement this in case it's needed
dev/pcireg.h:
put these defs in pcireg instead
--HG--
extra : convert_revision : 5e3581b5da17410f943907139bd479f15d2231e8
dev/ns_gige.cc:
fix serialization and move regsReset into the cc file
dev/ns_gige.hh:
put regsReset into cc instead of here in hh
--HG--
extra : convert_revision : 3a8796fa583e0765503104a9dbe28cc69f1a8fa9
busbridges. Also small fix for gcc 3.3.3.
dev/etherpkt.hh:
Gcc 3.3.3 wants assert.h to be include in this file.
dev/ide_ctrl.cc:
after unserialization we need to tell the busbridges what addresses to
respond to.
--HG--
extra : convert_revision : a421197a5be07761bdef571d0a9406d77788e270
3) add some new functions to etherpkt. 4) checkin the nice ping_linux.ini that i've been using.
dev/etherpkt.hh:
remove the packet headers nate hated so much.
also add some new functionality regarding packets, like isIpHdr(), etc.
dev/ns_gige.cc:
improve the code given the nice new functions offered in etherpkt
--HG--
extra : convert_revision : 2e27f5a8dca5323c0fa22d3c51af44a35f6be1a2
and started cleaning up config files.
arch/alpha/isa_desc:
Made implementation of cttz and ctlz more compact
base/remote_gdb.cc:
Added comment about PALcode debugger accesses
dev/baddev.cc:
dev/baddev.hh:
dev/ide_ctrl.cc:
dev/ide_ctrl.hh:
dev/pciconfigall.cc:
dev/pciconfigall.hh:
dev/tsunami_cchip.cc:
dev/tsunami_cchip.hh:
dev/tsunami_io.cc:
dev/tsunami_io.hh:
dev/tsunami_pchip.cc:
dev/tsunami_pchip.hh:
dev/tsunami_uart.cc:
dev/tsunami_uart.hh:
Cleaned up includes and changed device from FunctionalMemory to
PioDevice for detailed boot
dev/ns_gige.cc:
The ethernet dev uses two BARs, and the first bars size was being set
incorrectly.
dev/tsunamireg.h:
I don't know why we were using the superpage as the PCI memory addr.
Changed and works correctly with detailed boot.
--HG--
extra : convert_revision : b535e76612cb90b544305dc1aa8c5e0e774564bd
dev/tsunami_io.cc:
Timers don't need to be rescheduled cause they aren't scheduled by
the default constructor
--HG--
extra : convert_revision : afb68e4f0c4e2a2c98f0037e061752690080a503
dev/ide_ctrl.cc:
Properly serialize/unserialize the PciDev base class to get it to remap
the MMU
dev/ns_gige.cc:
dev/ns_gige.hh:
Remove the "addr" paramter from the constructor and change the device
to use PCI based MMU mappings only
dev/pciconfigall.cc:
Change comments
dev/pcidev.cc:
Properly setup the MMU after a serialize
--HG--
extra : convert_revision : 4b2e7ba58e3c24fac1ff6f80635e704d6ecc0eff
