more modifications for cross-endian support. linux now gets to pciconfig
dev/alpha_console.cc:
rather than acessing a byte array for alpha access, access the members
**this requires an updated console**
dev/pcidev.cc:
correctly type all the pci data and store in in little endian no
matter what system we are on
dev/tsunami_uart.cc:
correct a bug with the data type.
kern/linux/linux_system.cc:
system type in hwprb needs to be endian happy as well.
--HG--
extra : convert_revision : 8de9bb69365b5d30fceaf4fa342a1639f92d7a83
This commit is contained in:
Ali Saidi
parent
3f7b780af5
commit
231fac0a2b
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@ -80,6 +80,16 @@ AlphaConsole::AlphaConsole(const string &name, SimConsole *cons, SimpleDisk *d,
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alphaAccess->cpuClock = cpu->getFreq() / 1000000;
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alphaAccess->intrClockFrequency = platform->intrFrequency();
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alphaAccess->diskUnit = 1;
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alphaAccess->diskCount = 0;
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alphaAccess->diskPAddr = 0;
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alphaAccess->diskBlock = 0;
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alphaAccess->diskOperation = 0;
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alphaAccess->outputChar = 0;
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alphaAccess->inputChar = 0;
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alphaAccess->bootStrapImpure = 0;
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alphaAccess->bootStrapCPU = 0;
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alphaAccess->align2 = 0;
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}
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Fault
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@ -75,7 +75,8 @@ PciDev::ReadConfig(int offset, int size, uint8_t *data)
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{
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switch(size) {
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case sizeof(uint32_t):
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memcpy((uint32_t*)data, config.data + offset, sizeof(uint32_t));
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memcpy((uint8_t*)data, config.data + offset, sizeof(uint32_t));
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*(uint32_t*)data = htoa(*(uint32_t*)data);
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DPRINTF(PCIDEV,
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"read device: %#x function: %#x register: %#x %d bytes: data: %#x\n",
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deviceNum, functionNum, offset, size,
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@ -83,7 +84,8 @@ PciDev::ReadConfig(int offset, int size, uint8_t *data)
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break;
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case sizeof(uint16_t):
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memcpy((uint16_t*)data, config.data + offset, sizeof(uint16_t));
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memcpy((uint8_t*)data, config.data + offset, sizeof(uint16_t));
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*(uint16_t*)data = htoa(*(uint16_t*)data);
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DPRINTF(PCIDEV,
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"read device: %#x function: %#x register: %#x %d bytes: data: %#x\n",
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deviceNum, functionNum, offset, size,
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@ -282,18 +284,18 @@ PciDev::unserialize(Checkpoint *cp, const std::string §ion)
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BEGIN_DECLARE_SIM_OBJECT_PARAMS(PciConfigData)
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Param<int> VendorID;
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Param<int> DeviceID;
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Param<int> Command;
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Param<int> Status;
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Param<int> Revision;
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Param<int> ProgIF;
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Param<int> SubClassCode;
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Param<int> ClassCode;
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Param<int> CacheLineSize;
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Param<int> LatencyTimer;
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Param<int> HeaderType;
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Param<int> BIST;
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Param<uint16_t> VendorID;
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Param<uint16_t> DeviceID;
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Param<uint16_t> Command;
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Param<uint16_t> Status;
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Param<uint8_t> Revision;
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Param<uint8_t> ProgIF;
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Param<uint8_t> SubClassCode;
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Param<uint8_t> ClassCode;
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Param<uint8_t> CacheLineSize;
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Param<uint8_t> LatencyTimer;
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Param<uint8_t> HeaderType;
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Param<uint8_t> BIST;
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Param<uint32_t> BAR0;
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Param<uint32_t> BAR1;
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Param<uint32_t> BAR2;
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@ -301,13 +303,13 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(PciConfigData)
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Param<uint32_t> BAR4;
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Param<uint32_t> BAR5;
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Param<uint32_t> CardbusCIS;
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Param<int> SubsystemVendorID;
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Param<int> SubsystemID;
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Param<uint16_t> SubsystemVendorID;
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Param<uint16_t> SubsystemID;
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Param<uint32_t> ExpansionROM;
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Param<int> InterruptLine;
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Param<int> InterruptPin;
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Param<int> MinimumGrant;
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Param<int> MaximumLatency;
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Param<uint8_t> InterruptLine;
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Param<uint8_t> InterruptPin;
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Param<uint8_t> MinimumGrant;
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Param<uint8_t> MaximumLatency;
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Param<uint32_t> BAR0Size;
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Param<uint32_t> BAR1Size;
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Param<uint32_t> BAR2Size;
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@ -358,33 +360,33 @@ CREATE_SIM_OBJECT(PciConfigData)
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{
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PciConfigData *data = new PciConfigData(getInstanceName());
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data->config.hdr.vendor = VendorID;
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data->config.hdr.device = DeviceID;
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data->config.hdr.command = Command;
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data->config.hdr.status = Status;
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data->config.hdr.revision = Revision;
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data->config.hdr.progIF = ProgIF;
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data->config.hdr.subClassCode = SubClassCode;
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data->config.hdr.classCode = ClassCode;
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data->config.hdr.cacheLineSize = CacheLineSize;
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data->config.hdr.latencyTimer = LatencyTimer;
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data->config.hdr.headerType = HeaderType;
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data->config.hdr.bist = BIST;
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data->config.hdr.vendor = htoa(VendorID);
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data->config.hdr.device = htoa(DeviceID);
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data->config.hdr.command = htoa(Command);
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data->config.hdr.status = htoa(Status);
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data->config.hdr.revision = htoa(Revision);
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data->config.hdr.progIF = htoa(ProgIF);
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data->config.hdr.subClassCode = htoa(SubClassCode);
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data->config.hdr.classCode = htoa(ClassCode);
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data->config.hdr.cacheLineSize = htoa(CacheLineSize);
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data->config.hdr.latencyTimer = htoa(LatencyTimer);
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data->config.hdr.headerType = htoa(HeaderType);
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data->config.hdr.bist = htoa(BIST);
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data->config.hdr.pci0.baseAddr0 = BAR0;
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data->config.hdr.pci0.baseAddr1 = BAR1;
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data->config.hdr.pci0.baseAddr2 = BAR2;
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data->config.hdr.pci0.baseAddr3 = BAR3;
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data->config.hdr.pci0.baseAddr4 = BAR4;
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data->config.hdr.pci0.baseAddr5 = BAR5;
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data->config.hdr.pci0.cardbusCIS = CardbusCIS;
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data->config.hdr.pci0.subsystemVendorID = SubsystemVendorID;
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data->config.hdr.pci0.subsystemID = SubsystemVendorID;
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data->config.hdr.pci0.expansionROM = ExpansionROM;
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data->config.hdr.pci0.interruptLine = InterruptLine;
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data->config.hdr.pci0.interruptPin = InterruptPin;
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data->config.hdr.pci0.minimumGrant = MinimumGrant;
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data->config.hdr.pci0.maximumLatency = MaximumLatency;
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data->config.hdr.pci0.baseAddr0 = htoa(BAR0);
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data->config.hdr.pci0.baseAddr1 = htoa(BAR1);
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data->config.hdr.pci0.baseAddr2 = htoa(BAR2);
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data->config.hdr.pci0.baseAddr3 = htoa(BAR3);
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data->config.hdr.pci0.baseAddr4 = htoa(BAR4);
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data->config.hdr.pci0.baseAddr5 = htoa(BAR5);
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data->config.hdr.pci0.cardbusCIS = htoa(CardbusCIS);
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data->config.hdr.pci0.subsystemVendorID = htoa(SubsystemVendorID);
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data->config.hdr.pci0.subsystemID = htoa(SubsystemVendorID);
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data->config.hdr.pci0.expansionROM = htoa(ExpansionROM);
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data->config.hdr.pci0.interruptLine = htoa(InterruptLine);
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data->config.hdr.pci0.interruptPin = htoa(InterruptPin);
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data->config.hdr.pci0.minimumGrant = htoa(MinimumGrant);
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data->config.hdr.pci0.maximumLatency = htoa(MaximumLatency);
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data->BARSize[0] = BAR0Size;
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data->BARSize[1] = BAR1Size;
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@ -214,7 +214,7 @@ TsunamiUart::write(MemReqPtr &req, const uint8_t *data)
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case 0x0: // Data register (TX)
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char ourchar;
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ourchar = *(uint64_t *)data;
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ourchar = *(uint8_t *)data;
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if ((isprint(ourchar) || iscntrl(ourchar)) && (ourchar != 0x0C))
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cons->out(ourchar);
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cons->clearInt(CONS_INT_TX);
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@ -141,7 +141,7 @@ LinuxSystem::LinuxSystem(const string _name, const uint64_t _init_param,
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physmem->dma_addr(paddr, sizeof(uint64_t));
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if (est_cycle_frequency)
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*(uint64_t *)est_cycle_frequency = ticksPerSecond;
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*(uint64_t *)est_cycle_frequency = htoa(ticksPerSecond);
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}
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@ -179,8 +179,8 @@ LinuxSystem::LinuxSystem(const string _name, const uint64_t _init_param,
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char *hwprb = (char *)physmem->dma_addr(paddr, sizeof(uint64_t));
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if (hwprb) {
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*(uint64_t*)(hwprb+0x50) = 34; // Tsunami
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*(uint64_t*)(hwprb+0x58) = (1<<10); // Plain DP264
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*(uint64_t*)(hwprb+0x50) = htoa(ULL(34)); // Tsunami
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*(uint64_t*)(hwprb+0x58) = htoa(ULL(1)<<10); // Plain DP264
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}
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else
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panic("could not translate hwprb addr to set system type/variation\n");
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