diff --git a/dev/alpha_console.cc b/dev/alpha_console.cc
index f8870496f..5c4858ee5 100644
--- a/dev/alpha_console.cc
+++ b/dev/alpha_console.cc
@@ -80,6 +80,16 @@ AlphaConsole::AlphaConsole(const string &name, SimConsole *cons, SimpleDisk *d,
     alphaAccess->cpuClock = cpu->getFreq() / 1000000;
         alphaAccess->intrClockFrequency = platform->intrFrequency();
     alphaAccess->diskUnit = 1;
+
+    alphaAccess->diskCount = 0;
+    alphaAccess->diskPAddr = 0;
+    alphaAccess->diskBlock = 0;
+    alphaAccess->diskOperation = 0;
+    alphaAccess->outputChar = 0;
+    alphaAccess->inputChar = 0;
+    alphaAccess->bootStrapImpure = 0;
+    alphaAccess->bootStrapCPU = 0;
+    alphaAccess->align2 = 0;
 }
 
 Fault
diff --git a/dev/pcidev.cc b/dev/pcidev.cc
index 01f336ff8..7b13aac80 100644
--- a/dev/pcidev.cc
+++ b/dev/pcidev.cc
@@ -75,7 +75,8 @@ PciDev::ReadConfig(int offset, int size, uint8_t *data)
 {
     switch(size) {
       case sizeof(uint32_t):
-        memcpy((uint32_t*)data, config.data + offset, sizeof(uint32_t));
+        memcpy((uint8_t*)data, config.data + offset, sizeof(uint32_t));
+        *(uint32_t*)data = htoa(*(uint32_t*)data);
         DPRINTF(PCIDEV,
                 "read device: %#x function: %#x register: %#x %d bytes: data: %#x\n",
                 deviceNum, functionNum, offset, size,
@@ -83,7 +84,8 @@ PciDev::ReadConfig(int offset, int size, uint8_t *data)
         break;
 
       case sizeof(uint16_t):
-        memcpy((uint16_t*)data, config.data + offset, sizeof(uint16_t));
+        memcpy((uint8_t*)data, config.data + offset, sizeof(uint16_t));
+        *(uint16_t*)data = htoa(*(uint16_t*)data);
         DPRINTF(PCIDEV,
                 "read device: %#x function: %#x register: %#x %d bytes: data: %#x\n",
                 deviceNum, functionNum, offset, size,
@@ -282,18 +284,18 @@ PciDev::unserialize(Checkpoint *cp, const std::string &section)
 
 BEGIN_DECLARE_SIM_OBJECT_PARAMS(PciConfigData)
 
-    Param<int> VendorID;
-    Param<int> DeviceID;
-    Param<int> Command;
-    Param<int> Status;
-    Param<int> Revision;
-    Param<int> ProgIF;
-    Param<int> SubClassCode;
-    Param<int> ClassCode;
-    Param<int> CacheLineSize;
-    Param<int> LatencyTimer;
-    Param<int> HeaderType;
-    Param<int> BIST;
+    Param<uint16_t> VendorID;
+    Param<uint16_t> DeviceID;
+    Param<uint16_t> Command;
+    Param<uint16_t> Status;
+    Param<uint8_t> Revision;
+    Param<uint8_t> ProgIF;
+    Param<uint8_t> SubClassCode;
+    Param<uint8_t> ClassCode;
+    Param<uint8_t> CacheLineSize;
+    Param<uint8_t> LatencyTimer;
+    Param<uint8_t> HeaderType;
+    Param<uint8_t> BIST;
     Param<uint32_t> BAR0;
     Param<uint32_t> BAR1;
     Param<uint32_t> BAR2;
@@ -301,13 +303,13 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(PciConfigData)
     Param<uint32_t> BAR4;
     Param<uint32_t> BAR5;
     Param<uint32_t> CardbusCIS;
-    Param<int> SubsystemVendorID;
-    Param<int> SubsystemID;
+    Param<uint16_t> SubsystemVendorID;
+    Param<uint16_t> SubsystemID;
     Param<uint32_t> ExpansionROM;
-    Param<int> InterruptLine;
-    Param<int> InterruptPin;
-    Param<int> MinimumGrant;
-    Param<int> MaximumLatency;
+    Param<uint8_t> InterruptLine;
+    Param<uint8_t> InterruptPin;
+    Param<uint8_t> MinimumGrant;
+    Param<uint8_t> MaximumLatency;
     Param<uint32_t> BAR0Size;
     Param<uint32_t> BAR1Size;
     Param<uint32_t> BAR2Size;
@@ -358,33 +360,33 @@ CREATE_SIM_OBJECT(PciConfigData)
 {
     PciConfigData *data = new PciConfigData(getInstanceName());
 
-    data->config.hdr.vendor = VendorID;
-    data->config.hdr.device = DeviceID;
-    data->config.hdr.command = Command;
-    data->config.hdr.status = Status;
-    data->config.hdr.revision = Revision;
-    data->config.hdr.progIF = ProgIF;
-    data->config.hdr.subClassCode = SubClassCode;
-    data->config.hdr.classCode = ClassCode;
-    data->config.hdr.cacheLineSize = CacheLineSize;
-    data->config.hdr.latencyTimer = LatencyTimer;
-    data->config.hdr.headerType = HeaderType;
-    data->config.hdr.bist = BIST;
+    data->config.hdr.vendor = htoa(VendorID);
+    data->config.hdr.device = htoa(DeviceID);
+    data->config.hdr.command = htoa(Command);
+    data->config.hdr.status = htoa(Status);
+    data->config.hdr.revision = htoa(Revision);
+    data->config.hdr.progIF = htoa(ProgIF);
+    data->config.hdr.subClassCode = htoa(SubClassCode);
+    data->config.hdr.classCode = htoa(ClassCode);
+    data->config.hdr.cacheLineSize = htoa(CacheLineSize);
+    data->config.hdr.latencyTimer = htoa(LatencyTimer);
+    data->config.hdr.headerType = htoa(HeaderType);
+    data->config.hdr.bist = htoa(BIST);
 
-    data->config.hdr.pci0.baseAddr0 = BAR0;
-    data->config.hdr.pci0.baseAddr1 = BAR1;
-    data->config.hdr.pci0.baseAddr2 = BAR2;
-    data->config.hdr.pci0.baseAddr3 = BAR3;
-    data->config.hdr.pci0.baseAddr4 = BAR4;
-    data->config.hdr.pci0.baseAddr5 = BAR5;
-    data->config.hdr.pci0.cardbusCIS = CardbusCIS;
-    data->config.hdr.pci0.subsystemVendorID = SubsystemVendorID;
-    data->config.hdr.pci0.subsystemID = SubsystemVendorID;
-    data->config.hdr.pci0.expansionROM = ExpansionROM;
-    data->config.hdr.pci0.interruptLine = InterruptLine;
-    data->config.hdr.pci0.interruptPin = InterruptPin;
-    data->config.hdr.pci0.minimumGrant = MinimumGrant;
-    data->config.hdr.pci0.maximumLatency = MaximumLatency;
+    data->config.hdr.pci0.baseAddr0 = htoa(BAR0);
+    data->config.hdr.pci0.baseAddr1 = htoa(BAR1);
+    data->config.hdr.pci0.baseAddr2 = htoa(BAR2);
+    data->config.hdr.pci0.baseAddr3 = htoa(BAR3);
+    data->config.hdr.pci0.baseAddr4 = htoa(BAR4);
+    data->config.hdr.pci0.baseAddr5 = htoa(BAR5);
+    data->config.hdr.pci0.cardbusCIS = htoa(CardbusCIS);
+    data->config.hdr.pci0.subsystemVendorID = htoa(SubsystemVendorID);
+    data->config.hdr.pci0.subsystemID = htoa(SubsystemVendorID);
+    data->config.hdr.pci0.expansionROM = htoa(ExpansionROM);
+    data->config.hdr.pci0.interruptLine = htoa(InterruptLine);
+    data->config.hdr.pci0.interruptPin = htoa(InterruptPin);
+    data->config.hdr.pci0.minimumGrant = htoa(MinimumGrant);
+    data->config.hdr.pci0.maximumLatency = htoa(MaximumLatency);
 
     data->BARSize[0] = BAR0Size;
     data->BARSize[1] = BAR1Size;
diff --git a/dev/tsunami_uart.cc b/dev/tsunami_uart.cc
index 84eb80c8a..c6da02cf4 100644
--- a/dev/tsunami_uart.cc
+++ b/dev/tsunami_uart.cc
@@ -214,7 +214,7 @@ TsunamiUart::write(MemReqPtr &req, const uint8_t *data)
 
       case 0x0: // Data register (TX)
         char ourchar;
-        ourchar = *(uint64_t *)data;
+        ourchar = *(uint8_t *)data;
         if ((isprint(ourchar) || iscntrl(ourchar)) && (ourchar != 0x0C))
                 cons->out(ourchar);
         cons->clearInt(CONS_INT_TX);
diff --git a/kern/linux/linux_system.cc b/kern/linux/linux_system.cc
index 6287ce470..4b3f32f9c 100644
--- a/kern/linux/linux_system.cc
+++ b/kern/linux/linux_system.cc
@@ -141,7 +141,7 @@ LinuxSystem::LinuxSystem(const string _name, const uint64_t _init_param,
             physmem->dma_addr(paddr, sizeof(uint64_t));
 
         if (est_cycle_frequency)
-            *(uint64_t *)est_cycle_frequency = ticksPerSecond;
+            *(uint64_t *)est_cycle_frequency = htoa(ticksPerSecond);
     }
 
 
@@ -179,8 +179,8 @@ LinuxSystem::LinuxSystem(const string _name, const uint64_t _init_param,
         char *hwprb = (char *)physmem->dma_addr(paddr, sizeof(uint64_t));
 
         if (hwprb) {
-            *(uint64_t*)(hwprb+0x50) = 34;      // Tsunami
-            *(uint64_t*)(hwprb+0x58) = (1<<10); // Plain DP264
+            *(uint64_t*)(hwprb+0x50) = htoa(ULL(34));      // Tsunami
+            *(uint64_t*)(hwprb+0x58) = htoa(ULL(1)<<10); // Plain DP264
         }
         else
             panic("could not translate hwprb addr to set system type/variation\n");