Changes to support serialization with PCI devices
dev/ide_ctrl.cc:
Properly serialize/unserialize the PciDev base class to get it to remap
the MMU
dev/ns_gige.cc:
dev/ns_gige.hh:
Remove the "addr" paramter from the constructor and change the device
to use PCI based MMU mappings only
dev/pciconfigall.cc:
Change comments
dev/pcidev.cc:
Properly setup the MMU after a serialize
--HG--
extra : convert_revision : 4b2e7ba58e3c24fac1ff6f80635e704d6ecc0eff
This commit is contained in:
Andrew Schultz
parent
0408051f20
commit
d270ea851a
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@ -338,7 +338,10 @@ IdeController::WriteConfig(int offset, int size, uint32_t data)
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memcpy((void *)&pci_regs[offset], (void *)&data, size);
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}
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if (offset == PCI_COMMAND) {
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// Catch the writes to specific PCI registers that have side affects
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// (like updating the PIO ranges)
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switch (offset) {
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case PCI_COMMAND:
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if (config.data[offset] & IOSE)
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io_enabled = true;
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else
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@ -348,53 +351,61 @@ IdeController::WriteConfig(int offset, int size, uint32_t data)
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bm_enabled = true;
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else
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bm_enabled = false;
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break;
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} else if (data != 0xffffffff) {
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switch (offset) {
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case PCI0_BASE_ADDR0:
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case PCI0_BASE_ADDR0:
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if (BARAddrs[0] != 0) {
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pri_cmd_addr = BARAddrs[0];
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if (pioInterface)
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pioInterface->addAddrRange(pri_cmd_addr,
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pri_cmd_addr + pri_cmd_size - 1);
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pri_cmd_addr = pri_cmd_addr & PA_UNCACHED_MASK;
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break;
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pri_cmd_addr &= PA_UNCACHED_MASK;
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}
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break;
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case PCI0_BASE_ADDR1:
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case PCI0_BASE_ADDR1:
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if (BARAddrs[1] != 0) {
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pri_ctrl_addr = BARAddrs[1];
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if (pioInterface)
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pioInterface->addAddrRange(pri_ctrl_addr,
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pri_ctrl_addr + pri_ctrl_size - 1);
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pri_ctrl_addr = pri_ctrl_addr & PA_UNCACHED_MASK;
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break;
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pri_ctrl_addr &= PA_UNCACHED_MASK;
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}
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break;
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case PCI0_BASE_ADDR2:
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case PCI0_BASE_ADDR2:
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if (BARAddrs[2] != 0) {
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sec_cmd_addr = BARAddrs[2];
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if (pioInterface)
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pioInterface->addAddrRange(sec_cmd_addr,
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sec_cmd_addr + sec_cmd_size - 1);
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sec_cmd_addr = sec_cmd_addr & PA_UNCACHED_MASK;
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break;
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sec_cmd_addr &= PA_UNCACHED_MASK;
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}
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break;
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case PCI0_BASE_ADDR3:
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case PCI0_BASE_ADDR3:
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if (BARAddrs[3] != 0) {
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sec_ctrl_addr = BARAddrs[3];
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if (pioInterface)
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pioInterface->addAddrRange(sec_ctrl_addr,
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sec_ctrl_addr + sec_ctrl_size - 1);
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sec_ctrl_addr = sec_ctrl_addr & PA_UNCACHED_MASK;
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break;
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sec_ctrl_addr &= PA_UNCACHED_MASK;
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}
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break;
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case PCI0_BASE_ADDR4:
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case PCI0_BASE_ADDR4:
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if (BARAddrs[4] != 0) {
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bmi_addr = BARAddrs[4];
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if (pioInterface)
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pioInterface->addAddrRange(bmi_addr, bmi_addr + bmi_size - 1);
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bmi_addr = bmi_addr & PA_UNCACHED_MASK;
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break;
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bmi_addr &= PA_UNCACHED_MASK;
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}
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break;
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}
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}
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@ -589,6 +600,9 @@ IdeController::write(MemReqPtr &req, const uint8_t *data)
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void
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IdeController::serialize(std::ostream &os)
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{
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// Serialize the PciDev base class
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PciDev::serialize(os);
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// Serialize register addresses and sizes
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SERIALIZE_SCALAR(pri_cmd_addr);
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SERIALIZE_SCALAR(pri_cmd_size);
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@ -615,6 +629,9 @@ IdeController::serialize(std::ostream &os)
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void
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IdeController::unserialize(Checkpoint *cp, const std::string §ion)
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{
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// Unserialize the PciDev base class
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PciDev::unserialize(cp, section);
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// Unserialize register addresses and sizes
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UNSERIALIZE_SCALAR(pri_cmd_addr);
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UNSERIALIZE_SCALAR(pri_cmd_size);
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@ -97,9 +97,9 @@ NSGigE::NSGigE(const std::string &name, IntrControl *i, Tick intr_delay,
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bool dma_data_free, Tick dma_read_delay, Tick dma_write_delay,
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Tick dma_read_factor, Tick dma_write_factor, PciConfigAll *cf,
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PciConfigData *cd, Tsunami *t, uint32_t bus, uint32_t dev,
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uint32_t func, bool rx_filter, const int eaddr[6], Addr addr)
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uint32_t func, bool rx_filter, const int eaddr[6])
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: PciDev(name, mmu, cf, cd, bus, dev, func), tsunami(t),
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addr(addr), txPacketBufPtr(NULL), rxPacketBufPtr(NULL),
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txPacketBufPtr(NULL), rxPacketBufPtr(NULL),
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txXferLen(0), rxXferLen(0), txPktXmitted(0), txState(txIdle), CTDD(false),
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txFifoCnt(0), txFifoAvail(MAX_TX_FIFO_SIZE), txHalt(false),
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txFragPtr(0), txDescCnt(0), txDmaState(dmaIdle), rxState(rxIdle),
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@ -115,13 +115,12 @@ NSGigE::NSGigE(const std::string &name, IntrControl *i, Tick intr_delay,
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physmem(pmem), intctrl(i), intrTick(0),
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cpuPendingIntr(false), intrEvent(0), interface(0), pioLatency(pio_latency)
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{
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mmu->add_child(this, Range<Addr>(addr, addr + size));
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tsunami->ethernet = this;
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if (header_bus) {
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pioInterface = newPioInterface(name, hier, header_bus, this,
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&NSGigE::cacheAccess);
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pioInterface->addAddrRange(addr, addr + size - 1);
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if (payload_bus)
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dmaInterface = new DMAInterface<Bus>(name + ".dma",
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header_bus, payload_bus, 1);
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@ -131,7 +130,7 @@ NSGigE::NSGigE(const std::string &name, IntrControl *i, Tick intr_delay,
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} else if (payload_bus) {
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pioInterface = newPioInterface(name, hier, payload_bus, this,
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&NSGigE::cacheAccess);
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pioInterface->addAddrRange(addr, addr + size - 1);
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dmaInterface = new DMAInterface<Bus>(name + ".dma",
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payload_bus, payload_bus, 1);
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@ -226,9 +225,8 @@ NSGigE::ReadConfig(int offset, int size, uint8_t *data)
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{
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if (offset < PCI_DEVICE_SPECIFIC)
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PciDev::ReadConfig(offset, size, data);
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else {
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panic("need to do this\n");
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}
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else
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panic("Device specific PCI config space not implemented!\n");
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}
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/**
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@ -240,7 +238,21 @@ NSGigE::WriteConfig(int offset, int size, uint32_t data)
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if (offset < PCI_DEVICE_SPECIFIC)
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PciDev::WriteConfig(offset, size, data);
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else
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panic("Need to do that\n");
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panic("Device specific PCI config space not implemented!\n");
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// Need to catch writes to BARs to update the PIO interface
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switch (offset) {
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case PCI0_BASE_ADDR0:
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if (BARAddrs[0] != 0) {
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addr = BARAddrs[0];
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if (pioInterface)
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pioInterface->addAddrRange(addr, addr + size - 1);
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addr &= PA_UNCACHED_MASK;
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}
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break;
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}
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}
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/**
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@ -2002,6 +2014,9 @@ NSGigE::checksumCalc(uint16_t *pseudo, uint16_t *buf, uint32_t len)
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void
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NSGigE::serialize(ostream &os)
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{
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// Serialize the PciDev base class
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PciDev::serialize(os);
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/*
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* Finalize any DMA events now.
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*/
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@ -2153,6 +2168,9 @@ NSGigE::serialize(ostream &os)
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void
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NSGigE::unserialize(Checkpoint *cp, const std::string §ion)
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{
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// Unserialize the PciDev base class
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PciDev::unserialize(cp, section);
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UNSERIALIZE_SCALAR(regs.command);
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UNSERIALIZE_SCALAR(regs.config);
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UNSERIALIZE_SCALAR(regs.mear);
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@ -2346,7 +2364,6 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(NSGigE)
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Param<Tick> intr_delay;
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SimObjectParam<MemoryController *> mmu;
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SimObjectParam<PhysicalMemory *> physmem;
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Param<Addr> addr;
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Param<bool> rx_filter;
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Param<string> hardware_address;
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SimObjectParam<Bus*> header_bus;
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@ -2376,7 +2393,6 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(NSGigE)
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INIT_PARAM_DFLT(intr_delay, "Interrupt Delay in microseconds", 0),
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INIT_PARAM(mmu, "Memory Controller"),
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INIT_PARAM(physmem, "Physical Memory"),
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INIT_PARAM(addr, "Device Address"),
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INIT_PARAM_DFLT(rx_filter, "Enable Receive Filter", true),
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INIT_PARAM_DFLT(hardware_address, "Ethernet Hardware Address",
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"00:99:00:00:00:01"),
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@ -2407,12 +2423,11 @@ CREATE_SIM_OBJECT(NSGigE)
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&eaddr[0], &eaddr[1], &eaddr[2], &eaddr[3], &eaddr[4], &eaddr[5]);
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return new NSGigE(getInstanceName(), intr_ctrl, intr_delay,
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physmem, tx_delay, rx_delay, mmu, hier, header_bus,
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payload_bus, pio_latency, dma_desc_free, dma_data_free,
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dma_read_delay, dma_write_delay, dma_read_factor,
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dma_write_factor, configspace, configdata,
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tsunami, pci_bus, pci_dev, pci_func, rx_filter, eaddr,
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addr);
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physmem, tx_delay, rx_delay, mmu, hier, header_bus,
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payload_bus, pio_latency, dma_desc_free, dma_data_free,
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dma_read_delay, dma_write_delay, dma_read_factor,
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dma_write_factor, configspace, configdata,
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tsunami, pci_bus, pci_dev, pci_func, rx_filter, eaddr);
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}
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REGISTER_SIM_OBJECT("NSGigE", NSGigE)
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@ -345,7 +345,7 @@ class NSGigE : public PciDev
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bool dma_data_free, Tick dma_read_delay, Tick dma_write_delay,
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Tick dma_read_factor, Tick dma_write_factor, PciConfigAll *cf,
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PciConfigData *cd, Tsunami *t, uint32_t bus, uint32_t dev,
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uint32_t func, bool rx_filter, const int eaddr[6], Addr addr);
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uint32_t func, bool rx_filter, const int eaddr[6]);
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~NSGigE();
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virtual void WriteConfig(int offset, int size, uint32_t data);
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@ -148,13 +148,21 @@ PciConfigAll::write(MemReqPtr &req, const uint8_t *data)
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void
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PciConfigAll::serialize(std::ostream &os)
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{
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// code should be written
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/*
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* There is no state associated with this object that requires
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* serialization. The only real state are the device pointers
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* which are all setup by the constructor of the PciDev class
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*/
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}
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void
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PciConfigAll::unserialize(Checkpoint *cp, const std::string §ion)
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{
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//code should be written
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/*
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* There is no state associated with this object that requires
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* serialization. The only real state are the device pointers
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* which are all setup by the constructor of the PciDev class
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*/
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}
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#ifndef DOXYGEN_SHOULD_SKIP_THIS
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@ -256,13 +256,26 @@ PciDev::WriteConfig(int offset, int size, uint32_t data)
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void
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PciDev::serialize(ostream &os)
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{
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SERIALIZE_ARRAY(BARSize, 6);
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SERIALIZE_ARRAY(BARAddrs, 6);
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SERIALIZE_ARRAY(config.data, 64);
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}
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void
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PciDev::unserialize(Checkpoint *cp, const std::string §ion)
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{
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UNSERIALIZE_ARRAY(BARSize, 6);
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UNSERIALIZE_ARRAY(BARAddrs, 6);
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UNSERIALIZE_ARRAY(config.data, 64);
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// Add the MMU mappings for the BARs
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for (int i=0; i < 6; i++) {
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if (BARAddrs[i] != 0)
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mmu->add_child((FunctionalMemory *)this,
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Range<Addr>(BARAddrs[i],
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BARAddrs[i] +
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BARSize[i] - 1));
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}
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}
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#ifndef DOXYGEN_SHOULD_SKIP_THIS
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