make tx/rx fifo size a param, also fix the empty dma problem by adjusting the state machine.
dev/ns_gige.cc:
make tx/rx fifo sizes a param. the default is 128K for each. also, make the state machine not move onto txFragRead if there is no room in the txfifo for data.
dev/ns_gige.hh:
make tx/rx fifo size a param
--HG--
extra : convert_revision : ed91eb31c2b21d4cdc6de87d8641df6197be5209
This commit is contained in:
Lisa Hsu
parent
537e840cc3
commit
f857bd9dff
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@ -96,17 +96,19 @@ uint32_t reverseEnd32(uint32_t);
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// NSGigE PCI Device
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//
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NSGigE::NSGigE(const std::string &name, IntrControl *i, Tick intr_delay,
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PhysicalMemory *pmem, Tick tx_delay, Tick rx_delay,
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MemoryController *mmu, HierParams *hier, Bus *header_bus,
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Bus *payload_bus, Tick pio_latency, bool dma_desc_free,
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bool dma_data_free, Tick dma_read_delay, Tick dma_write_delay,
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Tick dma_read_factor, Tick dma_write_factor, PciConfigAll *cf,
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PciConfigData *cd, Tsunami *t, uint32_t bus, uint32_t dev,
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uint32_t func, bool rx_filter, const int eaddr[6])
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PhysicalMemory *pmem, Tick tx_delay, Tick rx_delay,
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MemoryController *mmu, HierParams *hier, Bus *header_bus,
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Bus *payload_bus, Tick pio_latency, bool dma_desc_free,
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bool dma_data_free, Tick dma_read_delay, Tick dma_write_delay,
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Tick dma_read_factor, Tick dma_write_factor, PciConfigAll *cf,
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PciConfigData *cd, Tsunami *t, uint32_t bus, uint32_t dev,
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uint32_t func, bool rx_filter, const int eaddr[6],
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uint32_t tx_fifo_size, uint32_t rx_fifo_size)
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: PciDev(name, mmu, cf, cd, bus, dev, func), tsunami(t), ioEnable(false),
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maxTxFifoSize(tx_fifo_size), maxRxFifoSize(rx_fifo_size),
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txPacket(0), rxPacket(0), txPacketBufPtr(NULL), rxPacketBufPtr(NULL),
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txXferLen(0), rxXferLen(0), txState(txIdle), CTDD(false),
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txFifoAvail(MAX_TX_FIFO_SIZE), txHalt(false),
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txFifoAvail(tx_fifo_size), txHalt(false),
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txFragPtr(0), txDescCnt(0), txDmaState(dmaIdle), rxState(rxIdle),
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CRDD(false), rxPktBytes(0), rxFifoCnt(0), rxHalt(false),
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rxFragPtr(0), rxDescCnt(0), rxDmaState(dmaIdle), extstsEnable(false),
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@ -1127,7 +1129,7 @@ NSGigE::txReset()
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DPRINTF(Ethernet, "transmit reset\n");
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CTDD = false;
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txFifoAvail = MAX_TX_FIFO_SIZE;
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txFifoAvail = maxTxFifoSize;
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txHalt = false;
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txFragPtr = 0;
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assert(txDescCnt == 0);
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@ -1587,7 +1589,7 @@ NSGigE::transmit()
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}
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DPRINTF(Ethernet, "\n\nAttempt Pkt Transmit: txFifo length = %d\n",
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MAX_TX_FIFO_SIZE - txFifoAvail);
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maxTxFifoSize - txFifoAvail);
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if (interface->sendPacket(txFifo.front())) {
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if (DTRACE(Ethernet)) {
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if (txFifo.front()->isIpPkt()) {
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@ -1904,21 +1906,29 @@ NSGigE::txKick()
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}
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} else {
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DPRINTF(EthernetSM, "this descriptor isn't done yet\n");
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txState = txFragRead;
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if (txFifoAvail) {
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txState = txFragRead;
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/* The number of bytes transferred is either whatever is left
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in the descriptor (txDescCnt), or if there is not enough
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room in the fifo, just whatever room is left in the fifo
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*/
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txXferLen = min<uint32_t>(txDescCnt, txFifoAvail);
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/* The number of bytes transferred is either whatever is left
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in the descriptor (txDescCnt), or if there is not enough
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room in the fifo, just whatever room is left in the fifo
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*/
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txXferLen = min<uint32_t>(txDescCnt, txFifoAvail);
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txDmaAddr = txFragPtr & 0x3fffffff;
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txDmaData = txPacketBufPtr;
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txDmaLen = txXferLen;
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txDmaFree = dmaDataFree;
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txDmaAddr = txFragPtr & 0x3fffffff;
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txDmaData = txPacketBufPtr;
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txDmaLen = txXferLen;
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txDmaFree = dmaDataFree;
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if (doTxDmaRead())
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goto exit;
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} else {
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txState = txFifoBlock;
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transmit();
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break;
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}
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if (doTxDmaRead())
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goto exit;
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}
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break;
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@ -2054,7 +2064,7 @@ NSGigE::recvPacket(PacketPtr packet)
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rxBytes += packet->length;
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rxPackets++;
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DPRINTF(Ethernet, "\n\nReceiving packet from wire, rxFifoAvail = %d\n", MAX_RX_FIFO_SIZE - rxFifoCnt);
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DPRINTF(Ethernet, "\n\nReceiving packet from wire, rxFifoAvail = %d\n", maxRxFifoSize - rxFifoCnt);
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if (rxState == rxIdle) {
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DPRINTF(Ethernet, "receive disabled...packet dropped\n");
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@ -2068,7 +2078,7 @@ NSGigE::recvPacket(PacketPtr packet)
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return true;
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}
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if ((rxFifoCnt + packet->length) >= MAX_RX_FIFO_SIZE) {
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if ((rxFifoCnt + packet->length) >= maxRxFifoSize) {
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DPRINTF(Ethernet,
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"packet will not fit in receive buffer...packet dropped\n");
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devIntrPost(ISR_RXORN);
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@ -2630,6 +2640,8 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(NSGigE)
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Param<uint32_t> pci_bus;
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Param<uint32_t> pci_dev;
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Param<uint32_t> pci_func;
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Param<uint32_t> tx_fifo_size;
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Param<uint32_t> rx_fifo_size;
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END_DECLARE_SIM_OBJECT_PARAMS(NSGigE)
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@ -2659,7 +2671,9 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(NSGigE)
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INIT_PARAM(tsunami, "Tsunami"),
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INIT_PARAM(pci_bus, "PCI bus"),
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INIT_PARAM(pci_dev, "PCI device number"),
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INIT_PARAM(pci_func, "PCI function code")
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INIT_PARAM(pci_func, "PCI function code"),
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INIT_PARAM_DFLT(tx_fifo_size, "max size in bytes of txFifo", 131072),
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INIT_PARAM_DFLT(rx_fifo_size, "max size in bytes of rxFifo", 131072)
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END_INIT_SIM_OBJECT_PARAMS(NSGigE)
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@ -2675,7 +2689,8 @@ CREATE_SIM_OBJECT(NSGigE)
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payload_bus, pio_latency, dma_desc_free, dma_data_free,
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dma_read_delay, dma_write_delay, dma_read_factor,
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dma_write_factor, configspace, configdata,
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tsunami, pci_bus, pci_dev, pci_func, rx_filter, eaddr);
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tsunami, pci_bus, pci_dev, pci_func, rx_filter, eaddr,
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tx_fifo_size, rx_fifo_size);
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}
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REGISTER_SIM_OBJECT("NSGigE", NSGigE)
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@ -46,8 +46,9 @@
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#include "mem/bus/bus.hh"
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/** defined by the NS83820 data sheet */
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#define MAX_TX_FIFO_SIZE 8192
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#define MAX_RX_FIFO_SIZE 32768
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//these are now params for the device
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//#define MAX_TX_FIFO_SIZE 8192
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//#define MAX_RX_FIFO_SIZE 32768
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/** length of ethernet address in bytes */
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#define EADDR_LEN 6
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@ -168,7 +169,9 @@ class NSGigE : public PciDev
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/*** BASIC STRUCTURES FOR TX/RX ***/
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/* Data FIFOs */
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pktbuf_t txFifo;
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uint32_t maxTxFifoSize;
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pktbuf_t rxFifo;
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uint32_t maxRxFifoSize;
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/** various helper vars */
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PacketPtr txPacket;
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@ -332,13 +335,14 @@ class NSGigE : public PciDev
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public:
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NSGigE(const std::string &name, IntrControl *i, Tick intr_delay,
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PhysicalMemory *pmem, Tick tx_delay, Tick rx_delay,
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MemoryController *mmu, HierParams *hier, Bus *header_bus,
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Bus *payload_bus, Tick pio_latency, bool dma_desc_free,
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bool dma_data_free, Tick dma_read_delay, Tick dma_write_delay,
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Tick dma_read_factor, Tick dma_write_factor, PciConfigAll *cf,
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PciConfigData *cd, Tsunami *t, uint32_t bus, uint32_t dev,
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uint32_t func, bool rx_filter, const int eaddr[6]);
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PhysicalMemory *pmem, Tick tx_delay, Tick rx_delay,
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MemoryController *mmu, HierParams *hier, Bus *header_bus,
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Bus *payload_bus, Tick pio_latency, bool dma_desc_free,
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bool dma_data_free, Tick dma_read_delay, Tick dma_write_delay,
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Tick dma_read_factor, Tick dma_write_factor, PciConfigAll *cf,
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PciConfigData *cd, Tsunami *t, uint32_t bus, uint32_t dev,
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uint32_t func, bool rx_filter, const int eaddr[6],
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uint32_t tx_fifo_size, uint32_t rx_fifo_size);
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~NSGigE();
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virtual void WriteConfig(int offset, int size, uint32_t data);
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