Fix a few bugs in the receive state machine. In doing back to tracking
whether or not the state machine is enabled rather than tracking the
specific instance of trying to halt the state machine.
dev/ns_gige.cc:
change back to tracking the state machine's enableness instead of
whether or not it is trying to halt. Also fix a major bug that
would cause the NIC to drop packets when the rx state machine was
idle, but enabled.
Fix a couple other bugs in the state machine where the idle interrupt
would happen at the wrong time.
Add a warning to deal with improper values of intrTick
dev/ns_gige.hh:
We need to keep track of whether the state machine is enabled
or not separately from the control register since the bits don't
always reflect the truth.
--HG--
extra : convert_revision : 20056b225fa62a0744473babfd693506aa5f29b2
This commit is contained in:
Nathan Binkert
parent
8f87a57e70
commit
e60a4c58ee
2 changed files with 50 additions and 44 deletions
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@ -108,10 +108,10 @@ NSGigE::NSGigE(const std::string &name, IntrControl *i, Tick intr_delay,
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: PciDev(name, mmu, cf, cd, bus, dev, func), tsunami(t), ioEnable(false),
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maxTxFifoSize(tx_fifo_size), maxRxFifoSize(rx_fifo_size),
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txPacket(0), rxPacket(0), txPacketBufPtr(NULL), rxPacketBufPtr(NULL),
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txXferLen(0), rxXferLen(0), txState(txIdle), CTDD(false),
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txFifoAvail(tx_fifo_size), txHalt(false),
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txXferLen(0), rxXferLen(0), txState(txIdle), txEnable(false),
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CTDD(false), txFifoAvail(tx_fifo_size),
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txFragPtr(0), txDescCnt(0), txDmaState(dmaIdle), rxState(rxIdle),
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CRDD(false), rxPktBytes(0), rxFifoCnt(0), rxHalt(false),
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rxEnable(false), CRDD(false), rxPktBytes(0), rxFifoCnt(0),
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rxFragPtr(0), rxDescCnt(0), rxDmaState(dmaIdle), extstsEnable(false),
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rxDmaReadEvent(this), rxDmaWriteEvent(this),
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txDmaReadEvent(this), txDmaWriteEvent(this),
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@ -586,24 +586,23 @@ NSGigE::write(MemReqPtr &req, const uint8_t *data)
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switch (daddr) {
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case CR:
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regs.command = reg;
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if ((reg & (CR_TXE | CR_TXD)) == (CR_TXE | CR_TXD)) {
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txHalt = true;
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if (reg & CR_TXD) {
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txEnable = false;
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} else if (reg & CR_TXE) {
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//the kernel is enabling the transmit machine
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txEnable = true;
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// the kernel is enabling the transmit machine
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if (txState == txIdle)
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txKick();
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} else if (reg & CR_TXD) {
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txHalt = true;
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}
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if ((reg & (CR_RXE | CR_RXD)) == (CR_RXE | CR_RXD)) {
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rxHalt = true;
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if (reg & CR_RXD) {
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rxEnable = false;
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} else if (reg & CR_RXE) {
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if (rxState == rxIdle) {
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rxEnable = true;
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if (rxState == rxIdle)
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rxKick();
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}
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} else if (reg & CR_RXD) {
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rxHalt = true;
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}
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if (reg & CR_TXR)
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@ -777,6 +776,7 @@ NSGigE::write(MemReqPtr &req, const uint8_t *data)
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case RXDP:
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regs.rxdp = reg;
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CRDD = false;
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break;
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case RXDP_HI:
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@ -1076,6 +1076,15 @@ NSGigE::cpuIntrPost(Tick when)
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// schedule another.
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// HOWEVER, must be sure that the scheduled intrTick is in the
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// future (this was formerly the source of a bug)
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/**
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* @todo this warning should be removed and the intrTick code should
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* be fixed.
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*/
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if (intrTick < curTick && intrTick != 0) {
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warn("intrTick < curTick !!! intrTick=%d curTick=%d\n",
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intrTick, curTick);
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intrTick = 0;
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}
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assert((intrTick >= curTick) || (intrTick == 0));
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if (when > intrTick && intrTick != 0)
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return;
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@ -1154,11 +1163,10 @@ NSGigE::txReset()
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CTDD = false;
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txFifoAvail = maxTxFifoSize;
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txHalt = false;
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txEnable = false;;
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txFragPtr = 0;
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assert(txDescCnt == 0);
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txFifo.clear();
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regs.command &= ~CR_TXE;
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txState = txIdle;
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assert(txDmaState == dmaIdle);
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}
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@ -1171,12 +1179,11 @@ NSGigE::rxReset()
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CRDD = false;
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assert(rxPktBytes == 0);
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rxFifoCnt = 0;
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rxHalt = false;
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rxEnable = false;
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rxFragPtr = 0;
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assert(rxDescCnt == 0);
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assert(rxDmaState == dmaIdle);
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rxFifo.clear();
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regs.command &= ~CR_RXE;
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rxState = rxIdle;
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}
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@ -1340,7 +1347,7 @@ NSGigE::rxKick()
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// an event and come back to this loop.
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switch (rxState) {
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case rxIdle:
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if (!regs.command & CR_RXE) {
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if (!rxEnable) {
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DPRINTF(EthernetSM, "Receive Disabled! Nothing to do.\n");
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goto exit;
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}
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@ -1395,7 +1402,9 @@ NSGigE::rxKick()
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rxDescCache.extsts);
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if (rxDescCache.cmdsts & CMDSTS_OWN) {
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devIntrPost(ISR_RXIDLE);
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rxState = rxIdle;
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goto exit;
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} else {
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rxState = rxFifoBlock;
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rxFragPtr = rxDescCache.bufptr;
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@ -1566,18 +1575,20 @@ NSGigE::rxKick()
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if (rxDescCache.cmdsts & CMDSTS_INTR)
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devIntrPost(ISR_RXDESC);
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if (rxHalt) {
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if (!rxEnable) {
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DPRINTF(EthernetSM, "Halting the RX state machine\n");
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rxState = rxIdle;
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rxHalt = false;
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goto exit;
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} else
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rxState = rxAdvance;
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break;
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case rxAdvance:
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if (rxDescCache.link == 0) {
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devIntrPost(ISR_RXIDLE);
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rxState = rxIdle;
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return;
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CRDD = true;
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goto exit;
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} else {
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rxState = rxDescRead;
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regs.rxdp = rxDescCache.link;
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@ -1601,12 +1612,6 @@ NSGigE::rxKick()
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DPRINTF(EthernetSM, "entering next rx state = %s\n",
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NsRxStateStrings[rxState]);
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if (rxState == rxIdle) {
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regs.command &= ~CR_RXE;
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devIntrPost(ISR_RXIDLE);
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return;
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}
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goto next;
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exit:
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@ -1805,7 +1810,7 @@ NSGigE::txKick()
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switch (txState) {
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case txIdle:
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if (!regs.command & CR_TXE) {
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if (!txEnable) {
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DPRINTF(EthernetSM, "Transmit disabled. Nothing to do.\n");
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goto exit;
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}
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@ -1865,7 +1870,9 @@ NSGigE::txKick()
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txFragPtr = txDescCache.bufptr;
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txDescCnt = txDescCache.cmdsts & CMDSTS_LEN_MASK;
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} else {
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devIntrPost(ISR_TXIDLE);
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txState = txIdle;
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goto exit;
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}
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break;
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@ -1948,10 +1955,10 @@ NSGigE::txKick()
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transmit();
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txPacket = 0;
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if (txHalt) {
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if (!txEnable) {
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DPRINTF(EthernetSM, "halting TX state machine\n");
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txState = txIdle;
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txHalt = false;
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goto exit;
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} else
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txState = txAdvance;
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@ -2004,16 +2011,17 @@ NSGigE::txKick()
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if (txDmaState != dmaIdle)
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goto exit;
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if (txDescCache.cmdsts & CMDSTS_INTR) {
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if (txDescCache.cmdsts & CMDSTS_INTR)
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devIntrPost(ISR_TXDESC);
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}
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txState = txAdvance;
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break;
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case txAdvance:
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if (txDescCache.link == 0) {
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devIntrPost(ISR_TXIDLE);
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txState = txIdle;
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goto exit;
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} else {
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txState = txDescRead;
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regs.txdp = txDescCache.link;
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@ -2036,12 +2044,6 @@ NSGigE::txKick()
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DPRINTF(EthernetSM, "entering next tx state=%s\n",
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NsTxStateStrings[txState]);
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if (txState == txIdle) {
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regs.command &= ~CR_TXE;
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devIntrPost(ISR_TXIDLE);
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return;
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}
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goto next;
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exit:
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@ -2123,7 +2125,7 @@ NSGigE::recvPacket(PacketPtr packet)
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DPRINTF(Ethernet, "\n\nReceiving packet from wire, rxFifoAvail=%d\n",
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maxRxFifoSize - rxFifoCnt);
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if (rxState == rxIdle) {
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if (!rxEnable) {
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DPRINTF(Ethernet, "receive disabled...packet dropped\n");
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interface->recvDone();
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return true;
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@ -2388,9 +2390,9 @@ NSGigE::serialize(ostream &os)
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*/
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int txState = this->txState;
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SERIALIZE_SCALAR(txState);
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SERIALIZE_SCALAR(txEnable);
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SERIALIZE_SCALAR(CTDD);
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SERIALIZE_SCALAR(txFifoAvail);
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SERIALIZE_SCALAR(txHalt);
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SERIALIZE_SCALAR(txFragPtr);
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SERIALIZE_SCALAR(txDescCnt);
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int txDmaState = this->txDmaState;
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@ -2401,10 +2403,10 @@ NSGigE::serialize(ostream &os)
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*/
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int rxState = this->rxState;
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SERIALIZE_SCALAR(rxState);
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SERIALIZE_SCALAR(rxEnable);
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SERIALIZE_SCALAR(CRDD);
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SERIALIZE_SCALAR(rxPktBytes);
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SERIALIZE_SCALAR(rxFifoCnt);
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SERIALIZE_SCALAR(rxHalt);
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SERIALIZE_SCALAR(rxDescCnt);
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int rxDmaState = this->rxDmaState;
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SERIALIZE_SCALAR(rxDmaState);
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@ -2550,9 +2552,9 @@ NSGigE::unserialize(Checkpoint *cp, const std::string §ion)
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int txState;
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UNSERIALIZE_SCALAR(txState);
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this->txState = (TxState) txState;
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UNSERIALIZE_SCALAR(txEnable);
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UNSERIALIZE_SCALAR(CTDD);
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UNSERIALIZE_SCALAR(txFifoAvail);
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UNSERIALIZE_SCALAR(txHalt);
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UNSERIALIZE_SCALAR(txFragPtr);
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UNSERIALIZE_SCALAR(txDescCnt);
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int txDmaState;
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@ -2565,10 +2567,10 @@ NSGigE::unserialize(Checkpoint *cp, const std::string §ion)
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int rxState;
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UNSERIALIZE_SCALAR(rxState);
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this->rxState = (RxState) rxState;
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UNSERIALIZE_SCALAR(rxEnable);
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UNSERIALIZE_SCALAR(CRDD);
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UNSERIALIZE_SCALAR(rxPktBytes);
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UNSERIALIZE_SCALAR(rxFifoCnt);
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UNSERIALIZE_SCALAR(rxHalt);
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UNSERIALIZE_SCALAR(rxDescCnt);
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int rxDmaState;
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UNSERIALIZE_SCALAR(rxDmaState);
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@ -186,6 +186,8 @@ class NSGigE : public PciDev
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/* tx State Machine */
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TxState txState;
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bool txEnable;
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/** Current Transmit Descriptor Done */
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bool CTDD;
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/** current amt of free space in txDataFifo in bytes */
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@ -200,6 +202,8 @@ class NSGigE : public PciDev
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/** rx State Machine */
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RxState rxState;
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bool rxEnable;
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/** Current Receive Descriptor Done */
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bool CRDD;
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/** num of bytes in the current packet being drained from rxDataFifo */
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