Commit graph

2300 commits

Author SHA1 Message Date
Kevin Lim
8a9416ef8d Small fixes to O3 model.
cpu/o3/alpha_dyn_inst.hh:
    Set the instResult using a function on the base dyn inst.
cpu/o3/bpred_unit_impl.hh:
    Don't need to reset the state.
cpu/o3/commit_impl.hh:
    Mark instructions as completed.

    Wait until all stores are written back to handle a fault.
cpu/o3/cpu.cc:
    Clear instruction lists when switching out.
cpu/o3/lsq_unit.hh:
    Allow wbEvent to be set externally.
cpu/o3/lsq_unit_impl.hh:
    Mark instructions as completed properly.  Also use events for writing back stores even if there is a hit in the dcache.

--HG--
extra : convert_revision : 172ad088b75ac31e848a5040633152b5c051444c
2006-05-11 15:39:02 -04:00
Kevin Lim
92838fd35e Set memory properly.
--HG--
extra : convert_revision : 4e6c61d31bf052bb4aabf4bb7a4f0e870b44b771
2006-05-11 15:19:48 -04:00
Kevin Lim
9a96ebf368 Separate out result being ready and the instruction being complete.
--HG--
extra : convert_revision : 9f17af114bf639f8fb61896e49fa714932c081d7
2006-05-11 14:12:34 -04:00
Kevin Lim
f3358e5f7b O3 CPU now handles being used with the sampler.
cpu/o3/2bit_local_pred.cc:
cpu/o3/2bit_local_pred.hh:
cpu/o3/bpred_unit.hh:
cpu/o3/bpred_unit_impl.hh:
cpu/o3/btb.cc:
cpu/o3/btb.hh:
cpu/o3/commit.hh:
cpu/o3/commit_impl.hh:
cpu/o3/cpu.cc:
cpu/o3/cpu.hh:
cpu/o3/decode.hh:
cpu/o3/decode_impl.hh:
cpu/o3/fetch.hh:
cpu/o3/fetch_impl.hh:
cpu/o3/fu_pool.cc:
cpu/o3/fu_pool.hh:
cpu/o3/iew.hh:
cpu/o3/iew_impl.hh:
cpu/o3/inst_queue.hh:
cpu/o3/inst_queue_impl.hh:
cpu/o3/lsq.hh:
cpu/o3/lsq_impl.hh:
cpu/o3/lsq_unit.hh:
cpu/o3/lsq_unit_impl.hh:
cpu/o3/mem_dep_unit.hh:
cpu/o3/mem_dep_unit_impl.hh:
cpu/o3/ras.cc:
cpu/o3/ras.hh:
cpu/o3/rename.hh:
cpu/o3/rename_impl.hh:
cpu/o3/rob.hh:
cpu/o3/rob_impl.hh:
cpu/o3/sat_counter.cc:
cpu/o3/sat_counter.hh:
cpu/o3/thread_state.hh:
    Handle switching out and taking over.  Needs to be able to reset all state.
cpu/o3/alpha_cpu_impl.hh:
    Handle taking over from another XC.

--HG--
extra : convert_revision : b936e826f0f8a18319bfa940ff35097b4192b449
2006-05-04 11:36:20 -04:00
Kevin Lim
4601230d35 Fixes for the sampler.
cpu/simple/cpu.cc:
    Sampler fixes.  The status may be switched out when calling activate or suspend if there is a switchover during a quiesce.

--HG--
extra : convert_revision : da026e75dfb86289484cf01c5b1ecd9b03a72bd3
2006-05-03 15:54:36 -04:00
Kevin Lim
32a5294983 XC needs to get memory from the process.
--HG--
extra : convert_revision : a2c014276824255a896a7e353f919fe81071091e
2006-05-03 15:51:53 -04:00
Kevin Lim
d363d5aad7 Quiesce stuff.
cpu/ozone/cpu.hh:
    Add quiesce stat (not clear how it should be used yet).
cpu/ozone/cpu_impl.hh:
    Fix for quiesce.

--HG--
extra : convert_revision : a1998818e241374ae3f4c3cabbef885dda55c884
2006-04-24 17:40:00 -04:00
Kevin Lim
31e09892d7 Include option for disabling PC symbols.
cpu/inst_seq.hh:
cpu/o3/cpu.cc:
cpu/ozone/cpu_builder.cc:
cpu/ozone/thread_state.hh:
    SE build fixes.

--HG--
extra : convert_revision : a4df6128533105f849b5469f62d83dffe299b7df
2006-04-24 17:11:31 -04:00
Kevin Lim
e704960c80 Updates to Ozone model for quiesce, store conditionals.
--HG--
extra : convert_revision : 72ddd75ad0b5783aca9484e7d178c2915ee8e355
2006-04-24 17:10:06 -04:00
Kevin Lim
676afbe2c7 New stats added to O3 model.
--HG--
extra : convert_revision : 7abb491e89e3e1a331cd19aa05ddce5184abf9e0
2006-04-24 17:06:00 -04:00
Kevin Lim
b14bf03219 Fixes for ll/sc for the O3 model.
cpu/o3/alpha_cpu.hh:
    Store conditionals should not write their data to memory if they failed.
cpu/o3/lsq_unit.hh:
    Setup request parameters when they're needed.

--HG--
extra : convert_revision : d75cd7deda03584b7e25cb567e4d79032cac7118
2006-04-24 16:59:50 -04:00
Kevin Lim
b363a3703d Allow the switching on and off of PC symbols for tracing.
--HG--
extra : convert_revision : a2422e30ace9874ba1be44cd0e1d3024cabbf1ed
2006-04-24 16:56:24 -04:00
Kevin Lim
55db48891c Use dwarf-2 debugging symbols (they work much better).
--HG--
extra : convert_revision : 669e4c32f2bc2c035a4199d6152a638b75a25148
2006-04-24 16:55:31 -04:00
Kevin Lim
7bab47ac3a Include new OzoneCPU files
--HG--
extra : convert_revision : f8c8751aab62df5d57c6491c5ce9b90b5a176e86
2006-04-22 19:17:05 -04:00
Kevin Lim
6b4396111b Updates for OzoneCPU.
cpu/static_inst.hh:
    Updates for new CPU, also include a classification of quiesce instructions.

--HG--
extra : convert_revision : a34cd56da88fe57d7de24674fbb375bbf13f887f
2006-04-22 19:10:39 -04:00
Kevin Lim
bfc507e44e Remove unnecessary functions.
cpu/exec_context.hh:
    Remove functions that shouldn't be accessible to anything outside of the CPU.

--HG--
extra : convert_revision : 9793c3ceb6d5404484bafc7a75d75ed71815d9eb
2006-04-22 18:49:52 -04:00
Kevin Lim
f0baf0ec99 Update the python file for the CPU.
--HG--
extra : convert_revision : be899403d893f5ab6c11ae5a4334c0e36bd6ff61
2006-04-22 18:47:07 -04:00
Kevin Lim
759ff4b910 Updates for OzoneCPU.
build/SConstruct:
    Include Ozone CPU models.
cpu/cpu_models.py:
    Include OzoneCPU models.

--HG--
extra : convert_revision : 51a016c216cacd2cc613eed79653026c2edda4b3
2006-04-22 18:45:01 -04:00
Kevin Lim
a8b03e4d01 Updates for O3 model.
arch/alpha/isa/decoder.isa:
    Make IPR accessing instructions serializing so they are not issued incorrectly in the O3 model.
arch/alpha/isa/pal.isa:
    Allow IPR instructions to have flags.
base/traceflags.py:
    Include new trace flags from the two new CPU models.
cpu/SConscript:
    Create the templates for the split mem accessor methods.  Also include the new files from the new models (the Ozone model will be checked in next).
cpu/base_dyn_inst.cc:
cpu/base_dyn_inst.hh:
    Update to the BaseDynInst for the new models.

--HG--
extra : convert_revision : cc82db9c72ec3e29cea4c3fdff74a3843e287a35
2006-04-22 18:26:48 -04:00
Kevin Lim
c30f91c2f6 Namespace fix.
base/timebuf.hh:
    namespace fix.

--HG--
extra : convert_revision : 38e880b9394cf2923e2fb9775368cd93d719f950
2006-04-22 18:16:18 -04:00
Kevin Lim
de8baeb58a Move quiesce event to its own class.
SConscript:
    Move quiesce event to its own file/class.

--HG--
extra : convert_revision : 6aa7863adb529fc03142666213c3ec348825bd3b
2006-04-22 18:11:54 -04:00
Kevin Lim
bd38b56774 Move TLB faults into the normal fault classes. Now they are executed when the fault is invoked.
--HG--
extra : convert_revision : b5f00fff277e863b3fe43422bc39d0487c482e60
2006-04-22 18:09:08 -04:00
Ron Dreslinski
6f590b4ddc Fix indentation
--HG--
extra : convert_revision : 321ff3c6e8dcc41f18e983fac83e14c037081dcb
2006-03-29 17:54:58 -05:00
Ron Dreslinski
9a434869a1 Fix for prefetching check with blocking buffers. Need to look into support for prefetching with blocking buffers.
--HG--
extra : convert_revision : 7b401cf76742ffda6c911faf710970c58a0c337b
2006-03-29 17:53:52 -05:00
Ron Dreslinski
e881f8ce2a Add some basic statistics to the disk model
--HG--
extra : convert_revision : 0f3a45745b0122de64a2f434604a474df04f2938
2006-03-29 14:27:10 -05:00
Ron Dreslinski
9e39454f58 Make the .mpy file a .py file and convert it to the form recognized now.
--HG--
extra : convert_revision : 1019fd1e2bb484e1ea8f15db8dbe8e7a0201bd58
2006-03-28 14:58:23 -05:00
Ron Dreslinski
cdd861084a Add the detailed DRAM model into M5. See the /mem/timing/DRAM_M5.txt for discussion on setting paramaters.
SConscript:
    Add support for detailed DRAM model

--HG--
extra : convert_revision : b65f9a810fa95957b585c85632ac20f9283337d1
2006-03-27 15:06:16 -05:00
Ron Dreslinski
b96405b7e4 Add support in the fullsys script to run the POVray benchmark.
To run it use
-ETEST=POVRAY_BENCH   to run the built in povray benchmark program (more CPU intensive, small fileset ~11MB)
-ETEST=POVRAY_AUTUMN  to run the first part of a rendering of a autumn leaves/tree scene, less cpu intensive ~500MB working set.

For now I have been running with -ESYSTEM=Simple in order to drop checkpoints (built into binary at the point the render begins) and create memory traces.
I will check in a SYSTEM=3D_DRAM and SYSTEM=3D_CACHE configuration as soon as those are ready.

--HG--
extra : convert_revision : fb55834a02317d5e9961a5145c932965c8bc6a0e
2006-03-23 18:05:39 -05:00
Ron Dreslinski
73b0fbc3e1 Don't forget to check in the needed header file for the conditional prefetch building.
--HG--
extra : convert_revision : 2c2562da323fa1249af72af3a89c7666c745ae2b
2006-03-16 11:34:19 -05:00
Ron Dreslinski
beff73f1fa Merge zizzer:/z/m5/Bitkeeper/m5
into  zazzer.eecs.umich.edu:/z/rdreslin/m5bk/m5

--HG--
extra : convert_revision : a4de274ec50821218121ba38f9215f2348262c27
2006-03-15 17:53:49 -05:00
Ron Dreslinski
52cc2d5bad Add support for conditional compiling in of prefetchers.
--HG--
extra : convert_revision : 357554632f102224357c8c3848bc4bc7cbb9dc54
2006-03-15 17:53:21 -05:00
Kevin Lim
dc75cf121c Don't access init_regs directly. This does not affect newmem; Steve already changed this in newmem.
--HG--
extra : convert_revision : 19b1ed0bb2c8bcde72843e62f73635e84adf95b5
2006-03-15 15:38:14 -05:00
Ron Dreslinski
7405a3530b Remove unneeded header files.
Add some forward declerations.
Fix ordering problem of variables in constructor (see sourceforge)
Factor out code from header into _impl file to speed building process (keep cache_builder smaller in size)

--HG--
extra : convert_revision : 20087f88f95628af716094e09c2287e09580149e
2006-03-14 18:03:34 -05:00
Steve Reinhardt
918b3f59c2 Get rid of obsolete header that had only one declaration of
an obsolete function that doesn't exist.

arch/alpha/tru64/process.cc:
sim/process.cc:
    Don't include useless header.

--HG--
extra : convert_revision : 1dd5edeb0703e2190b89ea5ff563df4c95b7cf59
2006-03-12 01:05:01 -05:00
Gabe Black
9ca03a2183 Wrapped setSysCallReturn in !FULL_SYSTEM.
--HG--
extra : convert_revision : c6d3a5af04731a92eaca2337424ba10926f0d879
2006-03-10 15:12:46 -05:00
Ali Saidi
7b283dbc09 fix merging issues
arch/alpha/isa_traits.hh:
arch/sparc/linux/process.cc:
    fix merging problem
sim/syscall_emul.cc:
    use setIntReg

--HG--
extra : convert_revision : e88d72e415493cd17d7b88c22c7e995f3199e396
2006-03-09 16:17:10 -05:00
Ali Saidi
56cc760f6f Merge zizzer:/bk/multiarch
into  zeep.eecs.umich.edu:/z/saidi/work/m5.ma2

arch/alpha/isa_traits.hh:
arch/alpha/linux/process.cc:
arch/sparc/isa_traits.hh:
arch/sparc/linux/process.cc:
sim/process.cc:
    merge

--HG--
rename : cpu/exec_context.hh => cpu/cpu_exec_context.hh
extra : convert_revision : fea0155c8e23abbd0d5d5251abbd0f4d223fe935
2006-03-09 15:56:42 -05:00
Ali Saidi
ce3a6343b6 no more common syscall emulation, now common for everyone
check abi-tag note section of elf binary for OS
add pseudo functions (moved from alpha and made to be generic)
move setsyscallreturn into isa traits

arch/alpha/SConscript:
    no more common syscall emulation, now common for everyone
arch/alpha/isa_traits.hh:
    move setsyscallreturn into isa description
arch/alpha/linux/process.cc:
arch/alpha/tru64/process.cc:
    use generic functions rather than alpha specific ones
arch/sparc/isa_traits.hh:
    have consts for generic pseudo syscalls
arch/sparc/linux/process.cc:
    use generic functions
base/loader/elf_object.cc:
    check abi-tag note section of elf binary for OS
cpu/exec_context.hh:
    move syssyscallreturn into isa traits
sim/process.cc:
    find call num with a more generic
sim/syscall_emul.cc:
sim/syscall_emul.hh:
    add pseudo functions (moved from alpha and made to be generic)

--HG--
extra : convert_revision : 5a31024ecde7e39b830365ddd84593ea501a34d2
2006-03-09 15:42:09 -05:00
Gabe Black
91545ac2bf Merge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/m5
into  zizzer.eecs.umich.edu:/z/m5/Bitkeeper/multiarch

cpu/simple/cpu.cc:
    Hand Merge

--HG--
rename : cpu/exec_context.hh => cpu/cpu_exec_context.hh
extra : convert_revision : bf664b092f993d0f4675ce8e7df13645a920c1f4
2006-03-09 15:15:55 -05:00
Kevin Lim
e30bce8f8e Use functions to access XC.
cpu/exec_context.hh:
    Include readNextNPC function.
cpu/simple/cpu.cc:
    Use functions to set and access nextPC, nextNPC.

--HG--
extra : convert_revision : 22622b9c110e1d99cc9106a2a27c479579d7e1ad
2006-03-09 15:10:55 -05:00
Korey Sewell
a3aae21d03 last changes before big merge
arch/alpha/isa_traits.hh:
arch/sparc/isa_traits.hh:
    add nnpc for compiling purposes in exec_context setNextNPC function
cpu/exec_context.hh:
    set NNPC function
cpu/simple/cpu.cc:
    use NNPC in determining what PC we are using

--HG--
extra : convert_revision : e810cfbc5dc31879b20d2cc40bf9871613203532
2006-03-09 03:27:51 -05:00
Korey Sewell
9e304ed3e6 minor comments to decoder.isa
arch/mips/isa/decoder.isa:
    comments

--HG--
extra : convert_revision : 8e4fdf36d7f7365cda062bc169a313bf860a4fe5
2006-03-09 02:34:12 -05:00
Korey Sewell
226d49ef69 Merge zizzer:/bk/multiarch
into  zazzer.eecs.umich.edu:/z/ksewell/research/m5-sim/multiarch-m5

--HG--
extra : convert_revision : f3502f293f6ea44b5cf209ce2a935a25bca6054f
2006-03-08 16:54:08 -05:00
Korey Sewell
5a0fd8d9da add explicit support for nop,ssnop, and ehb instructions
--HG--
extra : convert_revision : 41151d38cabb6ce0ea81e5d78e4474d8f2ffeb67
2006-03-08 16:53:44 -05:00
Kevin Lim
77e40756b7 Include ability to copy all misc regs.
arch/alpha/ev5.cc:
    Include function for the MiscRegFile to copy all of the Iprs from an ExecContext.
arch/alpha/isa_traits.hh:
    Include functions to copy MiscRegs from an ExecContext.
cpu/cpu_exec_context.cc:
    Be sure to copy all of the misc regs when copying all architectural state.

--HG--
extra : convert_revision : cb948b5ff141ea0f739a1016f98236bd2a512f76
2006-03-08 15:10:47 -05:00
Kevin Lim
67732a7b28 Merge ktlim@zizzer:/bk/m5
into  zamp.eecs.umich.edu:/z/ktlim2/m5-proxyxc

arch/alpha/ev5.cc:
cpu/o3/cpu.hh:
    SCCS merged

--HG--
extra : convert_revision : 38889011ea02005c8fd3a7f3b0be3395223f6166
2006-03-08 13:26:30 -05:00
Kevin Lim
4d44e53736 Forward declaration of MemoryController.
My change to exec_context.hh probably affected these files to no longer have MemoryController forward declared through a long chain of includes.  MemoryController should be forward declared where it is used anyways.

dev/alpha_console.hh:
dev/uart.hh:
dev/uart8250.hh:
    Forward declaration of MemoryController.

--HG--
extra : convert_revision : afaac4014e0eb3b6d5d385cd4444b77511e03b51
2006-03-08 11:34:41 -05:00
Gabe Black
0df85fd8d8 Merge gblack@m5.eecs.umich.edu:/bk/multiarch
into  ewok.(none):/home/gblack/m5/multiarch

--HG--
extra : convert_revision : 5fe5a3d70774d6420b890237d9be4a5d0f00d17e
2006-03-08 08:09:45 -05:00
Gabe Black
3b7d756907 Working towards compiling SPARC_SE
arch/alpha/isa_traits.hh:
    Changed the enums to const ints, and got rid of a few unnecessary constants.
arch/sparc/isa_traits.hh:
    Got rid of the enums, and added in some missing constants.

--HG--
extra : convert_revision : ee47890af9d8c67300b31d8e0dda1d580bd21479
2006-03-08 08:09:27 -05:00
Korey Sewell
bfd820f704 Update MiscReg enum and miscRegFile definition
update miscReg file access

arch/mips/isa/decoder.isa:
arch/mips/isa_traits.cc:
    update miscRegfile access
arch/mips/isa_traits.hh:
    Update MiscReg enum and miscRegFile definition

--HG--
extra : convert_revision : 9b6b9343d674e1e38e25bb9a4ffe4325142e7424
2006-03-08 04:36:55 -05:00