Commit graph

9183 commits

Author SHA1 Message Date
Dam Sunwoo
7cbe0cf564 Mem: fix master id assertion in cache_impl.hh
The assertion was applied to the wrong packet.
This patch fixes the issue rerported by Xiang Jiang on the gem5-dev mailing list.
2012-06-29 11:19:07 -04:00
Matt Evans
234fd1c4d8 Style: Make style.py's invalid warning print which file caused the infraction. 2012-06-29 11:19:06 -04:00
Matt Evans
579047c76d Mem: Fix a livelock resulting in LLSC/locked memory access implementation.
Currently when multiple CPUs perform a load-linked/store-conditional sequence,
the loads all create a list of reservations which is then scanned when the
stores occur.  A reservation matching the context and address of the store is
sought, BUT all reservations matching the address are also erased at this point.

The upshot is that a store-conditional will remove all reservations even if the
store itself does not succeed.  A livelock was observed using 7-8 CPUs where a
thread would erase the reservations of other threads, not succeed, loop and put
its own reservation in again only to have it blown by another thread that
unsuccessfully now tries to store-conditional -- no forward progress was made,
hanging the system.

The correct way to do this is to only blow a reservation when a store
(conditional or not) actually /occurs/ to its address.  One thread always wins
(the one that does the store-conditional first).
2012-06-29 11:19:05 -04:00
Ali Saidi
3965ecc36b Stats: Update stats for RAS and LRU fixes. 2012-06-29 11:19:03 -04:00
Nathanael Premillieu
af2b14a362 O3: Track if the RAS has been pushed or not to pop the RAS if neccessary.
Add new flag (named pushedRAS) in the PredictorHistory structure.
This flag tracks whether the RAS has been pushed or not during a prediction.
Then, in the squash function it is used to pop the RAS if necessary.
2012-06-29 11:18:29 -04:00
Ali Saidi
71daeb0b2b ARM: Fix identification of one RAS pop instruction.
The check should be with the op2 field, not with the op1 field.
2012-06-29 11:18:29 -04:00
Ali Saidi
8d1e56bdcd Cache: Only invalidate a line in the cache when an uncacheable write is seen. 2012-06-29 11:18:29 -04:00
Ali Saidi
7e3496c78c ARM: Update version of linux we claim to be to 3.0.0.
Static binaries generated with new versions of libc complain that the kernel
is too old otherwise.
2012-06-29 11:18:29 -04:00
Ali Saidi
aed8050824 ARM: Fix issue with predicted next pc being wrong because of advance() ordering.
npc in PCState for ARM was being calculated before the current flags were
updated with the next flags. This causes an issue as the npc is incremented by
two or four depending on the current flags (thumb or not) and was leading to
branches that were predicted correctly being identified as mispredicted.
2012-06-29 11:18:28 -04:00
Ali Saidi
c51fc5ceff ARM: Fix address range issue with VExpress EMM 2012-06-27 19:23:02 -04:00
Andreas Hansson
c64731af61 swig: Use SWIG from environment when determining version
This patch fixes a minor issue in the SConstruct where a hardcoded
swig is used instead of the environment SWIG when determining the
version.
2012-06-20 19:32:42 -04:00
Andreas Hansson
eaf19d2815 Build: Point to the appropriate tcmalloc package
This patch updates the message printed if the user does not have
tcmalloc available. It turns out that the correct package (which
creates all required symlinks etc) is libgoogle-perftools-dev. This
has been verified on Ubuntu 12.04.
2012-06-18 15:43:12 -04:00
Anthony Gutierrez
ce9ac38342 configs: add run scripts for ics/gb versions of android and bbench
1) Modifies Benchmarks.py to add support for Android ICS and BBench on Android ICS.

2) An rcS script is added for BBench on ICS.

3) Separates benchmark entries and rcS scripts for GB/ICS

4) Removes the debugging output from the existing BBench run script. These
   print statements were used for debugging and they seemed to confuse users
   into believing they should see some terminal output.
2012-06-11 11:07:42 -04:00
Anthony Gutierrez
9764cde7f2 ARM: implement the ProcessInfo methods 2012-06-11 11:07:41 -04:00
Ali Saidi
12ba92055d scons: Make compiler version error more verbose and easier to debug. 2012-06-11 10:54:37 -04:00
Marc Orr
02f8178b44 Regression: Fix some bugs in simple-timing-mp-ruby.py. 2012-06-11 03:16:43 -04:00
Andreas Hansson
754a9570f2 Timing CPU: Remove a redundant port pointer
This patch is trivial and merely prunes a pointer that was never set
or used.
2012-06-08 12:45:24 -04:00
Andreas Hansson
a118c01716 Power: Fix MaxMiscDestRegs which was set to zero
This patch fixes a failing compilation caused by MaxMiscDestRegs being
zero. According to gcc 4.6, the result is a comparison that is always
false due to limited range of data type.
2012-06-08 12:44:17 -04:00
Nilay Vaish
d6609793d4 X86 TLB: Add a missing = sign 2012-06-07 17:03:45 -05:00
Ali Saidi
c80cd4136e mem: Delay deleting of incoming packets by one call.
This patch is a temporary fix until Andreas' four-phase patches
get reviewed and committed. Removing FastAlloc seems to have exposed
an issue which previously was reasonable rare in which packets are freed
before the sending cache is done with them. This change puts incoming packets
no a pendingDelete queue which are deleted at the start of the next call and
thus breaks the dependency between when the caller returns true and when the
packet is actually used by the sending cache.

Running valgrind on a multi-core linux boot and the memtester results in no
valgrind warnings.
2012-06-07 10:59:03 -04:00
Jayneel Gandhi
7183c3fd56 X86 TLB: Fix for gcc 4.4.3
Due to recent changes to X86 TLB, gem5 stopped compiling on
gcc version 4.4.3. This patch provides the fix for that problem. The patch
is tested on gcc 4.4.3. The change is not required for more recent
versions of gcc (like on 4.6.3).
2012-06-07 08:11:00 -05:00
Nilay Vaish
abb85a68f4 Config: call to setWorkCountOptions() for all ISAs 2012-06-07 08:05:31 -05:00
Nilay Vaish
51c23e601e Config: Remove setMipsOptions
As status matrix, MIPS fs does not work. Hence, these options are not
required. Secondly, the function is setting param values for a CPU class.
This seems strange, should probably be done in a different way.
2012-06-07 08:05:30 -05:00
Nilay Vaish
78a72d6972 Config: changes to a couple of error msgs 2012-06-07 08:05:30 -05:00
Anthony Gutierrez
d6da3ff317 cpu: Don't init simple and inorder CPUs if they are defered.
initCPU() will be called to initialize switched out CPUs for the simple and
inorder CPU models. this patch prevents those CPUs from being initialized
because they should get their state from the active CPU when it is switched
out.
2012-06-05 14:20:13 -04:00
Ali Saidi
20d25b9da7 ISA: Back-out NoopMachInst as a StaticInstPtr change. 2012-06-05 13:52:30 -04:00
Ali Saidi
c06970b673 cpt: update some comments in the checkpoint migration script 2012-06-05 10:36:59 -04:00
Ali Saidi
c49e739352 all: Update stats for memory per master and total fix. 2012-06-05 01:23:16 -04:00
William Wang
e5f0d6016b stats: when applying an operation to two vectors sum the components first.
Previously writing X/Y in a formula would result in:
x[0]/y[0] + x[1]/y[1]
In reality you want:
(x[0] +x[1])/(y[0] + y[1])
2012-06-05 01:23:11 -04:00
Dam Sunwoo
14539ccae1 Mem: add per-master stats to physmem
Added per-master stats (similar to cache stats) to physmem.
2012-06-05 01:23:11 -04:00
Geoffrey Blake
eced845a5e ARM: Add PCIe support to VExpress_EMM model and remove deprecated ELT 2012-06-05 01:23:11 -04:00
Chander Sudanthi
15228694d0 ARM: removed extra white space
Extra white space fixes in miscregs.hh
2012-06-05 01:23:10 -04:00
Chander Sudanthi
8a2ca2fd24 ARM: Fix MPIDR and MIDR register implementation.
This change allows designating a system as MP capable or not as some
bootloaders/kernels care that it's set right. You can have a single
processor MP capable system, but you can't have a multi-processor
UP only system. This change also fixes the initialization of the MIDR
register.
2012-06-05 01:23:10 -04:00
Chander Sudanthi
e60b2ac706 ARM: PS2 encoding fix
Fixed Disable encoding and added SetDefaults.
See http://wiki.osdev.org/Mouse_Input for encodings.
2012-06-05 01:23:10 -04:00
Ali Saidi
70d7d6cc7f sim: Provide a framework for detecting out of data checkpoints and migrating them. 2012-06-05 01:23:10 -04:00
Ali Saidi
2e988bbab0 stats: Add stats unittest for total calculations. 2012-06-05 01:23:10 -04:00
Ali Saidi
6df196b71e O3: Clean up the O3 structures and try to pack them a bit better.
DynInst is extremely large the hope is that this re-organization will put the
most used members close to each other.
2012-06-05 01:23:09 -04:00
Ali Saidi
aec7a44116 sim: Add support for tcmalloc if it's installed and available.
This package is available in Ubuntu, Debian, and Redhat as google-perftools.
With multiple tests on a single machine I've seen a little over 10% performance
gain with tcmalloc.
2012-06-05 01:23:09 -04:00
Ali Saidi
1b370431d0 sim: Remove FastAlloc
While FastAlloc provides a small performance increase (~1.5%) over regular malloc it isn't thread safe.
After removing FastAlloc and using tcmalloc I've seen a performance increase of 12% over libc malloc
when running twolf for ARM.
2012-06-05 01:23:08 -04:00
Ali Saidi
d6997777be ARM: Fix over-eager assert in gic. 2012-06-05 01:23:08 -04:00
Mitchell Hayenga
8294d49bb6 stats: Provide a mechanism to get a callback when stats are dumped.
This mechanism is useful for dumping output that is correlated with stats
dumping, but isn't tracked by the gem5 statistics.
2012-06-05 01:23:08 -04:00
Ali Saidi
0b0c5621ee ARM: Fix compilation on ARM after Gabe's change. 2012-06-05 01:23:08 -04:00
Gabe Black
008b17d816 ISA: Turn the ExtMachInst NoopMachinst into the StaticInstPtr NoopStaticInst.
This eliminates a use of the ExtMachInst type outside of the ISAs.
2012-06-04 10:57:23 -07:00
Gabe Black
6437f3f4ee X86: Update stats for the CPUID change. 2012-06-04 10:43:11 -07:00
Gabe Black
35fa5074aa X86: Ensure that the CPUID instruction always writes its outputs.
The CPUID instruction was implemented so that it would only write its results
if the instruction was successful. This works fine on the simple CPU where
unwritten registers retain their old values, but on a CPU like O3 with
renaming this is broken. The instruction needs to write the old values back
into the registers explicitly if they aren't being changed.
2012-06-04 10:43:09 -07:00
Gabe Black
7b73c36f5d X86: Ensure that the decoder's internal ExtMachInst is completely initialized.
There are some bits of some fields of the ExtMachInst which are not actually
used for anything but are included in the hash of an ExtMachInst for
simplicity and efficiency. This change makes sure the decoder's internal
working ExtMachInst is completely initialized, even these unused bits, so that
there isn't any nondeterministic behavior, no valgrind messages about
uninitialized variables, and no potential false misses/redundant entries in
the decode cache.
2012-06-04 10:43:08 -07:00
Andreas Hansson
0d32940711 Bus: Split the bus into a non-coherent and coherent bus
This patch introduces a class hierarchy of buses, a non-coherent one,
and a coherent one, splitting the existing bus functionality. By doing
so it also enables further specialisation of the two types of buses.

A non-coherent bus connects a number of non-snooping masters and
slaves, and routes the request and response packets based on the
address. The request packets issued by the master connected to a
non-coherent bus could still snoop in caches attached to a coherent
bus, as is the case with the I/O bus and memory bus in most system
configurations. No snoops will, however, reach any master on the
non-coherent bus itself. The non-coherent bus can be used as a
template for modelling PCI, PCIe, and non-coherent AMBA and OCP buses,
and is typically used for the I/O buses.

A coherent bus connects a number of (potentially) snooping masters and
slaves, and routes the request and response packets based on the
address, and also forwards all requests to the snoopers and deals with
the snoop responses. The coherent bus can be used as a template for
modelling QPI, HyperTransport, ACE and coherent OCP buses, and is
typically used for the L1-to-L2 buses and as the main system
interconnect.

The configuration scripts are updated to use a NoncoherentBus for all
peripheral and I/O buses.

A bit of minor tidying up has also been done.

--HG--
rename : src/mem/bus.cc => src/mem/coherent_bus.cc
rename : src/mem/bus.hh => src/mem/coherent_bus.hh
rename : src/mem/bus.cc => src/mem/noncoherent_bus.cc
rename : src/mem/bus.hh => src/mem/noncoherent_bus.hh
2012-05-31 13:30:04 -04:00
Andreas Hansson
fb9bfb9cfc Stats: Fix stats to match output after changeset 8800b05e1cb3
This patch updates the stats for parser to be aligned with the most
up-to-date behaviour. Somehow the wrong results got committed as part
of 8800b05e1cb3 (see details below) when fixing the no_value -> nan
stats.

changeset:   8983:8800b05e1cb3
user:        Nathan Binkert <nate@binkert.org>
summary:     stats: update stats for no_value -> nan
2012-05-09 11:52:14 -07:00
Andreas Hansson
1d520cda80 gcc: Small fixes to compile with gcc 4.7
This patch makes two very minor changes to please gcc 4.7. The
CopyData function no longer exists and this has been replaced. For
some reason previous versions of gcc did not complain on the const
char casting not having an implementation, but this is now addressed.
2012-05-30 05:31:48 -04:00
Andreas Hansson
b8cf48accc Bus: Remove redundant packet parameter from isOccupied
This patch merely remove the Packet* from the isOccupied member
function. Historically this was used to check if the packet was an
express snoop, but this is now done outside this function (where
relevant).
2012-05-30 05:31:11 -04:00