Commit graph

161 commits

Author SHA1 Message Date
Lisa Hsu 74ff45d353 factor some more commone code and enable going from checkpoint into arbitrary CPU with or without caches.
configs/common/Simulation.py:
    enable going from checkpoint into arbitrary CPU with or without caches.

--HG--
extra : convert_revision : 02e7ff8982fdb3a08bc609f89bd58df5b3a581b2
2006-11-01 19:25:09 -05:00
Lisa Hsu 7665be4f70 make it so that you can do a standard switch without the caches option. this will have only the o3 cpu have a cache, rather than timing (warmup) + o3 have cache.
--HG--
extra : convert_revision : d733de7ebb362bbd7376a0235ee7f117df2d6d37
2006-11-01 11:49:39 -05:00
Lisa Hsu 9ef8bf74c7 change name of 2nd switch_cpu so that ckpt recovery with multiple cpus doens't get confused.
--HG--
extra : convert_revision : 16c710c4196c520d03c1993a26f38cf1f04ab637
2006-11-01 11:40:49 -05:00
Kevin Lim f763864786 Fix up configs.
configs/common/Simulation.py:
    Remove mem parameter.
configs/example/se.py:
    Remove debug output that got included in my other push.

--HG--
extra : convert_revision : 643c34147f6c6cbb98b8e6d6e8206b9859593ab0
2006-10-31 14:58:09 -05:00
Kevin Lim 5825a6c9d8 Merge ktlim@zizzer:/bk/newmem
into  zamp.eecs.umich.edu:/z/ktlim2/clean/newmem-busfix

configs/example/fs.py:
configs/example/se.py:
src/mem/tport.hh:
    Hand merge.

--HG--
extra : convert_revision : b9df95534d43b3b311f24ae24717371d03d615bf
2006-10-31 14:37:19 -05:00
Kevin Lim bfd5eb2b08 Remove mem parameter. Now the translating port asks the CPU's dcache's peer for its MemObject instead of having to have a paramter for the MemObject.
configs/example/fs.py:
configs/example/se.py:
src/cpu/simple/base.cc:
src/cpu/simple/base.hh:
src/cpu/simple/timing.cc:
src/cpu/simple_thread.cc:
src/cpu/simple_thread.hh:
src/cpu/thread_state.cc:
src/cpu/thread_state.hh:
tests/configs/o3-timing-mp.py:
tests/configs/o3-timing.py:
tests/configs/simple-atomic-mp.py:
tests/configs/simple-atomic.py:
tests/configs/simple-timing-mp.py:
tests/configs/simple-timing.py:
tests/configs/tsunami-simple-atomic-dual.py:
tests/configs/tsunami-simple-atomic.py:
tests/configs/tsunami-simple-timing-dual.py:
tests/configs/tsunami-simple-timing.py:
    No need for mem parameter any more.
src/cpu/checker/cpu.cc:
    Use new constructor for simple thread (no more MemObject parameter).
src/cpu/checker/cpu.hh:
    Remove MemObject parameter.
src/cpu/memtest/memtest.hh:
    Ports now take in their MemObject owner.
src/cpu/o3/alpha/cpu_builder.cc:
    Remove mem parameter.
src/cpu/o3/alpha/cpu_impl.hh:
    Remove memory parameter and clean up handling of TranslatingPort.
src/cpu/o3/cpu.cc:
src/cpu/o3/cpu.hh:
src/cpu/o3/fetch.hh:
src/cpu/o3/fetch_impl.hh:
src/cpu/o3/mips/cpu_builder.cc:
src/cpu/o3/mips/cpu_impl.hh:
src/cpu/o3/params.hh:
src/cpu/o3/thread_state.hh:
src/cpu/ozone/cpu.hh:
src/cpu/ozone/cpu_builder.cc:
src/cpu/ozone/cpu_impl.hh:
src/cpu/ozone/front_end.hh:
src/cpu/ozone/front_end_impl.hh:
src/cpu/ozone/lw_lsq.hh:
src/cpu/ozone/lw_lsq_impl.hh:
src/cpu/ozone/simple_params.hh:
src/cpu/ozone/thread_state.hh:
src/cpu/simple/atomic.cc:
    Remove memory parameter.

--HG--
extra : convert_revision : 43cb44a33b31320d44b69679dcf646c0380d07d3
2006-10-31 14:33:56 -05:00
Lisa Hsu 697b432ba8 FSConfig.py:
Accidentally committed this last time

configs/common/FSConfig.py:
    Accidentally committed this last time

--HG--
extra : convert_revision : 32d49c17c661b57a9aa9c3b057258f6e037ba745
2006-10-30 16:55:52 -05:00
Lisa Hsu 580c8421ab se.py, fs.py:
import Caches
Simulation.py:
Fix typo - L2Cache --> L1Cache

configs/common/Simulation.py:
    Fix typo - L2Cache --> L1Cache
configs/example/fs.py:
configs/example/se.py:
    import Caches

--HG--
extra : convert_revision : 4292225b322c069665262eab7c83b5341844fba0
2006-10-30 16:51:46 -05:00
Lisa Hsu fe2698c435 ensure that there is a "/" between the cptdir and the cpt.%d.
--HG--
extra : convert_revision : 9aed7c3aecad10b039f3cfb26e04a7950be6bed1
2006-10-30 14:19:16 -05:00
Lisa Hsu 13cbd4e94b Merge zizzer:/bk/newmem
into  zed.eecs.umich.edu:/z/hsul/work/m5/newmem

--HG--
extra : convert_revision : 836fcb45f399ed4f860be2d0bfe2ac4709bfe2ef
2006-10-30 14:15:50 -05:00
Lisa Hsu 883f0394f5 decouple the switch option from the warmup period option - parsing was confused otherwise, oops.
--HG--
extra : convert_revision : 951fc664c59363df5f5e026aa791d83c26f050ec
2006-10-30 14:12:15 -05:00
Kevin Lim bc93802fb8 Use some python os.path stuff to make it more flexible where we can execute this script from.
--HG--
extra : convert_revision : a76861a0f2669a7cd3bf3a34177739c69a913545
2006-10-30 14:01:34 -05:00
Lisa Hsu b40af2328a add some comments and make the warmup period in a switchover parameterizable.
configs/common/Options.py:
    make the warmup period in a standard switch part of the option.
configs/common/Simulation.py:
    add some comments and also make the warmup period an option.

--HG--
extra : convert_revision : 0fa587291b97ff87c3b3a617e7359ac6d9bed7a5
2006-10-30 13:33:27 -05:00
Lisa Hsu a6fd29ddf9 factor out common run code from se.py and fs.py.
configs/example/fs.py:
    factor out common code.
configs/example/se.py:
    factor out common code

--HG--
extra : convert_revision : 72a1f653c84eae1b7d281e0a5e60ee116ad6b27d
2006-10-27 16:32:26 -04:00
Ali Saidi 86bd01dfc9 Fix fs.py. Lisa did you test this? Is there some wierd python version thing?
--HG--
extra : convert_revision : 6df5f90d5b66e7af27d4f524744b9dc3c703a588
2006-10-24 13:10:31 -04:00
Lisa Hsu 3922b2e076 warmup of 1B cpu cycles.
configs/example/fs.py:
configs/example/se.py:
    warm up of 1B CPU cycles

--HG--
extra : convert_revision : 0f3263f466fde4cd86e0663930e83617a6b3faad
2006-10-23 19:32:57 -04:00
Lisa Hsu 764f27a0c9 Merge zizzer:/bk/newmem
into  zed.eecs.umich.edu:/z/hsul/work/m5/newmem

--HG--
extra : convert_revision : bb58679e101570d50c040519fb08ffbabfee7416
2006-10-23 18:46:05 -04:00
Lisa Hsu 049f8d53a9 make a lot of the same changes as to fs.py for checkpointing.
1) rearrange the options to be in a nice logical order
2) add an option for what i call "standard switch", which is from simple->timing->detailed
3) make checkpointing code such that checkpoints taken from the command line override checkpoint instructions compiled into binaries.
4) add an option for maximum number of checkpoints - simulation will stop at max or maxtick, whichever is first

--HG--
extra : convert_revision : 8d905e1b297ae664d60f8c8ba48b2aac25437fc6
2006-10-23 18:42:46 -04:00
Lisa Hsu 40a04f2f40 changes regarding fs.py
1) rearrange the options to be in a nice logical order
2) add an option for what i call "standard switch", which is from simple->timing->detailed
3) change the client/server naming system to testsys/drivesys
4) make checkpointing code such that checkpoints taken from the command line override checkpoint instructions compiled into binaries.
5) add an option for maximum number of checkpoints - simulation will stop at max or maxtick, whichever is first

doesn't fully work because of a caching issue, but the python side of things i think should work - the counterpart of se.py does work.
i think i should factor out a lot of the common code in both, but i'll do that after this checkin, just to get this in the tree.

configs/example/fs.py:
    1) rearrange the options to be in a nice logical order
    2) add an option for what i call "standard switch", which is from simple->timing->detailed
    3) change the client/server naming system to testsys/drivesys
    4) make checkpointing code such that checkpoints taken from the command line override checkpoint instructions compiled into binaries.
    5) add an option for maximum number of checkpoints - simulation will stop at max or maxtick, whichever is first

--HG--
extra : convert_revision : 078e22800ff83f6e950bf5cc6fb16a98320e7c51
2006-10-23 18:07:51 -04:00
Steve Reinhardt d2856c2fde Add mutex test to Benchmarks.py.
--HG--
extra : convert_revision : 9b4f1ce9a181ac5a01e5b6a68067079969dfe9ce
2006-10-22 12:52:58 -04:00
Ron Dreslinski 30cd2298df Add some default options, point it to the /dist version of the splash benchmarks
--HG--
extra : convert_revision : cd3b4f395b360d646b8b60464768eaad0fd110a4
2006-10-20 21:13:10 -04:00
Ron Dreslinski e198e58e1e Clean up splash2 so it works in v2.0
configs/splash2/run.py:
    Update the splash2 file

--HG--
extra : convert_revision : b57ef1ab4b8fd1eaf281358db623b7581b96546b
2006-10-20 19:53:52 -04:00
Ron Dreslinski ad783962c5 Give physical memory some latency to stress the system
--HG--
extra : convert_revision : 3ca32ff9140770d0774cac5e82807a0574db09dd
2006-10-20 13:36:26 -04:00
Ron Dreslinski 316e0fa879 Add a config file in the example with the memtester and some parser options.
--HG--
extra : convert_revision : e70ccc3de4f7a3ae20ff9ec672853ee1555ed41b
2006-10-20 13:32:24 -04:00
Steve Reinhardt bba3dfb0d3 First cut at LL/SC support in caches (atomic mode only).
configs/example/fs.py:
    Add MOESI protocol to caches (uni coherence not quite working w/FS yet).

--HG--
extra : convert_revision : 7bef7d9c5b24bf7241cc810df692408837b06b86
2006-10-19 00:33:33 -07:00
Steve Reinhardt 0128b73d05 Add --caches option to add caches to server CPUs.
--HG--
extra : convert_revision : 6aa97dcc807e175215e73c638faf73be926d4cd4
2006-10-17 23:30:11 -07:00
Steve Reinhardt 05c487ef3c Enable MP systems via cmd-line flag in fs.py.
configs/example/fs.py:
    Add flag for MP server systems.
src/python/m5/objects/AlphaConsole.py:
src/python/m5/objects/IntrControl.py:
    Change CPU from 'any' to 'cpu[0]' to work better with MP sytems.
tests/configs/tsunami-simple-atomic-dual.py:
tests/configs/tsunami-simple-timing-dual.py:
    Don't need to set console & intrcontrol cpu
    params anymore (default is fixed now).

--HG--
extra : convert_revision : 9417b12b1b395ff7d6a9f2894e4123923c754daf
2006-10-17 21:15:11 -07:00
Steve Reinhardt 96737c8a9b Rename 'Machine' to 'SysConfig'.
Clean up a little.

--HG--
extra : convert_revision : db5f36776209c76a593205c46b08aa147358f33a
2006-10-17 11:08:49 -07:00
Kevin Lim e5b13138b1 Two minor fixes.
configs/common/SysPaths.py:
    Undo accidental change.
src/SConscript:
    Fix.

--HG--
extra : convert_revision : 665b186cff7d8ae560601ced7ae407a41a16cfea
2006-10-10 01:49:46 -04:00
Kevin Lim bdde892d66 Merge ktlim@zizzer:/bk/newmem
into  zamp.eecs.umich.edu:/z/ktlim2/clean/o3-merge/newmem

src/cpu/memtest/memtest.cc:
src/cpu/memtest/memtest.hh:
src/cpu/simple/timing.hh:
tests/configs/o3-timing-mp.py:
    Hand merge.

--HG--
extra : convert_revision : a58cc439eb5e8f900d175ed8b5a85b6c8723e558
2006-10-09 22:59:56 -04:00
Lisa Hsu 67a114fc29 add in checkpoint restoration option, you can restore a checkpoint by giving a directory, and then giving a checkpoint number, the earliest checkpoint is 1, the latest is N. the default checkpoint directory is the cwd.
so you can restore by a command line like this:

m5.opt fs.py --checkpoint_dir="/my/ckpt/dir" -c 3

configs/example/fs.py:
    add in checkpoint restoration option, you can restore a checkpoint by giving a directory, and then giving a checkpoint number, the earliest checkpoint is 1, the latest is N.

--HG--
extra : convert_revision : bf9c8d3265a3875cdfb6a878005baa7ae29af90d
2006-10-09 00:12:16 -04:00
Steve Reinhardt 91c76278b9 Set cpu_id params (required by ll/sc code now).
--HG--
extra : convert_revision : e0f7ccbeccca191a8edb54494d2b4f9369e9914c
2006-10-08 19:11:06 -07:00
Kevin Lim 8949d813ff Clean up configs.
configs/common/FSConfig.py:
configs/common/SysPaths.py:
configs/example/fs.py:
configs/example/se.py:
tests/configs/o3-timing-mp.py:
tests/configs/o3-timing.py:
    Clean up configs by removing FullO3Config and instead using default values.
src/python/m5/objects/FUPool.py:
    Add in default FUPool.
src/python/m5/objects/O3CPU.py:
    Use defaults better.  Also set checker parameters, and fix up a config bug.

--HG--
extra : convert_revision : 5fd0c000143f4881f10a9a575c3810dc97cb290b
2006-10-08 01:12:42 -04:00
Lisa Hsu 54cf456fd1 add an option for defining a directory in which to place all your checkpoints. if none, default is cwd.
--HG--
extra : convert_revision : 23a602c2d800c922346c9743cc0c583d178a0ee7
2006-10-06 00:42:39 -04:00
Lisa Hsu 868d112578 fix the argument to m5.simulate() on a checkpoint.
src/sim/stat_control.cc:
    add curTick to reset stats printf.

--HG--
extra : convert_revision : da8cf5921e81b73f47d6831d539ca1fbdace3d1d
2006-10-05 13:18:32 -04:00
Kevin Lim 4ed184eade Merge ktlim@zamp:./local/clean/o3-merge/m5
into  zamp.eecs.umich.edu:/z/ktlim2/clean/o3-merge/newmem

configs/boot/micro_memlat.rcS:
configs/boot/micro_tlblat.rcS:
src/arch/alpha/ev5.cc:
src/arch/alpha/isa/decoder.isa:
src/arch/alpha/isa_traits.hh:
src/cpu/base.cc:
src/cpu/base.hh:
src/cpu/base_dyn_inst.hh:
src/cpu/checker/cpu.hh:
src/cpu/checker/cpu_impl.hh:
src/cpu/o3/alpha/cpu_impl.hh:
src/cpu/o3/alpha/params.hh:
src/cpu/o3/checker_builder.cc:
src/cpu/o3/commit_impl.hh:
src/cpu/o3/cpu.cc:
src/cpu/o3/decode_impl.hh:
src/cpu/o3/fetch_impl.hh:
src/cpu/o3/iew.hh:
src/cpu/o3/iew_impl.hh:
src/cpu/o3/inst_queue.hh:
src/cpu/o3/lsq.hh:
src/cpu/o3/lsq_impl.hh:
src/cpu/o3/lsq_unit.hh:
src/cpu/o3/lsq_unit_impl.hh:
src/cpu/o3/regfile.hh:
src/cpu/o3/rename_impl.hh:
src/cpu/o3/thread_state.hh:
src/cpu/ozone/checker_builder.cc:
src/cpu/ozone/cpu.hh:
src/cpu/ozone/cpu_impl.hh:
src/cpu/ozone/front_end.hh:
src/cpu/ozone/front_end_impl.hh:
src/cpu/ozone/lw_back_end.hh:
src/cpu/ozone/lw_back_end_impl.hh:
src/cpu/ozone/lw_lsq.hh:
src/cpu/ozone/lw_lsq_impl.hh:
src/cpu/ozone/thread_state.hh:
src/cpu/simple/base.cc:
src/cpu/simple_thread.cc:
src/cpu/simple_thread.hh:
src/cpu/thread_state.hh:
src/dev/ide_disk.cc:
src/python/m5/objects/O3CPU.py:
src/python/m5/objects/Root.py:
src/python/m5/objects/System.py:
src/sim/pseudo_inst.cc:
src/sim/pseudo_inst.hh:
src/sim/system.hh:
util/m5/m5.c:
    Hand merge.

--HG--
rename : arch/alpha/ev5.cc => src/arch/alpha/ev5.cc
rename : arch/alpha/freebsd/system.cc => src/arch/alpha/freebsd/system.cc
rename : arch/alpha/isa/decoder.isa => src/arch/alpha/isa/decoder.isa
rename : arch/alpha/isa/mem.isa => src/arch/alpha/isa/mem.isa
rename : arch/alpha/isa_traits.hh => src/arch/alpha/isa_traits.hh
rename : arch/alpha/linux/system.cc => src/arch/alpha/linux/system.cc
rename : arch/alpha/system.cc => src/arch/alpha/system.cc
rename : arch/alpha/tru64/system.cc => src/arch/alpha/tru64/system.cc
rename : cpu/base.cc => src/cpu/base.cc
rename : cpu/base.hh => src/cpu/base.hh
rename : cpu/base_dyn_inst.hh => src/cpu/base_dyn_inst.hh
rename : cpu/checker/cpu.hh => src/cpu/checker/cpu.hh
rename : cpu/checker/cpu.cc => src/cpu/checker/cpu_impl.hh
rename : cpu/o3/alpha_cpu_builder.cc => src/cpu/o3/alpha/cpu_builder.cc
rename : cpu/checker/o3_cpu_builder.cc => src/cpu/o3/checker_builder.cc
rename : cpu/o3/commit_impl.hh => src/cpu/o3/commit_impl.hh
rename : cpu/o3/cpu.cc => src/cpu/o3/cpu.cc
rename : cpu/o3/fetch_impl.hh => src/cpu/o3/fetch_impl.hh
rename : cpu/o3/iew.hh => src/cpu/o3/iew.hh
rename : cpu/o3/iew_impl.hh => src/cpu/o3/iew_impl.hh
rename : cpu/o3/inst_queue.hh => src/cpu/o3/inst_queue.hh
rename : cpu/o3/inst_queue_impl.hh => src/cpu/o3/inst_queue_impl.hh
rename : cpu/o3/lsq_impl.hh => src/cpu/o3/lsq_impl.hh
rename : cpu/o3/lsq_unit.hh => src/cpu/o3/lsq_unit.hh
rename : cpu/o3/lsq_unit_impl.hh => src/cpu/o3/lsq_unit_impl.hh
rename : cpu/o3/mem_dep_unit_impl.hh => src/cpu/o3/mem_dep_unit_impl.hh
rename : cpu/o3/rename.hh => src/cpu/o3/rename.hh
rename : cpu/o3/rename_impl.hh => src/cpu/o3/rename_impl.hh
rename : cpu/o3/thread_state.hh => src/cpu/o3/thread_state.hh
rename : cpu/o3/tournament_pred.cc => src/cpu/o3/tournament_pred.cc
rename : cpu/o3/tournament_pred.hh => src/cpu/o3/tournament_pred.hh
rename : cpu/checker/cpu_builder.cc => src/cpu/ozone/checker_builder.cc
rename : cpu/ozone/cpu.hh => src/cpu/ozone/cpu.hh
rename : cpu/ozone/cpu_builder.cc => src/cpu/ozone/cpu_builder.cc
rename : cpu/ozone/cpu_impl.hh => src/cpu/ozone/cpu_impl.hh
rename : cpu/ozone/front_end.hh => src/cpu/ozone/front_end.hh
rename : cpu/ozone/front_end_impl.hh => src/cpu/ozone/front_end_impl.hh
rename : cpu/ozone/inorder_back_end_impl.hh => src/cpu/ozone/inorder_back_end_impl.hh
rename : cpu/ozone/inst_queue_impl.hh => src/cpu/ozone/inst_queue_impl.hh
rename : cpu/ozone/lw_back_end.hh => src/cpu/ozone/lw_back_end.hh
rename : cpu/ozone/lw_back_end_impl.hh => src/cpu/ozone/lw_back_end_impl.hh
rename : cpu/ozone/lw_lsq.hh => src/cpu/ozone/lw_lsq.hh
rename : cpu/ozone/lw_lsq_impl.hh => src/cpu/ozone/lw_lsq_impl.hh
rename : cpu/ozone/simple_params.hh => src/cpu/ozone/simple_params.hh
rename : cpu/ozone/thread_state.hh => src/cpu/ozone/thread_state.hh
rename : cpu/simple/cpu.cc => src/cpu/simple/base.cc
rename : cpu/cpu_exec_context.cc => src/cpu/simple_thread.cc
rename : cpu/thread_state.hh => src/cpu/thread_state.hh
rename : dev/ide_disk.hh => src/dev/ide_disk.hh
rename : python/m5/objects/BaseCPU.py => src/python/m5/objects/BaseCPU.py
rename : python/m5/objects/AlphaFullCPU.py => src/python/m5/objects/O3CPU.py
rename : python/m5/objects/OzoneCPU.py => src/python/m5/objects/OzoneCPU.py
rename : python/m5/objects/Root.py => src/python/m5/objects/Root.py
rename : python/m5/objects/System.py => src/python/m5/objects/System.py
rename : sim/eventq.hh => src/sim/eventq.hh
rename : sim/pseudo_inst.cc => src/sim/pseudo_inst.cc
rename : sim/pseudo_inst.hh => src/sim/pseudo_inst.hh
rename : sim/serialize.cc => src/sim/serialize.cc
rename : sim/stat_control.cc => src/sim/stat_control.cc
rename : sim/stat_control.hh => src/sim/stat_control.hh
rename : sim/system.hh => src/sim/system.hh
extra : convert_revision : 135d90e43f6cea89f9460ba4e23f4b0b85886e7d
2006-09-30 23:43:23 -04:00
Ali Saidi 44c6f953b0 Merge zizzer:/bk/newmem
into  zeep.pool:/z/saidi/work/m5.newmem.head

--HG--
extra : convert_revision : 14ac24236ff65b7e489c1ce4b4e9a295966013b8
2006-09-11 17:57:30 -04:00
Ali Saidi 46502851ab add annotation code to m5
configs/common/Benchmarks.py:
    add annotate test app
src/SConscript:
    add annotate.cc to lis
src/arch/alpha/isa/decoder.isa:
    add annotate instructions
src/base/traceflags.py:
    Add annotate trace flag
src/sim/pseudo_inst.cc:
src/sim/pseudo_inst.hh:
    add annotate pseudo ops
util/m5/m5op.S:
util/m5/m5op.h:
    add anotate ops

--HG--
extra : convert_revision : 7f965c0d84e41ce34f2ec8ec27a009276d67d8d6
2006-09-11 17:57:20 -04:00
Steve Reinhardt 545cbec5f7 Enable proxies (Self/Parent) for specifying ports.
Significant revamp of Port code.
Some cleanup of SimObject code too, particularly to
make the SimObject and MetaSimObject implementations of
__setattr__ more consistent.
Unproxy code split out of print_ini().

src/python/m5/multidict.py:
    Make get() return None by default, to match semantics
    of built-in dictionary objects.

--HG--
extra : convert_revision : db73b6cdd004a82a08b2402afd1e16544cb902a4
2006-09-05 22:04:34 -07:00
Steve Reinhardt 8bc3c2b192 Add FULL_SYSTEM check to example/fs.py.
--HG--
extra : convert_revision : 4cab46e73f29d2c9d24d9c0c847d598bf6d5c389
2006-08-29 14:36:35 -07:00
Steve Reinhardt b0bf1e84e4 Add missing cpu mem param to example/se.py.
configs/example/se.py:
    Add missing cpu mem param.

--HG--
extra : convert_revision : 29a11b09524612f079b8998e99b8f5ee8c67c8a6
2006-08-29 14:14:29 -07:00
Kevin Lim 65741cd048 Updates to configs to support various sampling forms, truncated execution forms.
--HG--
extra : convert_revision : a6cf77f6c902e5f4f0a96206093d123eec2e0167
2006-08-24 18:01:07 -04:00
Steve Reinhardt 21b21c63b0 fs.py:
Add temporary cpu.mem parameter settings.

configs/example/fs.py:
    Add temporary cpu.mem parameter settings.

--HG--
extra : convert_revision : d7c2fcd8df8dc809b0511485877b2a85769aaf43
2006-08-21 12:31:59 -04:00
Steve Reinhardt b83d0e5544 configs/example/fs.py:
Arg to m5.simulate() is a delta, not an absolute curTick value.
I didn't test this change, but I'm not convinced the previous
example was tested either, so I don't feel too badly about it.

configs/example/fs.py:
    Arg to m5.simulate() is a delta, not an absolute curTick value.
    I didn't test this change, but I'm not convinced the previous
    example was tested either, so I don't feel too badly about it.

--HG--
extra : convert_revision : ef7df7b83b3e2b5da02408c674169ccbed75a441
2006-08-20 19:28:58 -07:00
Lisa Hsu a99534d429 Merge zizzer:/bk/newmem
into  zed.eecs.umich.edu:/z/hsul/work/m5/newmem

--HG--
extra : convert_revision : 382a9d4b420a9bdb35f93049306b7b7af0d33ad5
2006-08-17 00:02:38 -04:00
Lisa Hsu a88a6758ce make tree rcS files reflect what we've been actually using in /dist.
also, update all the rcS files so that they are in sync with the new linux-dist build system.

configs/boot/devtime.rcS:
configs/boot/iscsi-client.rcS:
configs/boot/iscsi-server.rcS:
configs/boot/micro_memlat.rcS:
configs/boot/micro_stream.rcS:
configs/boot/micro_tlblat.rcS:
configs/boot/nat-netperf-maerts-client.rcS:
configs/boot/nat-netperf-server.rcS:
configs/boot/nat-netperf-stream-client.rcS:
configs/boot/nat-spec-surge-client.rcS:
configs/boot/nat-spec-surge-server.rcS:
configs/boot/natbox-netperf.rcS:
configs/boot/natbox-spec-surge.rcS:
configs/boot/netperf-rr.rcS:
configs/boot/netperf-server.rcS:
configs/boot/netperf-stream-client.rcS:
configs/boot/netperf-stream-nt-client.rcS:
configs/boot/nfs-client-nhfsstone.rcS:
configs/boot/nfs-client-tcp-smallb.rcS:
configs/boot/nfs-client-tcp.rcS:
configs/boot/nfs-client.rcS:
configs/boot/nfs-server-nhfsstone.rcS:
configs/boot/nfs-server.rcS:
configs/boot/ping-client.rcS:
configs/boot/ping-server.rcS:
configs/boot/spec-surge-client.rcS:
configs/boot/spec-surge-server.rcS:
configs/boot/surge-client.rcS:
configs/boot/surge-server.rcS:
    make tree rcS files reflect what we've been actually using in /dist.

--HG--
extra : convert_revision : 48fe4fe71938ef9d029e428028a271242c8d2faa
2006-08-17 00:00:27 -04:00
Ali Saidi 76ab1c466c add etherdump file option
--HG--
extra : convert_revision : 6b62398778208bc4e64582e06fb73b71a94f3014
2006-08-16 22:17:23 -04:00
Lisa Hsu c475fd5211 Add in checkpointing in the frontend, so that when a checkpoint is called, the python handles it, and the simulation continues. Also, make it so that the cycle number is part of the cpt dir name, so that multiple checkpoints do not overwrite each other.
--HG--
extra : convert_revision : a55e4ac20da5a57ea8735951b9070960b9b8298f
2006-08-16 17:54:00 -04:00
Steve Reinhardt bd4ccd6e39 Finish test clean-up & reorg.
configs/common/FSConfig.py:
    Add default Machine() param
configs/example/fs.py:
configs/example/se.py:
    make it work again
src/python/m5/objects/BaseCPU.py:
    Make mem PhysicalMemory so that a Parent.any proxy works well
src/sim/process.cc:
    Increase default stack size so we don't get an
    'increasing stack' message on 'hello world'
tests/SConscript:
    Add full list of current configs.
tests/configs/simple-atomic.py:
tests/configs/simple-timing.py:
    don't need SEConfig anymore
tests/quick/00.hello/test.py:
tests/quick/20.eio-short/test.py:
    fix
tests/run.py:
    move configs to separate dir

--HG--
rename : configs/test/fs.py => configs/example/fs.py
rename : configs/test/test.py => configs/example/se.py
rename : tests/simple-atomic.py => tests/configs/simple-atomic.py
rename : tests/simple-timing.py => tests/configs/simple-timing.py
rename : tests/linux-mpboot/ref/alpha/atomic/config.ini => tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini
rename : tests/linux-mpboot/ref/alpha/atomic/config.out => tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.out
rename : tests/linux-mpboot/ref/alpha/atomic/console.system.sim_console => tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/console.system.sim_console
rename : tests/linux-mpboot/ref/alpha/atomic/m5stats.txt => tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/m5stats.txt
rename : tests/linux-mpboot/ref/alpha/atomic/stderr => tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stderr
rename : tests/linux-mpboot/ref/alpha/atomic/stdout => tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stdout
rename : tests/linux-boot/ref/alpha/atomic/config.ini => tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini
rename : tests/linux-boot/ref/alpha/atomic/config.out => tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.out
rename : tests/linux-boot/ref/alpha/atomic/console.system.sim_console => tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/console.system.sim_console
rename : tests/linux-boot/ref/alpha/atomic/m5stats.txt => tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/m5stats.txt
rename : tests/linux-boot/ref/alpha/atomic/stderr => tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stderr
rename : tests/linux-boot/ref/alpha/atomic/stdout => tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stdout
rename : tests/linux-mpboot/ref/alpha/timing/config.ini => tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini
rename : tests/linux-mpboot/ref/alpha/timing/config.out => tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.out
rename : tests/linux-mpboot/ref/alpha/timing/console.system.sim_console => tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/console.system.sim_console
rename : tests/linux-mpboot/ref/alpha/timing/m5stats.txt => tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/m5stats.txt
rename : tests/linux-mpboot/ref/alpha/timing/stderr => tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stderr
rename : tests/linux-mpboot/ref/alpha/timing/stdout => tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stdout
rename : tests/test-progs/hello/bin/mips/linux/hello_mips => tests/test-progs/hello/bin/mips/linux/hello
rename : tests/test-progs/hello/bin/sparc/bin => tests/test-progs/hello/bin/sparc/linux/hello
extra : convert_revision : d68ee6d7eefa7ba57370f3fb3c3589f86a6ea6b4
2006-08-16 14:42:44 -04:00
Steve Reinhardt 2552e68eb6 More restructuring of regression tests.
Moving work back to zizzer...

configs/common/FSConfig.py:
configs/test/fs.py:
    Move CPU connections out of makeLinuxAlphaSystem()
src/python/m5/objects/BaseCPU.py:
    Create default TLBs in full system.
    Move utility cache functions here.
src/python/m5/objects/O3CPU.py:
    Add _mem_ports
tests/run.py:
    Add binpath()
    Change maxtick default to 'forever'
tests/simple-atomic.py:
    Use connectmemPorts()
tests/simple-timing.py:
    Fix up.

--HG--
rename : tests/quick/eio1/ref/alpha/eio/detailed/config.ini => tests/quick/20.eio-short/ref/alpha/eio/detailed/config.ini
rename : tests/quick/eio1/ref/alpha/eio/detailed/config.out => tests/quick/20.eio-short/ref/alpha/eio/detailed/config.out
rename : tests/quick/eio1/ref/alpha/eio/detailed/m5stats.txt => tests/quick/20.eio-short/ref/alpha/eio/detailed/m5stats.txt
rename : tests/quick/eio1/ref/alpha/eio/detailed/stderr => tests/quick/20.eio-short/ref/alpha/eio/detailed/stderr
rename : tests/quick/eio1/ref/alpha/eio/detailed/stdout => tests/quick/20.eio-short/ref/alpha/eio/detailed/stdout
rename : tests/quick/eio1/ref/alpha/eio/simple-atomic/config.ini => tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/config.ini
rename : tests/quick/eio1/ref/alpha/eio/simple-atomic/config.out => tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/config.out
rename : tests/quick/eio1/ref/alpha/eio/simple-atomic/m5stats.txt => tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/m5stats.txt
rename : tests/quick/eio1/ref/alpha/eio/simple-atomic/stderr => tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/stderr
rename : tests/quick/eio1/ref/alpha/eio/simple-atomic/stdout => tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/stdout
rename : tests/quick/eio1/ref/alpha/eio/simple-timing/config.ini => tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.ini
rename : tests/quick/eio1/ref/alpha/eio/simple-timing/config.out => tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.out
rename : tests/quick/eio1/ref/alpha/eio/simple-timing/m5stats.txt => tests/quick/20.eio-short/ref/alpha/eio/simple-timing/m5stats.txt
rename : tests/quick/eio1/ref/alpha/eio/simple-timing/stderr => tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stderr
rename : tests/quick/eio1/ref/alpha/eio/simple-timing/stdout => tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stdout
rename : tests/quick/eio1/test.py => tests/quick/20.eio-short/test.py
rename : configs/test/hello => tests/test-progs/hello/bin/alpha/linux/hello
rename : configs/test/hello_mips => tests/test-progs/hello/bin/mips/linux/hello_mips
rename : configs/test/sparc_tests/hello_sparc => tests/test-progs/hello/bin/sparc/bin
extra : convert_revision : 1f891392ecc11ffcc3b3182fa673c401c0efc8a5
2006-08-16 09:52:05 -07:00