Commit graph

543 commits

Author SHA1 Message Date
Malek Musleh
3137557cad config: move ruby objects under ruby_system in obj hierarchy
This patch moves the contollers to be children of the ruby_system instead of
'system' under the python object hierarchy. This is so that these objects
can inherit some of the ruby_system's parameter values without resorting to
calling a global system pointer during run-time.

Committed by: Nilay Vaish <nilay@cs.wisc.edu>
2013-01-14 10:05:14 -06:00
Ali Saidi
fe3fbe624e config: Fix issue with changeset: a4739b6f799d. 2013-01-08 17:12:22 -05:00
Lluís Vilanova
807168a1de util: add m5_fail op.
Used as a command in full-system scripts helps the user ensure the benchmarks have finished successfully.

For example, one can use:

    /path/to/benchmark args || /sbin/m5 fail 1

and thus ensure gem5 will exit with an error if the benchmark fails.
2013-01-08 08:54:12 -05:00
Andreas Sandberg
2cfe62adc4 cpu: Rename defer_registration->switched_out
The defer_registration parameter is used to prevent a CPU from
initializing at startup, leaving it in the "switched out" mode. The
name of this parameter (and the help string) is confusing. This patch
renames it to switched_out, which should be more descriptive.
2013-01-07 13:05:45 -05:00
Andreas Hansson
e65de3f5ca config: Do not use hardcoded physmem in fs script
This patch generalises the address range resolution for the I/O cache
and I/O bridge such that they do not assume a single memory. The patch
involves adding a parameter to the system which is then defined based
on the memories that are to be visible from the I/O subsystem, whether
behind a cache or a bridge.

The change is needed to allow interleaved memory controllers in the
system.
2013-01-07 13:05:38 -05:00
Andreas Sandberg
3db3f83a5e arch: Make the ISA class inherit from SimObject
The ISA class on stores the contents of ID registers on many
architectures. In order to make reset values of such registers
configurable, we make the class inherit from SimObject, which allows
us to use the normal generated parameter headers.

This patch introduces a Python helper method, BaseCPU.createThreads(),
which creates a set of ISAs for each of the threads in an SMT
system. Although it is currently only needed when creating
multi-threaded CPUs, it should always be called before instantiating
the system as this is an obvious place to configure ID registers
identifying a thread/CPU.
2013-01-07 13:05:35 -05:00
Nilay Vaish
f3d0be210f ruby: add support for prefetching to MESI protocol 2012-12-11 10:05:56 -06:00
Nilay Vaish
c120273708 ruby: modify the directed tester to read/write streams
The directed tester supports only generating only read or only write accesses. The
patch modifies the tester to support streams that have both read and write accesses.
2012-12-11 10:05:55 -06:00
Erik Tomusk
3dc7e4f496 TournamentBP: Fix some bugs with table sizes and counters
globalHistoryBits, globalPredictorSize, and choicePredictorSize are decoupled.
globalHistoryBits controls how much history is kept, global and choice
predictor sizes control how much of that history is used when accessing
predictor tables. This way, global and choice predictors can actually be
different sizes, and it is no longer possible to walk off the predictor arrays
and cause a seg fault.

There are now individual thresholds for choice, global, and local saturating
counters, so that taken/not taken decisions are correct even when the
predictors' counters' sizes are different.

The interface for localPredictorSize has been removed from TournamentBP because
the value can be calculated from localHistoryBits.

Committed by: Nilay Vaish <nilay@cs.wisc.edu>
2012-12-06 09:31:06 -06:00
Andreas Hansson
13f6d29a76 config: Fix description of checkpoint option from cycle to tick
This patch merely updates the description of the "take-checkpoints"
option to reflect that it is specified in ticks and not in cycles.
2012-11-19 11:21:09 -05:00
Andreas Sandberg
dc01535c7e python: Rename doDrain()->drain() and make it do the right thing
There is no point in exporting the old drain() method in
Simulate.py. It should only be used internally by doDrain(). This
patch moves the old drain() method into doDrain() and renames
doDrain() to drain().
2012-11-02 11:32:02 -05:00
Andreas Sandberg
7e25052fee Partly revert [4f54b0f229b5] and move draining to m5.changeToTiming
Changeset 4f54b0f229b5 removed the call to doDrain in changeToTiming
based on the assumption that the system does not need draining when
running in atomic mode. This is a false assumption since at least the
System class requires the system to be drained before it allows
switching of memory modes. This patch reverts that part of the
changeset.
2012-11-02 11:32:00 -05:00
Andreas Hansson
9cbe1cb653 config: Unify caches used in regressions and adjust L2 MSHRs
This patch unified the L1 and L2 caches used throughout the
regressions instead of declaring different, but very similar,
configurations in the different scripts.

The patch also changes the default L2 configuration to match what it
used to be for the fs and se scripts (until the last patch that
updated the regressions to also make use of the cache config). The
MSHRs and targets per MSHR are now set to a more realistic default of
20 and 12, respectively.

As a result of both the aforementioned changes, many of the regression
stats are changed. A follow-on patch will bump the stats.
2012-10-30 07:44:08 -04:00
Malek Musleh
d2d431f439 ruby: set the is_icache param for caches
This patch sets the is_icache param for the L1 caches used in
the MESI and the MOESI CMP directory protocols.
2012-10-27 16:04:30 -05:00
Jason Power ext:(%2C%20Joel%20Hestness%20%3Chestness%40cs.wisc.edu%3E)
931ec6b7cc Ruby: Use block size in configuring directory bits in address
This patch replaces hard coded values used in Ruby's configuration files
for setting directory bits with values based on the block size in use.
2012-10-27 16:01:09 -05:00
Andreas Hansson
a4d8996fd9 config: Add a check for fastmem only used with Atomic CPU
This patch adds an additional check to ensure that the fastmem option
is only used if the system is using the Atomic CPU.
2012-10-26 06:42:45 -04:00
Andreas Hansson
7cd01cf769 config: Remove unused mem_size in fs.py
This patch removes a segment of dead code that is never used.
2012-10-26 06:42:43 -04:00
Andreas Hansson
651de2d9af config: Fix the cache class naming in regression scripts
This patch unifies the naming of the default L1 and L2 caches in the
regression configs to be in line with what is used in the se and fs
scripts.
2012-10-26 06:42:42 -04:00
Andreas Hansson
66e331c7bb config: Use SimpleDRAM in full-system, and with o3 and inorder
This patch favours using SimpleDRAM with the default timing instead of
SimpleMemory for all regressions that involve the o3 or inorder CPU,
or are full system (in other words, where the actual performance of
the memory is important for the overall performance).

Moving forward, the solution for FSConfig and the users of fs.py and
se.py is probably something similar to what we use to choose the CPU
type. I envision a few pre-set configurations SimpleLPDDR2,
SimpleDDR3, etc that can be choosen by a dram_type option. Feedback on
this part is welcome.

This patch changes plenty stats and adds all the DRAM controller
related stats. A follow-on patch updates the relevant statistics. The
total run-time for the entire regression goes up with ~5% with this
patch due to the added complexity of the SimpleDRAM model. This is a
concious trade-off to ensure that the model is properly tested.
2012-10-25 13:14:38 -04:00
Andreas Hansson
d22796c03c config: Use shared cache config for regressions
This patch uses the common L1, L2 and IOCache configuration for the
regressions that all share the same cache parameters. There are a few
regressions that use a slightly different configuration (memtest,
o3-timing=mp, simple-atomic-mp and simple-timing-mp), and the latter
are not changed in this patch. They will be updated in a future patch.

The common cache configurations are changed to match the ones used in
the regressions, and are slightly changed with respect to what they
were. Hopefully this means we can converge on a common base
configuration, used both in the normal user configurations and
regressions.

As only regressions that shared the same cache configuration are
updated, no regressions are affected.
2012-10-25 04:32:44 -04:00
Nilay Vaish
5ffc165939 ruby: improved support for functional accesses
This patch adds support to different entities in the ruby memory system
for more reliable functional read/write accesses. Only the simple network
has been augmented as of now. Later on Garnet will also support functional
accesses.
The patch adds functional access code to all the different types of messages
that protocols can send around. These messages are functionally accessed
by going through the buffers maintained by the network entities.
The patch also rectifies some of the bugs found in coherence protocols while
testing the patch.

With this patch applied, functional writes always succeed. But functional
reads can still fail.
2012-10-15 17:51:57 -05:00
Andreas Hansson
88554790c3 Mem: Use cycles to express cache-related latencies
This patch changes the cache-related latencies from an absolute time
expressed in Ticks, to a number of cycles that can be scaled with the
clock period of the caches. Ultimately this patch serves to enable
future work that involves dynamic frequency scaling. As an immediate
benefit it also makes it more convenient to specify cache performance
without implicitly assuming a specific CPU core operating frequency.

The stat blocked_cycles that actually counter in ticks is now updated
to count in cycles.

As the timing is now rounded to the clock edges of the cache, there
are some regressions that change. Plenty of them have very minor
changes, whereas some regressions with a short run-time are perturbed
quite significantly. A follow-on patch updates all the statistics for
the regressions.
2012-10-15 08:10:54 -04:00
Andreas Hansson
1c321b8847 Regression: Use CPU clock and 32-byte width for L1-L2 bus
This patch changes the CoherentBus between the L1s and L2 to use the
CPU clock and also four times the width compared to the default
bus. The parameters are not intending to fit every single scenario,
but rather serve as a better startingpoint than what we previously
had.

Note that the scripts that do not use the addTwoLevelCacheHiearchy are
not affected by this change.

A separate patch will update the stats.
2012-10-15 08:08:08 -04:00
Nilay Vaish
4488379244 ruby: changes to simple network
This patch makes the Switch structure inherit from BasicRouter, as is
done in two other networks.
2012-10-02 14:35:45 -05:00
Malek Musleh
3fc23b9b96 Configs: SE script fix for Alpha and Ruby simulations
PIO interrupt port is only present for x86. Do not attempt to connect
for other ISAs.
2012-09-28 09:35:25 -04:00
Andreas Hansson
6596059d05 Configs: Fix memtest cache latency to match new parameters
This patch changes the memtest config to use the new response latency
of the cache model.
2012-09-27 08:59:25 -04:00
Andreas Hansson
9d9b71e485 Configs: Fix memtest.py by moving the system port
The memtest.py script used to connect the system port directly to the
SimpleMemory, but the latter is now single ported. Since the system
port is not used for anything in this particular example, a quick fix
is to attach it to the functional bus instead.
2012-09-27 03:24:21 -04:00
Mrinmoy Ghosh
6fc0094337 Cache: add a response latency to the caches
In the current caches the hit latency is paid twice on a miss. This patch lets
a configurable response latency be set of the cache for the backward path.
2012-09-25 11:49:41 -05:00
Andreas Hansson
fccbf8bb45 AddrRange: Simplify AddrRange params Python hierarchy
This patch simplifies the Range object hierarchy in preparation for an
address range class that also allows striping (e.g. selecting a few
bits as matching in addition to the range).

To extend the AddrRange class to an AddrRegion, the first step is to
simplify the hierarchy such that we can make it as lean as possible
before adding the new functionality. The only class using Range and
MetaRange is AddrRange, and the three classes are now collapsed into
one.
2012-09-19 06:15:41 -04:00
Joel Hestness
90dd745ff6 se.py Ruby: Connect TLB walker ports
In order to ensure correct functionality of switch CPUs, the TLB walker ports
must be connected to the Ruby system in x86 simulation.

This fixes x86 assertion failures that the TLB walker ports are not connected
during the CPU switch process.
2012-09-12 21:42:57 -05:00
Joel Hestness
234fa4cf7e Standard Switch: Drain the system before switching CPUs
When switching from an atomic CPU to any of the timing CPUs, a drain is
unnecessary since no events are scheduled in atomic mode. However, when
trying to switch CPUs starting with a timing CPU, there may be events
scheduled. This change ensures that all events are drained from the system
by calling m5.drain before switching CPUs.
2012-09-12 21:41:37 -05:00
Nilay Vaish
89a5ba1ef8 se.py: removes error in passing options to a binary 2012-09-11 17:47:21 -05:00
Andreas Hansson
9ad7e23e9e Checkpoint: Pass maxtick to avoid undefined variable
This patch fixes a bug in scriptCheckpoints, where maxtick was used
undefined. The bug caused checkpointing by means of --take-checkpoints
to fail.
2012-09-11 14:14:51 -04:00
Nilay Vaish
0b45ae5df3 se.py: support specifying multiple programs via command line
This patch allows for specifying multiple programs via command line. It also
adds an option for specifying whether to use of SMT. But SMT does not work for
the o3 cpu as of now.
2012-09-09 09:33:45 -05:00
Andreas Hansson
a6074016e2 Bridge: Remove NACKs in the bridge and unify with packet queue
This patch removes the NACKing in the bridge, as the split
request/response busses now ensure that protocol deadlocks do not
occur, i.e. the message-dependency chain is broken by always allowing
responses to make progress without being stalled by requests. The
NACKs had limited support in the system with most components ignoring
their use (with a suitable call to panic), and as the NACKs are no
longer needed to avoid protocol deadlocks, the cleanest way is to
simply remove them.

The bridge is the starting point as this is the only place where the
NACKs are created. A follow-up patch will remove the code that deals
with NACKs in the endpoints, e.g. the X86 table walker and DMA
port. Ultimately the type of packet can be complete removed (until
someone sees a need for modelling more complex protocols, which can
now be done in parts of the system since the port and interface is
split).

As a consequence of the NACK removal, the bridge now has to send a
retry to a master if the request or response queue was full on the
first attempt. This change also makes the bridge ports very similar to
QueuedPorts, and a later patch will change the bridge to use these. A
first step in this direction is taken by aligning the name of the
member functions, as done by this patch.

A bit of tidying up has also been done as part of the simplifications.

Surprisingly, this patch has no impact on any of the
regressions. Hence, there was never any NACKs issued. In a follow-up
patch I would suggest changing the size of the bridge buffers set in
FSConfig.py to also test the situation where the bridge fills up.
2012-08-22 11:39:58 -04:00
Andreas Hansson
4ebefc145a Checkpoint: Fix broken checkpointing functionality
This patch fixes the checkpointing by ensuring that the directory is
passer to the scriptCheckpoints function, and that the num_checkpoints
is not used before it is initialised.
2012-08-21 05:48:52 -04:00
Jason Power
44b4c96253 Ruby: Add RubySystem parameter to MemoryControl
This guarantees that RubySystem object is created before the MemoryController
object is created.
2012-08-16 23:39:36 -05:00
Anthony Gutierrez
5a648f2074 configs: add option for repeatedly switching back-and-forth between cpu types.
This patch adds a --repeat-switch option that will enable repeat core
switching at a user defined period (set with --switch-freq option).
currently, a switch can only occur between like CPU types. inorder CPU
switching is not supported.

*note*
this patch simply allows a config that will perform repeat switching, it
does not fix drain/switchout functionality. if you run with repeat switching
you will hit assertion failures and/or your workload with hang or die.
2012-08-15 10:38:07 -04:00
Jason Power
11411cc9c7 Ruby: Clean up topology changes
This patch moves instantiateTopology into Ruby.py and removes the
mem/ruby/network/topologies directory. It also adds some extra inheritance to
the topologies to clean up some issues in the existing topologies.
2012-08-10 13:50:42 -05:00
Nilay Vaish
62425b7a07 Simulation.py: move code related to checkpointing to functions
This patch moves the code related to checkpointing from the run() function to
several different functions. The aim is to make the code more manageable. No
functionality changes are expected, but since the code is kind of unruly, it
is possible that some change might have creeped in.
2012-08-06 18:14:32 -05:00
Nilay Vaish
d81a51a4c8 Config: change how cpu class is set
This changes the way in which the cpu class while restoring from a checkpoint
is set. Earlier it was assumed if cpu type with which to restore is not same
as the cpu type with the which to run the simulation, then the checkpoint
should be restored with the atomic cpu. This assumption is being dropped. The
checkpoint can now be restored with any cpu type, the default being atomic cpu.
2012-08-06 18:14:31 -05:00
Andreas Hansson
ae6ab7c03c Config: Use clock option in se/fs script and pass to switch_cpus
This patch changes the se and fs script to use the clock option and
not simply set the CPUs clock to 2 GHz. It also makes a minor change
to the assignment of the switch_cpus clock to allow different clocks.
2012-07-23 09:32:22 -04:00
Andreas Hansson
f00cba34eb Mem: Make SimpleMemory single ported
This patch changes the simple memory to have a single slave port
rather than a vector port. The simple memory makes no attempts at
modelling the contention between multiple ports, and any such
multiplexing and demultiplexing could be done in a bus (or crossbar)
outside the memory controller. This scenario also matches with the
ongoing work on a SimpleDRAM model, which will be a single-ported
single-channel controller that can be used in conjunction with a bus
(or crossbar) to create a multi-port multi-channel controller.

There are only very few regressions that make use of the vector port,
and these are all for functional accesses only. To facilitate these
cases, memtest and memtest-ruby have been updated to also have a
"functional" bus to perform the (de)multiplexing of the functional
memory accesses.
2012-07-12 12:56:13 -04:00
Brad Beckmann
6f9bd33b73 ruby: remove the cpu assumptions for the random tester 2012-07-10 22:51:54 -07:00
Brad Beckmann
11b725c19d ruby: changes how Topologies are created
Instead of just passing a list of controllers to the makeTopology function
in src/mem/ruby/network/topologies/<Topo>.py we pass in a function pointer
which knows how to make the topology, possibly with some extra state set
in the configs/ruby/<protocol>.py file. Thus, we can move all of the files
from network/topologies to configs/topologies. A new class BaseTopology
is added which all topologies in configs/topologies must inheirit from and
follow its API.

--HG--
rename : src/mem/ruby/network/topologies/Crossbar.py => configs/topologies/Crossbar.py
rename : src/mem/ruby/network/topologies/Mesh.py => configs/topologies/Mesh.py
rename : src/mem/ruby/network/topologies/MeshDirCorners.py => configs/topologies/MeshDirCorners.py
rename : src/mem/ruby/network/topologies/Pt2Pt.py => configs/topologies/Pt2Pt.py
rename : src/mem/ruby/network/topologies/Torus.py => configs/topologies/Torus.py
2012-07-10 22:51:53 -07:00
Anthony Gutierrez
ce9ac38342 configs: add run scripts for ics/gb versions of android and bbench
1) Modifies Benchmarks.py to add support for Android ICS and BBench on Android ICS.

2) An rcS script is added for BBench on ICS.

3) Separates benchmark entries and rcS scripts for GB/ICS

4) Removes the debugging output from the existing BBench run script. These
   print statements were used for debugging and they seemed to confuse users
   into believing they should see some terminal output.
2012-06-11 11:07:42 -04:00
Nilay Vaish
abb85a68f4 Config: call to setWorkCountOptions() for all ISAs 2012-06-07 08:05:31 -05:00
Nilay Vaish
51c23e601e Config: Remove setMipsOptions
As status matrix, MIPS fs does not work. Hence, these options are not
required. Secondly, the function is setting param values for a CPU class.
This seems strange, should probably be done in a different way.
2012-06-07 08:05:30 -05:00
Nilay Vaish
78a72d6972 Config: changes to a couple of error msgs 2012-06-07 08:05:30 -05:00
Andreas Hansson
0d32940711 Bus: Split the bus into a non-coherent and coherent bus
This patch introduces a class hierarchy of buses, a non-coherent one,
and a coherent one, splitting the existing bus functionality. By doing
so it also enables further specialisation of the two types of buses.

A non-coherent bus connects a number of non-snooping masters and
slaves, and routes the request and response packets based on the
address. The request packets issued by the master connected to a
non-coherent bus could still snoop in caches attached to a coherent
bus, as is the case with the I/O bus and memory bus in most system
configurations. No snoops will, however, reach any master on the
non-coherent bus itself. The non-coherent bus can be used as a
template for modelling PCI, PCIe, and non-coherent AMBA and OCP buses,
and is typically used for the I/O buses.

A coherent bus connects a number of (potentially) snooping masters and
slaves, and routes the request and response packets based on the
address, and also forwards all requests to the snoopers and deals with
the snoop responses. The coherent bus can be used as a template for
modelling QPI, HyperTransport, ACE and coherent OCP buses, and is
typically used for the L1-to-L2 buses and as the main system
interconnect.

The configuration scripts are updated to use a NoncoherentBus for all
peripheral and I/O buses.

A bit of minor tidying up has also been done.

--HG--
rename : src/mem/bus.cc => src/mem/coherent_bus.cc
rename : src/mem/bus.hh => src/mem/coherent_bus.hh
rename : src/mem/bus.cc => src/mem/noncoherent_bus.cc
rename : src/mem/bus.hh => src/mem/noncoherent_bus.hh
2012-05-31 13:30:04 -04:00