gem5/configs
Andreas Sandberg 3db3f83a5e arch: Make the ISA class inherit from SimObject
The ISA class on stores the contents of ID registers on many
architectures. In order to make reset values of such registers
configurable, we make the class inherit from SimObject, which allows
us to use the normal generated parameter headers.

This patch introduces a Python helper method, BaseCPU.createThreads(),
which creates a set of ISAs for each of the threads in an SMT
system. Although it is currently only needed when creating
multi-threaded CPUs, it should always be called before instantiating
the system as this is an obvious place to configure ID registers
identifying a thread/CPU.
2013-01-07 13:05:35 -05:00
..
boot configs: add run scripts for ics/gb versions of android and bbench 2012-06-11 11:07:42 -04:00
common TournamentBP: Fix some bugs with table sizes and counters 2012-12-06 09:31:06 -06:00
example arch: Make the ISA class inherit from SimObject 2013-01-07 13:05:35 -05:00
ruby ruby: add support for prefetching to MESI protocol 2012-12-11 10:05:56 -06:00
splash2 Bus: Split the bus into a non-coherent and coherent bus 2012-05-31 13:30:04 -04:00
topologies Ruby: Clean up topology changes 2012-08-10 13:50:42 -05:00