se.py Ruby: Connect TLB walker ports
In order to ensure correct functionality of switch CPUs, the TLB walker ports must be connected to the Ruby system in x86 simulation. This fixes x86 assertion failures that the TLB walker ports are not connected during the CPU switch process.
This commit is contained in:
parent
234fa4cf7e
commit
90dd745ff6
1 changed files with 3 additions and 0 deletions
|
@ -198,6 +198,9 @@ if options.ruby:
|
|||
# Connect the cpu's cache ports to Ruby
|
||||
system.cpu[i].icache_port = ruby_port.slave
|
||||
system.cpu[i].dcache_port = ruby_port.slave
|
||||
if buildEnv['TARGET_ISA'] == 'x86':
|
||||
system.cpu[i].itb.walker.port = ruby_port.slave
|
||||
system.cpu[i].dtb.walker.port = ruby_port.slave
|
||||
else:
|
||||
system.system_port = system.membus.slave
|
||||
system.physmem.port = system.membus.master
|
||||
|
|
Loading…
Reference in a new issue