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Author SHA1 Message Date
Ali Saidi
81a00fdcfe Allocate the correct number of global registers 
Fix fault formating and code for traps
fix a couple of bugs in the decoder
Cleanup/fix page table entry code
Implement more mmaped iprs, fix numbered tlb insertion code, add function to dump tlb contents
Don't panic if we differ from legion on a tcc instruction because of where legion prints its data and where we print our data

src/arch/sparc/faults.cc:
    Fix fault formating and code for traps
src/arch/sparc/intregfile.hh:
    allocate the correct number of global registers
src/arch/sparc/isa/decoder.isa:
    fix a couple of bugs in the decoder: wrasi should write asi not ccr, done/retry should get hpstate from htstate
src/arch/sparc/pagetable.hh:
    cleanup/fix page table code
src/arch/sparc/tlb.cc:
    implement more mmaped iprs, fix numbered insertion  code, add function to dump tlb contents
src/arch/sparc/tlb.hh:
    add functions to write TagAccess register on tlb miss and to dump all tlb entries for debugging
src/cpu/exetrace.cc:
    dump tlb entries on error, don't consider differences the cycle we take a trap to be bad.

--HG--
extra : convert_revision : d7d771900f6f25219f3dc6a6e51986d342a32e03
 2006-12-09 18:00:40 -05:00
Lisa Hsu
369e10d95a Merge zizzer:/bk/sparcfs 
into  zed.eecs.umich.edu:/z/hsul/work/sparc/m5

src/arch/sparc/ua2005.cc:
    hand merge

--HG--
extra : convert_revision : 5157fa5d7053cb93f73241c63871eaae6f58b8a6
 2006-12-08 15:07:26 -05:00
Lisa Hsu
da6c1f5b09 mostly implemented SOFTINT relevant interrupt stuff. 
src/arch/sparc/interrupts.hh:
    add in thread_context.hh to get access to tc.
    get rid of stubs that don't make sense right now.
    implement checking and get softint interrupts
src/arch/sparc/miscregfile.cc:
    softint should be OR-ed on a write.
src/arch/sparc/miscregfile.hh:
    add some enums for state fields for easy access to bitmasks of HPSTATE and PSTATE regs.
src/arch/sparc/ua2005.cc:
    implement writing SOFTINT, PSTATE, PIL, and HPSTATE properly, add helpful info to panic for bad reg write.

--HG--
extra : convert_revision : d12d1147b508121075ee9be4599693554d4b9eae
 2006-12-08 14:37:31 -05:00
Ali Saidi
ed22eb781d get legion/m5 to first tlb miss fault 
src/arch/sparc/asi.cc:
src/arch/sparc/asi.hh:
    add sparc error asi
src/arch/sparc/faults.cc:
    put a panic in if TL == MaxTL
src/arch/sparc/isa/decoder.isa:
    Hpstate needs to be updated on a done too
src/arch/sparc/miscregfile.cc:
    warn istead of panicing of fprs/fsr accesses
src/arch/sparc/tlb.cc:
    add sparc error register code that just does nothing
    fix a couple of other tlb bugs
src/arch/sparc/ua2005.cc:
    fix implementation of HPSTATE  write
src/cpu/exetrace.cc:
    let exectrate mess up a couple of times before dying
src/python/m5/objects/T1000.py:
    add l2 error status register fake devices

--HG--
extra : convert_revision : ed5dfdfb28633bf36e5ae07d244f7510a02874ca
 2006-12-07 18:50:33 -05:00
Steve Reinhardt
ac32645c27 Change detault regression build from opt to fast. 
--HG--
extra : convert_revision : b6db0254b73a97ab6e3685c90cc9cd30ea274d4f
 2006-12-07 14:41:56 -05:00
Ali Saidi
03be92f23b Handle access to ASI_QUEUE 
Add function for interrupt ASIs
add all the new MISCREGs to the copyMiscRegs() file

src/arch/sparc/asi.cc:
src/arch/sparc/asi.hh:
    Add function for interrupt ASIs
src/arch/sparc/miscregfile.cc:
src/arch/sparc/miscregfile.hh:
    Add QUEUE asi/misc registers
src/arch/sparc/regfile.cc:
    add all the new MISCREGs to the copyMiscRegs() file
src/arch/sparc/tlb.cc:
    Handle access to ASI_QUEUE

--HG--
extra : convert_revision : 7a14450485816e6ee3bc8c80b462a13e1edf0ba0
 2006-12-06 19:25:53 -05:00
Ali Saidi
ecbb8debf6 Many more fixes for SPARC_FS. Gets us to the point where SOFTINT starts 
getting touched.

configs/common/FSConfig.py:
    Physical memory on the T1 starts at 1MB, The first megabyte is unmapped to catch bugs
src/arch/isa_parser.py:
    we should readmiscregwitheffect not readmiscreg
src/arch/sparc/asi.cc:
    Fix AsiIsNucleus spelling with respect to header file
    Add ASI_LSU_CONTROL_REG to AsiSiMmu
src/arch/sparc/asi.hh:
    Fix spelling of two ASIs
src/arch/sparc/isa/decoder.isa:
    switch back to defaults letting the isa_parser insert readMiscRegWithEffect
src/arch/sparc/isa/formats/mem/util.isa:
    Flesh out priviledgedString with hypervisor checks
    Make load alternate set the flags correctly
src/arch/sparc/miscregfile.cc:
    insert some forgotten break statements
src/arch/sparc/miscregfile.hh:
    Add some comments to make it easier to find which misc register is which number
src/arch/sparc/tlb.cc:
    flesh out the tlb memory mapped registers a lot more
src/base/traceflags.py:
    add an IPR traceflag
src/mem/request.hh:
    Fix a bad assert() in request

--HG--
extra : convert_revision : 1e11aa004e8f42c156e224c1d30d49479ebeed28
 2006-12-06 14:29:10 -05:00
Kevin Lim
b618e733bd Fix for MIPS_SE/m5.fast compile. 
--HG--
extra : convert_revision : dbb893250974ac6db7b6c1ba67263fd35098ca43
 2006-12-06 14:23:31 -05:00
Kevin Lim
54a946604b Override default SConscript options and only build the SimpleCPUs. 
--HG--
extra : convert_revision : cfcfb787d8442cb76ed766aa5bc947636f067209
 2006-12-05 11:12:18 -05:00
Steve Reinhardt
2e1200e57f Merge zizzer.eecs.umich.edu:bk/newmem-cache2 
into  vm1.(none):/home/stever/bk/newmem-cache2

--HG--
extra : convert_revision : 0a7d17460f17c96fe869124f54f9c92409495003
 2006-12-05 07:24:13 -08:00
Steve Reinhardt
c50965042f Merge zizzer.eecs.umich.edu:/z/stever/bk/newmem-head 
into  zizzer.eecs.umich.edu:/z/stever/bk/newmem-cache2

--HG--
extra : convert_revision : a5569cef10ab22da1865e368f0bb5e7532772227
 2006-12-05 10:23:20 -05:00
Steve Reinhardt
51b3d7f4de Merge zizzer.eecs.umich.edu:/z/stever/bk/newmem-head 
into  zizzer.eecs.umich.edu:/z/stever/bk/newmem-cache2

--HG--
extra : convert_revision : ca78bf2fc1ddefd56b98a90eaffab57d93026626
 2006-12-05 10:18:35 -05:00
Steve Reinhardt
1c28682cea Don't compress data on writebacks unless it's actually necessary. 
--HG--
extra : convert_revision : 7a068e28f9ea2f6aab57be7133b47bda72d10302
 2006-12-05 07:16:36 -08:00
Steve Reinhardt
a2c315b85f Merge vm1.(none):/home/stever/bk/newmem-head 
into  vm1.(none):/home/stever/bk/newmem-cache2

--HG--
extra : convert_revision : e456687d940c833d8255a88633555778480f7825
 2006-12-04 21:35:48 -08:00
Ali Saidi
4d57cab49a forgot to commit miscreg file 
--HG--
extra : convert_revision : c2ede9efbf7b264c32d5565d3f0fc0601c4cd63b
 2006-12-04 20:29:55 -05:00
Gabe Black
8b1bcc3f52 Merge zizzer:/bk/sparcfs 
into  zower.eecs.umich.edu:/eecshome/m5/newmemmid

--HG--
extra : convert_revision : 45d9599dd883e10c283812c1c241c20323f44cec
 2006-12-04 19:56:04 -05:00
Gabe Black
251f4e1134 Add in code to pass the ASI to translation. 
--HG--
extra : convert_revision : 4a985635cda7680abcddaf0bc9579fa03d5bc7c6
 2006-12-04 19:55:52 -05:00
Lisa Hsu
2de685cc21 Merge zizzer:/bk/sparcfs 
into  zed.eecs.umich.edu:/z/hsul/work/sparc/m5

--HG--
extra : convert_revision : 3186d6055794b41c26eb8d2411903869b5b39329
 2006-12-04 19:39:58 -05:00
Ali Saidi
8e75b6e2a5 reogranize code to split off FS only misc regs with effect into their own file (reducing the number of if FULL_SYSTEM defines and includes) 
Protect other pieces of code so that sparc compiles SE again

src/arch/sparc/SConscript:
    Add ua2005.cc back into SConscript
src/arch/sparc/miscregfile.hh:
    add functions that deal with priv registers so we don't have to have a bunch of if defs and other ugliness
src/arch/sparc/mmaped_ipr.hh:
    wrap handleIpr* with if full_system so it compiles under se
src/arch/sparc/ua2005.cc:
    reorganize edit fs only miscreg functions
src/cpu/exetrace.cc:
    protect legion code so it doesn't try to compile under se

--HG--
extra : convert_revision : 6b3c9f6f95b4da8544525f4f82e92861383ede76
 2006-12-04 19:39:57 -05:00
Lisa Hsu
e86832bed8 automatically build sparc system or alpha system. 
configs/example/fs.py:
    make it an automatic system build for alpha vs. sparc.

--HG--
extra : convert_revision : 4c217cf9309c6209be7f80e358f6640857a785e8
 2006-12-04 19:37:50 -05:00
Steve Reinhardt
6c1b311faf Merge zizzer.eecs.umich.edu:/bk/newmem 
into  vm1.(none):/home/stever/bk/newmem-head

--HG--
extra : convert_revision : df2b33a629ae4298c4da33383b491e3cbefab92d
 2006-12-04 16:10:50 -08:00
Steve Reinhardt
9d39407500 Update SPEC CPU2000 tests with actual benchmark output. 
tests/long/00.gzip/ref/alpha/linux/o3-timing/config.ini:
tests/long/00.gzip/ref/alpha/linux/o3-timing/config.out:
tests/long/00.gzip/ref/alpha/linux/o3-timing/m5stats.txt:
tests/long/00.gzip/ref/alpha/linux/o3-timing/stderr:
tests/long/00.gzip/ref/alpha/linux/o3-timing/stdout:
tests/long/00.gzip/ref/alpha/linux/simple-atomic/config.ini:
tests/long/00.gzip/ref/alpha/linux/simple-atomic/config.out:
tests/long/00.gzip/ref/alpha/linux/simple-atomic/m5stats.txt:
tests/long/00.gzip/ref/alpha/linux/simple-atomic/stderr:
tests/long/00.gzip/ref/alpha/linux/simple-atomic/stdout:
tests/long/00.gzip/ref/alpha/linux/simple-timing/config.ini:
tests/long/00.gzip/ref/alpha/linux/simple-timing/config.out:
tests/long/00.gzip/ref/alpha/linux/simple-timing/m5stats.txt:
tests/long/00.gzip/ref/alpha/linux/simple-timing/stderr:
tests/long/00.gzip/ref/alpha/linux/simple-timing/stdout:
tests/long/30.eon/ref/alpha/linux/simple-atomic/config.ini:
tests/long/30.eon/ref/alpha/linux/simple-atomic/config.out:
tests/long/30.eon/ref/alpha/linux/simple-atomic/m5stats.txt:
tests/long/30.eon/ref/alpha/linux/simple-atomic/stderr:
tests/long/30.eon/ref/alpha/linux/simple-atomic/stdout:
tests/long/30.eon/ref/alpha/linux/simple-timing/config.ini:
tests/long/30.eon/ref/alpha/linux/simple-timing/config.out:
tests/long/30.eon/ref/alpha/linux/simple-timing/m5stats.txt:
tests/long/30.eon/ref/alpha/linux/simple-timing/stderr:
tests/long/30.eon/ref/alpha/linux/simple-timing/stdout:
tests/long/40.perlbmk/ref/alpha/linux/simple-atomic/config.ini:
tests/long/40.perlbmk/ref/alpha/linux/simple-atomic/config.out:
tests/long/40.perlbmk/ref/alpha/linux/simple-atomic/m5stats.txt:
tests/long/40.perlbmk/ref/alpha/linux/simple-atomic/stderr:
tests/long/40.perlbmk/ref/alpha/linux/simple-atomic/stdout:
tests/long/40.perlbmk/ref/alpha/linux/simple-timing/config.ini:
tests/long/40.perlbmk/ref/alpha/linux/simple-timing/config.out:
tests/long/40.perlbmk/ref/alpha/linux/simple-timing/m5stats.txt:
tests/long/40.perlbmk/ref/alpha/linux/simple-timing/stderr:
tests/long/40.perlbmk/ref/alpha/linux/simple-timing/stdout:
tests/long/50.vortex/ref/alpha/linux/o3-timing/config.ini:
tests/long/50.vortex/ref/alpha/linux/o3-timing/config.out:
tests/long/50.vortex/ref/alpha/linux/o3-timing/m5stats.txt:
tests/long/50.vortex/ref/alpha/linux/o3-timing/stderr:
tests/long/50.vortex/ref/alpha/linux/o3-timing/stdout:
tests/long/50.vortex/ref/alpha/linux/simple-atomic/config.ini:
tests/long/50.vortex/ref/alpha/linux/simple-atomic/config.out:
tests/long/50.vortex/ref/alpha/linux/simple-atomic/m5stats.txt:
tests/long/50.vortex/ref/alpha/linux/simple-atomic/stderr:
tests/long/50.vortex/ref/alpha/linux/simple-atomic/stdout:
tests/long/50.vortex/ref/alpha/linux/simple-timing/config.ini:
tests/long/50.vortex/ref/alpha/linux/simple-timing/config.out:
tests/long/50.vortex/ref/alpha/linux/simple-timing/m5stats.txt:
tests/long/50.vortex/ref/alpha/linux/simple-timing/stderr:
tests/long/50.vortex/ref/alpha/linux/simple-timing/stdout:
tests/long/60.bzip2/ref/alpha/linux/o3-timing/config.ini:
tests/long/60.bzip2/ref/alpha/linux/o3-timing/config.out:
tests/long/60.bzip2/ref/alpha/linux/o3-timing/m5stats.txt:
tests/long/60.bzip2/ref/alpha/linux/o3-timing/stderr:
tests/long/60.bzip2/ref/alpha/linux/o3-timing/stdout:
tests/long/60.bzip2/ref/alpha/linux/simple-atomic/config.ini:
tests/long/60.bzip2/ref/alpha/linux/simple-atomic/config.out:
tests/long/60.bzip2/ref/alpha/linux/simple-atomic/m5stats.txt:
tests/long/60.bzip2/ref/alpha/linux/simple-atomic/stderr:
tests/long/60.bzip2/ref/alpha/linux/simple-atomic/stdout:
tests/long/60.bzip2/ref/alpha/linux/simple-timing/config.ini:
tests/long/60.bzip2/ref/alpha/linux/simple-timing/config.out:
tests/long/60.bzip2/ref/alpha/linux/simple-timing/m5stats.txt:
tests/long/60.bzip2/ref/alpha/linux/simple-timing/stderr:
tests/long/60.bzip2/ref/alpha/linux/simple-timing/stdout:
tests/long/70.twolf/ref/alpha/linux/o3-timing/config.ini:
tests/long/70.twolf/ref/alpha/linux/o3-timing/config.out:
tests/long/70.twolf/ref/alpha/linux/o3-timing/m5stats.txt:
tests/long/70.twolf/ref/alpha/linux/o3-timing/stderr:
tests/long/70.twolf/ref/alpha/linux/o3-timing/stdout:
tests/long/70.twolf/ref/alpha/linux/simple-atomic/config.ini:
tests/long/70.twolf/ref/alpha/linux/simple-atomic/config.out:
tests/long/70.twolf/ref/alpha/linux/simple-atomic/m5stats.txt:
tests/long/70.twolf/ref/alpha/linux/simple-atomic/stderr:
tests/long/70.twolf/ref/alpha/linux/simple-atomic/stdout:
tests/long/70.twolf/ref/alpha/linux/simple-timing/config.ini:
tests/long/70.twolf/ref/alpha/linux/simple-timing/config.out:
tests/long/70.twolf/ref/alpha/linux/simple-timing/m5stats.txt:
tests/long/70.twolf/ref/alpha/linux/simple-timing/stderr:
tests/long/70.twolf/ref/alpha/linux/simple-timing/stdout:
    Update with actual benchmark output.

--HG--
extra : convert_revision : 12e8de58172dd717d9cc8c5c27dd926a7257153c
 2006-12-04 19:07:00 -05:00
Steve Reinhardt
34a1f9e14e Only update stderr, stdout, m5stats.txt, and config.* on update_ref, 
since we don't know which of the other files are outputs and which
are inputs.

--HG--
extra : convert_revision : b038bd15930721ab9fceb0a18ab5c895aacb5309
 2006-12-04 19:05:09 -05:00
Steve Reinhardt
66a9697c49 Clean up SPEC CPU2000 reference files. 
Get rid of reference files for o3-atomic (non-existent configuration)
and mcf (doesn't seem to be working).
Left in empty refs for parser/simple-timing... this appears to be
dying because it's running out of memory, so maybe it will be OK
once we get the memory leak fixed.

--HG--
extra : convert_revision : ae3bc8dfec44d09a2a084da5041ec386fe16be8b
 2006-12-04 18:57:17 -05:00
Ali Saidi
db427bb3a9 delete m5stats which shouldn't have been commited 
--HG--
extra : convert_revision : cc9f65c94145e957ea96e0b765ae2ea0ae093029
 2006-12-04 18:25:21 -05:00
Ali Saidi
153e02a435 Legion actually writes to tl-1 in the data structure, so we need to compare correctly 
--HG--
extra : convert_revision : 60fef1bd5dc03d7b107150dba922dd4a3f51626f
 2006-12-04 18:22:55 -05:00
Lisa Hsu
0d62558d55 Merge zizzer:/bk/sparcfs 
into  zed.eecs.umich.edu:/z/hsul/work/sparc/m5

--HG--
extra : convert_revision : 3bce43982689e9bda3a12e21a24b5ea390f347b8
 2006-12-04 17:51:07 -05:00
Steve Reinhardt
5fbf3aa471 Turn cache MissQueue/BlockingBuffer into virtual object 
instead of template parameter.

--HG--
extra : convert_revision : fce0fbd041149b9c781eb23f480ba84fddbfd4a0
 2006-12-04 09:10:53 -08:00
Steve Reinhardt
51e3688701 Better handling of scons -u targets. 
--HG--
extra : convert_revision : 7bf0688a1c83d8385b77a59a1c75040e9624c0ae
 2006-12-04 09:09:36 -08:00
Steve Reinhardt
6b9903f426 SConstruct: 
Couple minor fixes.

SConstruct:
    Couple minor fixes.

--HG--
extra : convert_revision : 25f3c12570287334c2cbd1cf9b8227043a57e7d1
 2006-12-04 08:59:53 -08:00
Steve Reinhardt
6ae75ac958 import os.path.join as joinpath 
--HG--
extra : convert_revision : 200612675e49908b9ff9c965aede35a657241391
 2006-12-04 08:55:06 -08:00
Ali Saidi
92c5a5c8cb More changes to get SPARC fs closer. Now at 1.2M cycles before difference 
configs/common/FSConfig.py:
    seperate the hypervisor memory and the guest0 memory. In reality we're going to need a better way to do this at some point. Perhaps auto generating the hv-desc image based on the specified config.
src/arch/sparc/isa/decoder.isa:
    change reads/writes to the [hs]tick(cmpr) registers to use readmiscregwitheffect
src/arch/sparc/miscregfile.cc:
    For niagra stick and tick are aliased to one value (if we end up doing mps we might not want this).
    Use instruction count from cpu rather than cycles because that is what legion does
    we can change it back after were done with legion
src/base/bitfield.hh:
    add a new function mbits() that just masks off bits of interest but doesn't shift
src/cpu/base.cc:
src/cpu/base.hh:
    add instruction count to cpu
src/cpu/exetrace.cc:
src/cpu/m5legion_interface.h:
    compare instruction count between legion and m5 too
src/cpu/simple/atomic.cc:
    change asserts of packet success to if panics wrapped with NDEBUG defines
    so we can get some more useful information when we have a bad address
src/dev/isa_fake.cc:
src/dev/isa_fake.hh:
src/python/m5/objects/Device.py:
    expand isa fake a bit more having data for each size request, the ability to have writes update the data and to warn on accesses
src/python/m5/objects/System.py:
    convert some tabs to spaces
src/python/m5/objects/T1000.py:
    add more fake devices for each l1 bank and each memory controller

--HG--
extra : convert_revision : 8024ae07b765a04ff6f600e5875b55d8a7d3d276
 2006-12-04 00:54:40 -05:00
Steve Reinhardt
7a1120ab20 Merge vm1.(none):/home/stever/bk/newmem-head 
into  vm1.(none):/home/stever/bk/newmem-cache2

--HG--
extra : convert_revision : 321f7fcc8bd6c6aaaab92d10172814f4d07d5e65
 2006-12-02 22:26:40 -08:00
Steve Reinhardt
e6d7e8af21 Support better param conversions to/from numeric subclasses. 
--HG--
extra : convert_revision : 2ccb75b0912a384789458710fd9bbb65626f839e
 2006-12-02 22:24:52 -08:00
Steve Reinhardt
4c0014a187 Fix help strings on GenRepl params. 
--HG--
extra : convert_revision : 520814e193b9e86b6410f3ab98d62ed131d295aa
 2006-12-02 22:23:46 -08:00
Steve Reinhardt
6f94c3c8d7 Make cache compression policy a runtime virtual thing 
instead of a template policy.

--HG--
extra : convert_revision : 6a4ac7a189a950390a973fdfce94f56190de92db
 2006-12-02 22:22:58 -08:00
Steve Reinhardt
1431d1f9c2 Merge zizzer.eecs.umich.edu:/bk/newmem 
into  vm1.(none):/home/stever/bk/newmem-head

--HG--
extra : convert_revision : 4a077b463b938c54b546b00e586d8609c24ae465
 2006-12-02 22:12:26 -08:00
Steve Reinhardt
711dc47e8c Delete src/oldmem. 
util/make_release.py:
    src/oldmem gone from repo, no need to delete here.

--HG--
extra : convert_revision : 570fa1b8d7144376cf13a010160a39d1c1cccbc2
 2006-12-03 01:11:24 -05:00
Steve Reinhardt
d3e888ff90 Merge zizzer.eecs.umich.edu:/bk/newmem 
into  vm1.(none):/home/stever/bk/newmem-head

--HG--
extra : convert_revision : 4c8de6e4c6f729c83e92abd81ea6c1347e647756
 2006-12-02 19:52:26 -08:00
Kevin Lim
c0f21b09c8 Fixes for MIPS_SE compiling. Regressions seem to work, but Korey should make sure these changes (commit especially) work okay. 
src/cpu/o3/commit_impl.hh:
src/cpu/o3/fetch_impl.hh:
    Fixes for MIPS_SE compile.

--HG--
extra : convert_revision : fde9616f8e72b397c5ca965774172372cff53790
 2006-12-02 13:33:46 -05:00
Lisa Hsu
dc9438b157 stats update 
--HG--
extra : convert_revision : b47d3817d204a43e0afb89aafc8dacf619c3f910
 2006-12-02 11:11:58 -05:00
Nathan Binkert
5d637417a8 don't blow away the whole destination directory 
--HG--
extra : convert_revision : 7370bad15cc30e75ebb0c8685324d8db06fc2936
 2006-12-01 22:33:18 -08:00
Lisa Hsu
55b4ea0444 Merge zizzer:/bk/sparcfs 
into  zed.eecs.umich.edu:/z/hsul/work/sparc/m5

--HG--
extra : convert_revision : 07119747d9b08ea51f21942e36f22afcc62f16e1
 2006-12-01 15:04:48 -05:00
Lisa Hsu
ed50763135 change this to be a quick one so that it's in the regressions every night - it's only maybe 15 min. long. 
tests/configs/twosys-tsunami-simple-atomic.py:
    don't need this import

--HG--
rename : tests/long/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini => tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini
rename : tests/long/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.out => tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.out
rename : tests/long/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/console.drivesys.sim_console => tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/console.drivesys.sim_console
rename : tests/long/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/console.testsys.sim_console => tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/console.testsys.sim_console
rename : tests/long/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/m5stats.txt => tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/m5stats.txt
rename : tests/long/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stderr => tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stderr
rename : tests/long/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stdout => tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stdout
rename : tests/long/80.netperf-stream/test.py => tests/quick/80.netperf-stream/test.py
extra : convert_revision : 68497b2ef8b21590cb6c636485703e46dc616513
 2006-12-01 13:51:49 -05:00
Lisa Hsu
66832866be Merge zizzer:/bk/newmem 
into  zed.eecs.umich.edu:/z/hsul/work/m5/newmem

--HG--
extra : convert_revision : b62ca8009105aad7173bdbc5d528de243d21a82c
 2006-12-01 01:24:16 -05:00
Lisa Hsu
161b8d1a23 add a simple netperf-stream test to the long tests. 
tests/SConscript:
    add a new configuration for two-system tests (atomic simple only)

--HG--
extra : convert_revision : 16c260ab16f38779fe17b1cab18f36d5c7a70846
 2006-12-01 01:24:01 -05:00
Nathan Binkert
472073baaf Merge zizzer.eecs.umich.edu:/bk/newmem 
into  iceaxe.:/Volumes/work/m5/incoming

--HG--
extra : convert_revision : 05060a06e0b6d66a9c1e7005c233047c6e8ba15f
 2006-11-30 20:53:30 -08:00
Nathan Binkert
6e885ec9ba Get rid of the old release-edits script and create make_release.py 
which takes care of almost everything needed for putting together
a release.

--HG--
extra : convert_revision : b05d418a1002633b1286591eb8a8588ba33f5df1
 2006-11-30 20:50:47 -08:00
Ali Saidi
8c4f7a0404 Load the hypervisor symbols twice, once with an address mask so that we can get symbols for where it's copied to in memory 
Add the ability to use an address mask for symbol loading
Rather then silently failing on platform accesses panic
Move BadAddr/IsaFake no Device from Tsunami
Let the system kernel be none, but warn about it

configs/common/FSConfig.py:
    We don't have a kernel for sparc yet
src/arch/sparc/system.cc:
    Load the hypervisor symbols twice, once with an address mask so that we can get symbols for where it's copied to in memory
src/base/loader/aout_object.cc:
src/base/loader/aout_object.hh:
src/base/loader/ecoff_object.cc:
src/base/loader/ecoff_object.hh:
src/base/loader/elf_object.cc:
src/base/loader/elf_object.hh:
src/base/loader/object_file.hh:
src/base/loader/raw_object.cc:
src/base/loader/raw_object.hh:
    Add the ability to use an address mask for symbol loading
src/dev/sparc/t1000.cc:
    Rather then silently failing on platform accesses panic
src/dev/sparc/t1000.hh:
    fix up a couple of platform comments
src/python/m5/objects/Bus.py:
src/python/m5/objects/Device.py:
src/python/m5/objects/T1000.py:
src/python/m5/objects/Tsunami.py:
    Move BadAddr/IsaFake no Device from Tsunami
src/python/m5/objects/System.py:
    Let kernel be none
src/sim/system.cc:
    Let the system kernel be none, but warn about it

--HG--
extra : convert_revision : 92f6afef599a3d3c7c5026d03434102c41c7b5f4
 2006-11-30 15:51:54 -05:00
Ron Dreslinski
e38e893016 Update stats to match writeback fix that was made 
--HG--
extra : convert_revision : 3e0ed2b374d8d96798ea9b3416c9e5579cafacda
 2006-11-30 15:01:49 -05:00