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Ali Saidi ed22eb781d get legion/m5 to first tlb miss fault
src/arch/sparc/asi.cc:
src/arch/sparc/asi.hh:
    add sparc error asi
src/arch/sparc/faults.cc:
    put a panic in if TL == MaxTL
src/arch/sparc/isa/decoder.isa:
    Hpstate needs to be updated on a done too
src/arch/sparc/miscregfile.cc:
    warn istead of panicing of fprs/fsr accesses
src/arch/sparc/tlb.cc:
    add sparc error register code that just does nothing
    fix a couple of other tlb bugs
src/arch/sparc/ua2005.cc:
    fix implementation of HPSTATE  write
src/cpu/exetrace.cc:
    let exectrate mess up a couple of times before dying
src/python/m5/objects/T1000.py:
    add l2 error status register fake devices

--HG--
extra : convert_revision : ed5dfdfb28633bf36e5ae07d244f7510a02874ca
2006-12-07 18:50:33 -05:00
build_opts Add o3-timing configuration for ALPHA_SE "Hello world" tests. 2006-09-01 17:59:36 -04:00
configs Many more fixes for SPARC_FS. Gets us to the point where SOFTINT starts 2006-12-06 14:29:10 -05:00
ext New directory structure: 2006-05-22 14:29:33 -04:00
src get legion/m5 to first tlb miss fault 2006-12-07 18:50:33 -05:00
tests change this to be a quick one so that it's in the regressions every night - it's only maybe 15 min. long. 2006-12-01 13:51:49 -05:00
util Get rid of the old release-edits script and create make_release.py 2006-11-30 20:50:47 -08:00
AUTHORS AUTHORS: 2006-08-17 00:44:54 -04:00
LICENSE Remove authors from copyright. 2006-05-28 23:26:15 -04:00
README Update for 2.0 beta 1 patch 1 2006-08-25 15:17:25 -04:00
RELEASE_NOTES add 2.0b2 release notes 2006-11-28 16:02:13 -05:00
SConstruct Add in O3CPU to default CPU list. 2006-11-29 11:50:03 -05:00

This is release 2.0_beta (patch 1) of the M5 simulator.

For detailed information about building the simulator and getting
started please refer to http://www.m5sim.org.

Specific pages of interest are:
http://www.m5sim.org/wiki/index.php/Compiling_M5
http://www.m5sim.org/wiki/index.php/Running_M5

Short version:

1. If you don't have SCons version 0.96.91 or newer, get it from
http://wwww.scons.org.

2. If you don't have SWIG version 1.3.28 or newer, get it from
http://wwww.swig.org.

3. In this directory, type 'scons build/ALPHA_SE/tests/debug/quick'.  This
will build the debug version of the m5 binary (m5.debug) for the Alpha
syscall emulation target, and run the quick regression tests on it.

If you have questions, please send mail to m5-users@m5sim.org

WHAT'S INCLUDED (AND NOT)
-------------------------

The basic source release includes these subdirectories:
 - m5: 
   - src: source code of the m5 simulator
   - tests: regression tests
   - ext: less-common external packages needed to build m5
   - system/alpha: source for Alpha console and PALcode

To run full-system simulations, you will need compiled console,
PALcode, and kernel binaries and one or more disk images.  These files
are collected in a separate archive, m5_system.tar.bz2.  This file
can he downloaded separately.

M5 supports Linux 2.4/2.6, FreeBSD, and the proprietary Compaq/HP
Tru64 version of Unix. We are able to distribute Linux and FreeBSD
bootdisks, but we are unable to distribute bootable disk images of
Tru64 Unix. If you have a Tru64 license and are interested in
obtaining disk images, contact us at m5-dev@eecs.umich.edu.