Commit graph

8181 commits

Author SHA1 Message Date
Brad Beckmann
48b58b3332 ruby: fixed cache index setting 2011-03-25 10:13:50 -07:00
Gabe Black
6db65b40c1 Arm: Add in a missing miscRegName. 2011-03-25 00:46:14 -04:00
Gabe Black
475685df49 Arm: Get rid of unused and incomplete setCp15Register and readCp15Register. 2011-03-24 14:39:00 -04:00
Gabe Black
5d09a78dce Arm: Get rid of the unused copyStringArray32 method from Arm process classes. 2011-03-24 14:00:15 -04:00
Gabe Black
57ed5e77fe ISA parser: Set up op_src_decl and op_dest_decl for pc operands. 2011-03-24 13:55:16 -04:00
Tushar Krishna
531f54fb51 This patch fixes a build error in networktest.cc that occurs with gcc4.2 2011-03-22 23:38:09 -04:00
Nilay Vaish
1764ebbf30 Ruby: Remove CacheMsg class from SLICC
The goal of the patch is to do away with the CacheMsg class currently in use
in coherence protocols. In place of CacheMsg, the RubyRequest class will used.
This class is already present in slicc_interface/RubyRequest.hh. In fact,
objects of class CacheMsg are generated by copying values from a RubyRequest
object.
2011-03-22 06:41:54 -05:00
Tushar Krishna
46cce440be This patch makes garnet use the info about active and inactive vnets during allocation and power estimations etc 2011-03-21 22:51:59 -04:00
Tushar Krishna
1b9002eefc fix garnet fleible pipeline 2011-03-21 22:51:59 -04:00
Tushar Krishna
09c3a97a4c This patch adds the network tester for simple and garnet networks.
The tester code is in testers/networktest.
The tester can be invoked by configs/example/ruby_network_test.py.
A dummy coherence protocol called Network_test is also addded for network-only simulations and testing. The protocol takes in messages from the tester and just pushes them into the network in the appropriate vnet, without storing any state.
2011-03-21 22:51:58 -04:00
Nilay Vaish
d7aa794155 SLICC: Remove WakeUp* import calls from ast/__init__.py
I had recently committed a patch that removed the WakeUp*.py files from the
slicc/ast directory. I had forgotten to remove the import  calls for these
files from slicc/ast/__init__.py. This resulted in error while running
regressions on zizzer. This patch does the needful.
2011-03-20 09:23:27 -05:00
Lisa Hsu
8957b09da1 configs: combine ruby_se.py and se.py to avoid all that code duplication 2011-03-19 21:13:04 -07:00
Lisa Hsu
0e75e3fd5f enable x86 workloads on se.py 2011-03-19 21:13:02 -07:00
Lisa Hsu
5103c6fe88 se.py: Modify script to make multiprogramming much easier.
Now, instead of --bench benchname, you can do --bench bench1-bench2-bench3 and it will
set up a simulation that instantiates those three workloads.  Only caveat is that now,
for sanity checking, your -n X must match the number of benches in the list.
2011-03-19 21:12:59 -07:00
Lisa Hsu
83664630ee util: update aggregator to handle x86 checkpoints.
Also, make update to understand some of the newer serialized variables
2011-03-19 21:12:55 -07:00
Nilay Vaish
611f052e96 Ruby: Convert CacheRequestType to RubyRequestType
This patch converts CacheRequestType to RubyRequestType so that both the
protocol dependent and independent code makes use of the same request type.
2011-03-19 18:34:59 -05:00
Nilay Vaish
2f4276448b Ruby: Convert AccessModeType to RubyAccessMode
This patch converts AccessModeType to RubyAccessMode so that both the
protocol dependent and independent code uses the same access mode.
2011-03-19 18:34:37 -05:00
Brad Beckmann
dd9083115e MOESI_hammer: minor fixes to full-bit dir 2011-03-19 14:17:48 -07:00
Brad Beckmann
541fa1091a Ruby: dma retry fix
This patch fixes the problem where Ruby would fail to call sendRetry on ports
after it nacked the port.  This patch is particularly helpful for bursty dma
requests which often include several packets.
2011-03-19 14:17:48 -07:00
Brad Beckmann
d1cecc2241 RubyPort: minor fixes to trace flag and dprintfs 2011-03-19 14:17:48 -07:00
Brad Beckmann
8e61805a21 ruby: added useful dma progress dprintf 2011-03-19 14:17:48 -07:00
Brad Beckmann
08d73529bc slicc: improved invalid transition message 2011-03-19 14:17:48 -07:00
Brad Beckmann
31d0a421a9 MOESI_hammer: fixed dma bug with shared data 2011-03-19 14:17:48 -07:00
Brad Beckmann
a2e98f191f MOESI_CMP_directory: significant dma bug fixes 2011-03-19 14:17:48 -07:00
Nilay Vaish
18142df5b9 SLICC: Remove external_type for structures
In SLICC, in order to define a type a data type for which it should not
generate any code, the keyword external_type is used. For those data types for
which code should be generated, the keyword structure is used. This patch
eliminates the use of keyword external_type for defining structures. structure
key word can now have an optional attribute external, which would be used for
figuring out whether or not to generate the code for this structure. Also, now
structures can have functions as well data members in them.
2011-03-18 14:12:04 -05:00
Nilay Vaish
3f27ccbb54 SLICC: Remove the keyword wake_up_dependents
In order to add stall and wait facility for protocols, a keyword
wake_up_dependents was introduced. This patch removes the keyword,
instead this functionality is now implemented as function call.
2011-03-18 14:12:03 -05:00
Nilay Vaish
847ba941ea SLICC: Remove the keyword wake_up_all_dependents
In order to add stall and wait facility for protocols, a keyword
wake_up_all_dependents was introduced. This patch removes the keyword,
instead this functionality is now implemented as function call.
2011-03-18 14:12:01 -05:00
Steve Reinhardt
cc14689a86 swig: get rid of m5.internal.random module (swig/random.i)
Thanks to swig this was interfering with the standard Python
random module.  The only function in that module was seed(),
which erroneously called srand48().  Moved the function to
m5.internal.core, renamed it seedRandom(), and made it call
random_mt.init() instead.
2011-03-18 11:47:15 -07:00
Steve Reinhardt
38aa50bb49 base: disable FastAlloc in debug builds by default
FastAlloc's reuse policies can mask allocation bugs, so
we typically want it disabled when debugging.  Set
FORCE_FAST_ALLOC to enable even when debugging, and set
NO_FAST_ALLOC to disable even in non-debug builds.
2011-03-18 11:47:11 -07:00
Ali Saidi
6daf44dae6 Automated merge with ssh://hg@repo.m5sim.org/m5 2011-03-17 19:24:37 -05:00
Ali Saidi
63eb337b3b ARM: Update stats for the previous changes and add ARM_FS/O3 regression. 2011-03-17 19:20:22 -05:00
Chris Emmons
ccaaa98b49 ARM: Add minimal ARM_SE support for m5threads.
Updated some of the assembly code sequences to use armv7 instructions and
coprocessor 15 for storing the TLS pointer.
2011-03-17 19:20:20 -05:00
Ali Saidi
53ab306acc ARM: Fix subtle bug in LDM.
If the instruction faults mid-op the base register shouldn't be written back.
2011-03-17 19:20:20 -05:00
Ali Saidi
4c7a7796ad ARM: Implement the Instruction Set Attribute Registers (ISAR).
The ISAR registers describe which features the processor supports.
Transcribe the values listed in section B5.2.5 of the ARM ARM
into the registers as read-only values
2011-03-17 19:20:20 -05:00
Ali Saidi
5480ec798a ARM: Identify branches as conditional or unconditional and direct or indirect. 2011-03-17 19:20:20 -05:00
Ali Saidi
887e9e2b99 ARM: Bare metal system should have 256MB of RAM. 2011-03-17 19:20:20 -05:00
Ali Saidi
b754ad85c0 ARM: Fix small bug with VLDM/VSTM instructions. 2011-03-17 19:20:20 -05:00
Ali Saidi
b78be240cf ARM: Detect and skip udelay() functions in linux kernel.
This change speeds up booting, especially in MP cases, by not executing
udelay() on the core but instead skipping ahead tha amount of time that is being
delayed.
2011-03-17 19:20:20 -05:00
Ali Saidi
fe3d790ac8 ARM: Allow conditional quiesce instructions.
This patch prevents not executed conditional instructions marked as
IsQuiesce from stalling the pipeline indefinitely. If the instruction
is not executed the quiesceSkip psuedoinst is called which schedules a
wakes up call to the fetch stage.
2011-03-17 19:20:20 -05:00
Ali Saidi
845f791f37 Stats: Update the statistics for rfe patch. 2011-03-17 19:20:20 -05:00
Matt Horsnell
031f396c71 ARM: Fix RFE macrop.
This changes the RFE macroop into 3 microops:

URa = [sp]; URb = [sp+4]; // load CPSR,PC values from stack
sp = sp + offset;         // optionally auto-increment
PC = URa; CPSR = URb;     // write to the PC and CPSR.

Importantly:
- writing to PC is handled in the last micro-op.
- loading occurs prior to state changes.
2011-03-17 19:20:19 -05:00
Matt Horsnell
e65f480d62 ARM: Rename registers used as temporary state by microops. 2011-03-17 19:20:19 -05:00
Ali Saidi
799c3da8d0 O3: Send instruction back to fetch on squash to seed predecoder correctly. 2011-03-17 19:20:19 -05:00
Ali Saidi
30143baf7e O3: Cleanup the commitInfo comm struct.
Get rid of unused members and use base types rather than derrived values
where possible to limit amount of state.
2011-03-17 19:20:19 -05:00
Ali Saidi
db35053655 ARM: Previous change didn't end up setting instFlags, this does. 2011-03-17 19:20:19 -05:00
Ali Saidi
7112b44362 O3: Update regressions for mem block caching change. 2011-03-17 19:20:19 -05:00
Ali Saidi
a432d8e085 Mem: Fix issue with dirty block being lost when entire block transferred to non-cache.
This change fixes the problem for all the cases we actively use. If you want to try
more creative I/O device attachments (E.g. sharing an L2), this won't work. You
would need another level of caching between the I/O device and the cache
(which you actually need anyway with our current code to make sure writes
propagate). This is required so that you can mark the cache in between as
top level and it won't try to send ownership of a block to the I/O device.
Asserts have been added that should catch any issues.
2011-03-17 19:20:19 -05:00
Ali Saidi
2f40b3b8ae O3: Fix unaligned stores when cache blocked
Without this change the a store can be issued to the cache multiple times.
If this case occurs when the l1 cache is out of mshrs (and thus blocked)
the processor will never make forward progress because each cycle it will
send a single request using the recently freed mshr and not completing the
multipart store. This will continue forever.
2011-03-17 19:20:19 -05:00
Lisa Hsu
c4de6a0522 Ruby: minor bugfix, line did not adhere to some macro usage conventions. 2011-03-17 17:08:35 -07:00
Lisa Hsu
556b5c5488 Ruby: expose a simple mod function in slicc interface. 2011-03-17 17:01:41 -07:00