Ali Saidi
34a8e37c13
SE: Fix simulating more than 4GB of RAM in SE mode
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This change removes some dead code in PhysicalMemory, uses a 64 bit type
for the page pointer in System (instead of 32 bit) and cleans up some style.
2010-11-19 18:01:01 -06:00
Ali Saidi
5c6f4a0f17
SCons: Fix compilation on OS X
2010-11-19 18:00:59 -06:00
Ali Saidi
e1b9a815dd
SCons: Support building without an ISA
2010-11-19 18:00:39 -06:00
Gabe Black
92655b6399
O3: Fix fp destination register flattening, and index offset adjusting.
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This change makes O3 flatten floating point destination registers, and also
fixes misc register flattening so that it's correctly repositioned relative to
the resized regions for integer and floating point indices.
It also fixes some overly long lines.
2010-11-18 13:11:36 -05:00
Gabe Black
4876e0c92b
Config: Change misleading "cycle" message to say "tick".
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Most of the messages in the config scripts that report a time value already
print "@ tick" followed by the current tick value, but a few were printing
"@ cycle". Since this is a distinction that's frequently confusing to new
users, this changes those message to the more accurate and consistent "@ tick".
2010-11-17 23:16:19 -05:00
Gabe Black
0e41d4e5ea
Stats: Update the O3 fetch stats for SPARC.
2010-11-15 19:37:15 -08:00
Gabe Black
8b9b85e92c
O3: Make O3 support variably lengthed instructions.
2010-11-15 19:37:03 -08:00
Ali Saidi
776c075917
O3: reset architetural state by calling clear()
2010-11-15 14:04:05 -06:00
Ali Saidi
5f59e195d6
ARM: Add comment about the organization of the IT state register
2010-11-15 14:04:05 -06:00
Ali Saidi
371110fb0a
Regressions: Update regressions for SIMD opclass changes
2010-11-15 14:04:05 -06:00
Giacomo Gabrielli
0058927190
CPU/ARM: Add SIMD op classes to CPU models and ARM ISA.
2010-11-15 14:04:04 -06:00
Ali Saidi
2a3cefe151
ARM: Compile O3 CPU by default
2010-11-15 14:04:04 -06:00
Min Kyu Jeong
745df74fe0
O3: prevent a squash when completeAcc() modifies misc reg through TC.
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This happens on ARM instructions when they update the IT state bits.
Code and associated comment was copied from execute() and initiateAcc() methods
2010-11-15 14:04:04 -06:00
Ali Saidi
4a1814bd52
ARM: Return an FailUnimp instruction when an unimplemented CP15 register is accessed.
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Just panicing in readMiscReg() doesn't work because a speculative access
in the o3 model can end the simulation.
2010-11-15 14:04:04 -06:00
Ali Saidi
d4767f440a
SCons: Cleanup SCons output during compile
2010-11-15 14:04:04 -06:00
Ali Saidi
c370866331
ARM: Update regressions for CLCD and KMI additions
2010-11-15 14:04:03 -06:00
William Wang
6fbea15064
ARM: Add a Keyboard Mouse Interface controller
2010-11-15 14:04:03 -06:00
William Wang
fc1eeafc94
ARM: Implement a CLCD Frame buffer
2010-11-15 14:04:03 -06:00
William Wang
80db6a5ecb
ARM: Add support for GDB on ARM
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--HG--
rename : src/arch/alpha/remote_gdb.cc => src/arch/arm/remote_gdb.cc
2010-11-15 14:04:03 -06:00
Ali Saidi
06864386a1
ARM: Make utility.hh meet style guidelines
2010-11-15 14:04:03 -06:00
Ali Saidi
d7b8efa0df
ARM: Add support for a dumb IDE controller
2010-11-15 14:04:03 -06:00
Ali Saidi
13931b9b82
ARM: Cache the misc regs at the TLB to limit readMiscReg() calls.
2010-11-15 14:04:03 -06:00
Ali Saidi
4c2e5c282b
ARM: Add support for switching CPUs
2010-11-15 14:04:03 -06:00
Ali Saidi
08c5673d56
ARM: Use the correct delete operator for RFE
2010-11-15 14:04:03 -06:00
Ali Saidi
50431f4eab
ARM: Fix SRS instruction to micro-code memory operation and register update.
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Previously the SRS instruction attempted to writeback in initiateAcc() which
worked until a recent change, but was incorrect.
2010-11-15 14:04:03 -06:00
Ali Saidi
16f210da37
CPU: Fix bug when a split transaction is issued to a faster cache
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In the case of a split transaction and a cache that is faster than a CPU we
could get two responses before next_tick expires. Add an event that is
scheduled in this case and return false rather than asserting.
2010-11-15 14:04:03 -06:00
Ali Saidi
265e145db2
ARM: Do something predictable for an UNPREDICTABLE branch.
2010-11-15 14:04:03 -06:00
Gabe Black
46472279c0
Params: Fix an off by one error and a misleading comment.
2010-11-11 11:58:09 -08:00
Gabe Black
3c237f44c9
SimObject: Add a comment near clear_child that it's unlikely to be called.
2010-11-11 11:41:13 -08:00
Gabe Black
cdc585e0e8
SPARC: Clean up some historical style issues.
2010-11-11 02:03:58 -08:00
Ali Saidi
0b7967d606
Update EIO regressions for last set of patches
2010-11-10 00:48:03 -06:00
Gabe Black
14b27fc302
scons: Work around for old versions of scons mistaking strings for sequences.
2010-11-09 11:03:40 -08:00
Gabe Black
2fd9dc19cd
SimObject: Use "self" when calling the clear_child method.
2010-11-09 10:45:02 -08:00
Gabe Black
388124492e
X86: Fix X86_FS compilation.
2010-11-08 12:43:38 -08:00
Ali Saidi
06c5283930
ARM: Update SE stats for TLB stats additions
2010-11-08 13:59:35 -06:00
Ali Saidi
fe300c6de2
ARM: Add full-system regressions
2010-11-08 13:58:25 -06:00
Ali Saidi
057b451773
ARM: Add some TLB statistics for ARM
2010-11-08 13:58:25 -06:00
Ali Saidi
a1e8225975
ARM: Add checkpointing support
2010-11-08 13:58:25 -06:00
Ali Saidi
432fa0aad6
ARM: Add support for M5 ops in the ARM ISA
2010-11-08 13:58:24 -06:00
Ali Saidi
0f2bbe15dd
ARM: Keep the warnings to a minimum.
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These warnings still need to be addresses, but pages of them is
counterproductive.
2010-11-08 13:58:24 -06:00
Ali Saidi
c779af4e12
Mem: Finish half-baked support for mmaping file in physmem.
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Physmem has a parameter to be able to mem map a file, however
it isn't actually used. This changeset utilizes the parameter
so a file can be mmapped.
2010-11-08 13:58:24 -06:00
Ali Saidi
ea1167dd9f
Bus: Have the I/O devices that return address ranges print them out.
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This way we actually get device names associated with the devices.
2010-11-08 13:58:24 -06:00
Ali Saidi
e6c31ceb2b
ARM: Don't return the result of a table walk the same cycle it's completed.
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The L1 cache may have been accessed to provide this data, which confuses
it, if it ends up being accesses twice in one cycle. Instead wait 1 tick
which will force the timing simple CPU to forward to its next clock cycle
when the translation completes.
Also prevent multiple outstanding table walks from occuring at once.
2010-11-08 13:58:24 -06:00
Ali Saidi
5fcf442f4f
scons: add a parameter to configure SCons' build cache
2010-11-08 13:58:24 -06:00
Ali Saidi
b4b6a2338a
ARM/Alpha/Cpu: Stats change for prefetchs to be more like normal loads.
2010-11-08 13:58:24 -06:00
Ali Saidi
cdacbe734a
ARM/Alpha/Cpu: Change prefetchs to be more like normal loads.
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This change modifies the way prefetches work. They are now like normal loads
that don't writeback a register. Previously prefetches were supposed to call
prefetch() on the exection context, so they executed with execute() methods
instead of initiateAcc() completeAcc(). The prefetch() methods for all the CPUs
are blank, meaning that they get executed, but don't actually do anything.
On Alpha dead cache copy code was removed and prefetches are now normal ops.
They count as executed operations, but still don't do anything and IsMemRef is
not longer set on them.
On ARM IsDataPrefetch or IsInstructionPreftech is now set on all prefetch
instructions. The timing simple CPU doesn't try to do anything special for
prefetches now and they execute with the normal memory code path.
2010-11-08 13:58:22 -06:00
Ali Saidi
f4f5d03ed2
ARM: Make all ARM uops delayed commit.
2010-11-08 13:58:22 -06:00
Ali Saidi
0ea794bcf4
sim: Use forward declarations for ports.
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Virtual ports need TLB data which means anything touching a file in the arch
directory rebuilds any file that includes system.hh which in everything.
2010-11-08 13:58:22 -06:00
Gabe Black
72b5262278
scons: Replace the build_dir parameter to SConscript with variant_dir.
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The build_dir parameter name has been deprecated and replaced with
variant_dir. This change switches us over to avoid warning spew in newer
versions of scons.
2010-11-06 17:48:58 -07:00
Gabe Black
b53231e7fe
Ref output: Update refs for PCState change.
2010-10-31 00:07:48 -07:00
