ARM: Return an FailUnimp instruction when an unimplemented CP15 register is accessed.
Just panicing in readMiscReg() doesn't work because a speculative access in the o3 model can end the simulation.
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@ -173,11 +173,10 @@ ISA::readMiscReg(int misc_reg, ThreadContext *tc)
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cpsr.t = pc.thumb() ? 1 : 0;
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return cpsr;
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}
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if (misc_reg >= MISCREG_CP15_UNIMP_START &&
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misc_reg < MISCREG_CP15_END) {
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if (misc_reg >= MISCREG_CP15_UNIMP_START)
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panic("Unimplemented CP15 register %s read.\n",
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miscRegName[misc_reg]);
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}
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switch (misc_reg) {
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case MISCREG_CLIDR:
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warn_once("The clidr register always reports 0 caches.\n");
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@ -180,6 +180,10 @@ let {{
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// Read/write, priveleged only.
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default:
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if (miscReg >= MISCREG_CP15_UNIMP_START)
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return new FailUnimplemented(csprintf("%s %s",
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isRead ? "mrc" : "mcr", miscRegName[miscReg]).c_str(),
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machInst);
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if (isRead) {
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return new Mrc15(machInst, rt, (IntRegIndex)miscReg);
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} else {
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