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ARM: Add support for M5 ops in the ARM ISA

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This commit is contained in:
Ali Saidi 2010-11-08 13:58:24 -06:00
parent 0f2bbe15dd
commit 432fa0aad6
12 changed files with 648 additions and 3 deletions
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8
src/arch/arm/isa/decoder/arm.isa
View file

@ -90,7 +90,12 @@ format DataOp {
0x0: ArmParallelAddSubtract::armParallelAddSubtract();
0x1: ArmPackUnpackSatReverse::armPackUnpackSatReverse();
0x2: ArmSignedMultiplies::armSignedMultiplies();
0x3: ArmMiscMedia::armMiscMedia();
0x3: decode MEDIA_OPCODE {
0x1F: decode OPC2 {
default: ArmMiscMedia::armMiscMedia();
}
default: ArmMiscMedia::armMiscMedia();
}
}
}
0x4: ArmMacroMem::armMacroMem();
@ -107,6 +112,7 @@ format DataOp {
0xa, 0xb: VfpData::vfpData();
} // CPNUM
1: decode CPNUM { // 27-24=1110,4 ==1
0x1: M5ops::m5ops();
0xa, 0xb: ShortFpTransfer::shortFpTransfer();
0xf: McrMrc15::mcrMrc15();
} // CPNUM (OP4 == 1)

3
src/arch/arm/isa/decoder/thumb.isa
View file

@ -84,6 +84,7 @@ decode BIGTHUMB {
default: WarnUnimpl::cdp(); // cdp2
}
0x1: decode LTCOPROC {
0x1: M5ops::m5ops();
0xa, 0xb: ShortFpTransfer::shortFpTransfer();
0xf: McrMrc15::mcrMrc15();
}
@ -125,7 +126,6 @@ decode BIGTHUMB {
0x0: LoadByteMemoryHints::loadByteMemoryHints();
0x1: LoadHalfwordMemoryHints::loadHalfwordMemoryHints();
0x2: Thumb32LoadWord::thumb32LoadWord();
0x3: Unknown::undefined();
}
}
0x1: decode HTOPCODE_8_7 {
@ -140,6 +140,7 @@ decode BIGTHUMB {
default: WarnUnimpl::cdp(); // cdp2
}
0x1: decode LTCOPROC {
0x1: M5ops::m5ops();
0xa, 0xb: ShortFpTransfer::shortFpTransfer();
0xf: McrMrc15::mcrMrc15();
}

3
src/arch/arm/isa/formats/formats.isa
View file

@ -79,3 +79,6 @@
//Unconditional instructions
##include "uncond.isa"
//M5 Psuedo-ops
##include "m5ops.isa"

78
src/arch/arm/isa/formats/m5ops.isa Normal file
View file

@ -0,0 +1,78 @@
//
// Copyright (c) 2010 ARM Limited
// All rights reserved
//
// The license below extends only to copyright in the software and shall
// not be construed as granting a license to any other intellectual
// property including but not limited to intellectual property relating
// to a hardware implementation of the functionality of the software
// licensed hereunder. You may use the software subject to the license
// terms below provided that you ensure that this notice is replicated
// unmodified and in its entirety in all distributions of the software,
// modified or unmodified, in source code or in binary form.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met: redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer;
// redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution;
// neither the name of the copyright holders nor the names of its
// contributors may be used to endorse or promote products derived from
// this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
// Authors: Gene Wu
///
def format M5ops() {{
decode_block = '''
{
const uint32_t m5func = bits(machInst, 23, 16);
switch(m5func) {
#if FULL_SYSTEM
case 0x00: return new Arm(machInst);
case 0x01: return new Quiesce(machInst);
case 0x02: return new QuiesceNs(machInst);
case 0x03: return new QuiesceCycles(machInst);
case 0x04: return new QuiesceTime(machInst);
#endif
case 0x07: return new Rpns(machInst);
case 0x09: return new WakeCPU(machInst);
case 0x10: return new Deprecated_ivlb(machInst);
case 0x11: return new Deprecated_ivle(machInst);
case 0x20: return new Deprecated_exit (machInst);
case 0x21: return new M5exit(machInst);
#if FULL_SYSTEM
case 0x31: return new Loadsymbol(machInst);
case 0x30: return new Initparam(machInst);
#endif
case 0x40: return new Resetstats(machInst);
case 0x41: return new Dumpstats(machInst);
case 0x42: return new Dumpresetstats(machInst);
case 0x43: return new M5checkpoint(machInst);
#if FULL_SYSTEM
case 0x50: return new M5readfile(machInst);
#endif
case 0x51: return new M5break(machInst);
case 0x52: return new M5switchcpu(machInst);
#if FULL_SYSTEM
case 0x53: return new M5addsymbol(machInst);
#endif
case 0x54: return new M5panic(machInst);
}
}
'''
}};

1
src/arch/arm/isa/includes.isa
View file

@ -86,6 +86,7 @@ output exec {{
#include <fenv.h>
#endif
#include "base/cp_annotate.hh"
#include "mem/packet.hh"
#include "mem/packet_access.hh"
#include "sim/sim_exit.hh"

3
src/arch/arm/isa/insts/insts.isa
View file

@ -75,3 +75,6 @@
//Neon
##include "neon.isa"
//m5 Psuedo-ops
##include "m5ops.isa"

275
src/arch/arm/isa/insts/m5ops.isa Normal file
View file

@ -0,0 +1,275 @@
//
// Copyright (c) 2010 ARM Limited
// All rights reserved
//
// The license below extends only to copyright in the software and shall
// not be construed as granting a license to any other intellectual
// property including but not limited to intellectual property relating
// to a hardware implementation of the functionality of the software
// licensed hereunder. You may use the software subject to the license
// terms below provided that you ensure that this notice is replicated
// unmodified and in its entirety in all distributions of the software,
// modified or unmodified, in source code or in binary form.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met: redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer;
// redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution;
// neither the name of the copyright holders nor the names of its
// contributors may be used to endorse or promote products derived from
// this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
// Authors: Gene Wu
let {{
header_output = ""
decoder_output = ""
exec_output = ""
armCode = '''
#if FULL_SYSTEM
PseudoInst::arm(xc->tcBase());
#endif
'''
armIop = InstObjParams("arm", "Arm", "PredOp",
{ "code": armCode,
"predicate_test": predicateTest },
["IsNonSpeculative"])
header_output += BasicDeclare.subst(armIop)
decoder_output += BasicConstructor.subst(armIop)
exec_output += PredOpExecute.subst(armIop)
quiesceCode = '''
#if FULL_SYSTEM
PseudoInst::quiesceNs(xc->tcBase(), R0);
#endif
'''
quiesceIop = InstObjParams("quiesce", "Quiesce", "PredOp",
{ "code": quiesceCode,
"predicate_test": predicateTest },
["IsNonSpeculative", "IsQuiesce"])
header_output += BasicDeclare.subst(quiesceIop)
decoder_output += BasicConstructor.subst(quiesceIop)
exec_output += PredOpExecute.subst(quiesceIop)
quiesceNsCode = '''
#if FULL_SYSTEM
PseudoInst::quiesceNs(xc->tcBase(), R0);
#endif
'''
quiesceNsIop = InstObjParams("quiesceNs", "QuiesceNs", "PredOp",
{ "code": quiesceNsCode,
"predicate_test": predicateTest },
["IsNonSpeculative", "IsQuiesce"])
header_output += BasicDeclare.subst(quiesceNsIop)
decoder_output += BasicConstructor.subst(quiesceNsIop)
exec_output += PredOpExecute.subst(quiesceNsIop)
quiesceCyclesCode = '''
#if FULL_SYSTEM
PseudoInst::quiesceCycles(xc->tcBase(), R0);
#endif
'''
quiesceCyclesIop = InstObjParams("quiesceCycles", "QuiesceCycles", "PredOp",
{ "code": quiesceCyclesCode,
"predicate_test": predicateTest },
["IsNonSpeculative", "IsQuiesce", "IsUnverifiable"])
header_output += BasicDeclare.subst(quiesceCyclesIop)
decoder_output += BasicConstructor.subst(quiesceCyclesIop)
exec_output += PredOpExecute.subst(quiesceCyclesIop)
quiesceTimeCode = '''
#if FULL_SYSTEM
R0 = PseudoInst::quiesceTime(xc->tcBase());
#endif
'''
quiesceTimeIop = InstObjParams("quiesceTime", "QuiesceTime", "PredOp",
{ "code": quiesceTimeCode,
"predicate_test": predicateTest },
["IsNonSpeculative", "IsUnverifiable"])
header_output += BasicDeclare.subst(quiesceTimeIop)
decoder_output += BasicConstructor.subst(quiesceTimeIop)
exec_output += PredOpExecute.subst(quiesceTimeIop)
rpnsIop = InstObjParams("rpns", "Rpns", "PredOp",
{ "code": "R0 = PseudoInst::rpns(xc->tcBase());",
"predicate_test": predicateTest },
["IsNonSpeculative", "IsUnverifiable"])
header_output += BasicDeclare.subst(rpnsIop)
decoder_output += BasicConstructor.subst(rpnsIop)
exec_output += PredOpExecute.subst(rpnsIop)
wakeCPUIop = InstObjParams("wakeCPU", "WakeCPU", "PredOp",
{ "code": "PseudoInst::wakeCPU(xc->tcBase(), R0);",
"predicate_test": predicateTest },
["IsNonSpeculative", "IsUnverifiable"])
header_output += BasicDeclare.subst(wakeCPUIop)
decoder_output += BasicConstructor.subst(wakeCPUIop)
exec_output += PredOpExecute.subst(wakeCPUIop)
deprecated_ivlbIop = InstObjParams("deprecated_ivlb", "Deprecated_ivlb", "PredOp",
{ "code": '''warn_once("Obsolete M5 ivlb instruction encountered.\\n");''',
"predicate_test": predicateTest })
header_output += BasicDeclare.subst(deprecated_ivlbIop)
decoder_output += BasicConstructor.subst(deprecated_ivlbIop)
exec_output += PredOpExecute.subst(deprecated_ivlbIop)
deprecated_ivleIop = InstObjParams("deprecated_ivle", "Deprecated_ivle", "PredOp",
{ "code": '''warn_once("Obsolete M5 ivle instruction encountered.\\n");''',
"predicate_test": predicateTest })
header_output += BasicDeclare.subst(deprecated_ivleIop)
decoder_output += BasicConstructor.subst(deprecated_ivleIop)
exec_output += PredOpExecute.subst(deprecated_ivleIop)
deprecated_exit_code = '''
warn_once("Obsolete M5 exit instruction encountered.\\n");
PseudoInst::m5exit(xc->tcBase(), 0);
'''
deprecated_exitIop = InstObjParams("deprecated_exit", "Deprecated_exit", "PredOp",
{ "code": deprecated_exit_code,
"predicate_test": predicateTest },
["No_OpClass", "IsNonSpeculative"])
header_output += BasicDeclare.subst(deprecated_exitIop)
decoder_output += BasicConstructor.subst(deprecated_exitIop)
exec_output += PredOpExecute.subst(deprecated_exitIop)
m5exitIop = InstObjParams("m5exit", "M5exit", "PredOp",
{ "code": "PseudoInst::m5exit(xc->tcBase(), R0)",
"predicate_test": predicateTest },
["No_OpClass", "IsNonSpeculative"])
header_output += BasicDeclare.subst(m5exitIop)
decoder_output += BasicConstructor.subst(m5exitIop)
exec_output += PredOpExecute.subst(m5exitIop)
loadsymbolCode = '''
#if FULL_SYSTEM
PseudoInst::loadsymbol(xc->tcBase());
#endif
'''
loadsymbolIop = InstObjParams("loadsymbol", "Loadsymbol", "PredOp",
{ "code": loadsymbolCode,
"predicate_test": predicateTest },
["No_OpClass", "IsNonSpeculative"])
header_output += BasicDeclare.subst(loadsymbolIop)
decoder_output += BasicConstructor.subst(loadsymbolIop)
exec_output += PredOpExecute.subst(loadsymbolIop)
initparamCode = '''
#if FULL_SYSTEM
Rt = xc->tcBase()->getCpuPtr()->system->init_param;
#endif
'''
initparamIop = InstObjParams("initparam", "Initparam", "PredOp",
{ "code": initparamCode,
"predicate_test": predicateTest })
header_output += BasicDeclare.subst(initparamIop)
decoder_output += BasicConstructor.subst(initparamIop)
exec_output += PredOpExecute.subst(initparamIop)
resetstatsIop = InstObjParams("resetstats", "Resetstats", "PredOp",
{ "code": "PseudoInst::resetstats(xc->tcBase(), R0, R1);",
"predicate_test": predicateTest },
["IsNonSpeculative"])
header_output += BasicDeclare.subst(resetstatsIop)
decoder_output += BasicConstructor.subst(resetstatsIop)
exec_output += PredOpExecute.subst(resetstatsIop)
dumpstatsIop = InstObjParams("dumpstats", "Dumpstats", "PredOp",
{ "code": "PseudoInst::dumpstats(xc->tcBase(), R0, R1);",
"predicate_test": predicateTest },
["IsNonSpeculative"])
header_output += BasicDeclare.subst(dumpstatsIop)
decoder_output += BasicConstructor.subst(dumpstatsIop)
exec_output += PredOpExecute.subst(dumpstatsIop)
dumpresetstatsIop = InstObjParams("dumpresetstats", "Dumpresetstats", "PredOp",
{ "code": "PseudoInst::dumpresetstats(xc->tcBase(), R0, R1);",
"predicate_test": predicateTest },
["IsNonSpeculative"])
header_output += BasicDeclare.subst(dumpresetstatsIop)
decoder_output += BasicConstructor.subst(dumpresetstatsIop)
exec_output += PredOpExecute.subst(dumpresetstatsIop)
m5checkpointIop = InstObjParams("m5checkpoint", "M5checkpoint", "PredOp",
{ "code": "PseudoInst::m5checkpoint(xc->tcBase(), R0, R1);",
"predicate_test": predicateTest },
["IsNonSpeculative"])
header_output += BasicDeclare.subst(m5checkpointIop)
decoder_output += BasicConstructor.subst(m5checkpointIop)
exec_output += PredOpExecute.subst(m5checkpointIop)
m5readfileCode = '''
#if FULL_SYSTEM
R0 = PseudoInst::readfile(xc->tcBase(), R0, R1, R2);
#endif
'''
m5readfileIop = InstObjParams("m5readfile", "M5readfile", "PredOp",
{ "code": m5readfileCode,
"predicate_test": predicateTest },
["IsNonSpeculative"])
header_output += BasicDeclare.subst(m5readfileIop)
decoder_output += BasicConstructor.subst(m5readfileIop)
exec_output += PredOpExecute.subst(m5readfileIop)
m5breakIop = InstObjParams("m5break", "M5break", "PredOp",
{ "code": "PseudoInst::debugbreak(xc->tcBase());",
"predicate_test": predicateTest },
["IsNonSpeculative"])
header_output += BasicDeclare.subst(m5breakIop)
decoder_output += BasicConstructor.subst(m5breakIop)
exec_output += PredOpExecute.subst(m5breakIop)
m5switchcpuIop = InstObjParams("m5switchcpu", "M5switchcpu", "PredOp",
{ "code": "PseudoInst::switchcpu(xc->tcBase());",
"predicate_test": predicateTest },
["IsNonSpeculative"])
header_output += BasicDeclare.subst(m5switchcpuIop)
decoder_output += BasicConstructor.subst(m5switchcpuIop)
exec_output += PredOpExecute.subst(m5switchcpuIop)
m5addsymbolCode = '''
#if FULL_SYSTEM
PseudoInst::addsymbol(xc->tcBase(), R0, R1);
#endif
'''
m5addsymbolIop = InstObjParams("m5addsymbol", "M5addsymbol", "PredOp",
{ "code": m5addsymbolCode,
"predicate_test": predicateTest },
["IsNonSpeculative"])
header_output += BasicDeclare.subst(m5addsymbolIop)
decoder_output += BasicConstructor.subst(m5addsymbolIop)
exec_output += PredOpExecute.subst(m5addsymbolIop)
m5panicCode = '''panic("M5 panic instruction called at pc=%#x.",
xc->pcState().pc());'''
m5panicIop = InstObjParams("m5panic", "M5panic", "PredOp",
{ "code": m5panicCode,
"predicate_test": predicateTest },
["IsNonSpeculative"])
header_output += BasicDeclare.subst(m5panicIop)
decoder_output += BasicConstructor.subst(m5panicIop)
exec_output += PredOpExecute.subst(m5panicIop)
}};

3
src/arch/arm/isa/operands.isa
View file

@ -170,6 +170,9 @@ def operands {{
'Rn': ('IntReg', 'uw', 'RN', 'IsInteger', 3, maybePCRead, maybePCWrite),
'R7': ('IntReg', 'uw', '7', 'IsInteger', 3),
'R0': ('IntReg', 'uw', '0', 'IsInteger', 3),
'R1': ('IntReg', 'uw', '0', 'IsInteger', 3),
'R2': ('IntReg', 'uw', '1', 'IsInteger', 3),
'Rt' : ('IntReg', 'uw', 'RT', 'IsInteger', 3, maybePCRead, maybePCWrite),
'LR': ('IntReg', 'uw', 'INTREG_LR', 'IsInteger', 3),
'CondCodes': ('IntReg', 'uw', 'INTREG_CONDCODES', None, 3),

2
src/arch/arm/types.hh
View file

@ -141,7 +141,7 @@ namespace ArmISA
Bitfield<2, 0> fpImm;
Bitfield<24, 20> punwl;
Bitfield<7, 0> m5Func;
Bitfield<15, 8> m5Func;
// 16 bit thumb bitfields
Bitfield<15, 13> topcode15_13;

65
util/m5/Makefile.arm Normal file
View file

@ -0,0 +1,65 @@
# Copyright (c) 2010 ARM Limited
# All rights reserved.
#
# The license below extends only to copyright in the software and shall
# not be construed as granting a license to any other intellectual
# property including but not limited to intellectual property relating
# to a hardware implementation of the functionality of the software
# licensed hereunder. You may use the software subject to the license
# terms below provided that you ensure that this notice is replicated
# unmodified and in its entirety in all distributions of the software,
# modified or unmodified, in source code or in binary form.
#
# Copyright (c) 2005-2006 The Regents of The University of Michigan
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are
# met: redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer;
# redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution;
# neither the name of the copyright holders nor the names of its
# contributors may be used to endorse or promote products derived from
# this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
# Authors: Nathan Binkert
# Ali Saidi
### If we are not compiling on an arm, we must use cross tools ###
ifneq ($(shell uname -m), arm)
CROSS_COMPILE?=arm-none-linux-gnueabi-
endif
CC=$(CROSS_COMPILE)gcc
AS=$(CROSS_COMPILE)as
LD=$(CROSS_COMPILE)ld
CFLAGS=-O2
OBJS=m5.o m5op_arm.o
all: m5
%.o: %.S
$(CC) $(CFLAGS) -o $@ -c $<
%.o: %.c
$(CC) $(CFLAGS) -o $@ -c $<
m5: $(OBJS)
$(CC) -o $@ $(OBJS)
clean:
rm -f *.o m5

67
util/m5/Makefile.thumb Normal file
View file

@ -0,0 +1,67 @@
# Copyright (c) 2010 ARM Limited
# All rights reserved.
#
# The license below extends only to copyright in the software and shall
# not be construed as granting a license to any other intellectual
# property including but not limited to intellectual property relating
# to a hardware implementation of the functionality of the software
# licensed hereunder. You may use the software subject to the license
# terms below provided that you ensure that this notice is replicated
# unmodified and in its entirety in all distributions of the software,
# modified or unmodified, in source code or in binary form.
#
# Copyright (c) 2005-2006 The Regents of The University of Michigan
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are
# met: redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer;
# redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution;
# neither the name of the copyright holders nor the names of its
# contributors may be used to endorse or promote products derived from
# this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
# Authors: Nathan Binkert
# Ali Saidi
# Chander Sudanthi
### If we are not compiling on an arm, we must use cross tools ###
ifneq ($(shell uname -m), arm)
CROSS_COMPILE?=arm-none-linux-gnueabi-
endif
CC=$(CROSS_COMPILE)gcc
AS=$(CROSS_COMPILE)as
LD=$(CROSS_COMPILE)ld
#CFLAGS=-O2 -march=armv7 -mthumb
CFLAGS=-O2 -mthumb
OBJS=m5.o m5op_arm.o
all: m5
%.o: %.S
$(CC) $(CFLAGS) -o $@ -c $<
%.o: %.c
$(CC) $(CFLAGS) -o $@ -c $<
m5: $(OBJS)
$(CC) -o $@ -march=armv7 -mthumb $(OBJS)
clean:
rm -f *.o m5

143
util/m5/m5op_arm.S Normal file
View file

@ -0,0 +1,143 @@
/*
* Copyright (c) 2010 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
* not be construed as granting a license to any other intellectual
* property including but not limited to intellectual property relating
* to a hardware implementation of the functionality of the software
* licensed hereunder. You may use the software subject to the license
* terms below provided that you ensure that this notice is replicated
* unmodified and in its entirety in all distributions of the software,
* modified or unmodified, in source code or in binary form.
*
* Copyright (c) 2003-2006 The Regents of The University of Michigan
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met: redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer;
* redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution;
* neither the name of the copyright holders nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Authors: Nathan Binkert
* Ali Saidi
* Chander Sudanthi
*/
#define m5_op 0xEE
#include "m5ops.h"
#define INST(op, ra, rb, func) \
.long (((op) << 24) | ((func) << 16) | ((ra) << 12) | (0x1 << 8) | (0x1 << 4) | (rb))
/* m5ops m5func ra coproc 1 op=1 rb */
#define LEAF(func) \
.globl func; \
func:
#define RET \
mov pc,lr
#define END(func) \
#define SIMPLE_OP(_f, _o) \
LEAF(_f) \
_o; \
RET; \
END(_f)
#define ARM(reg) INST(m5_op, reg, 0, arm_func)
#define QUIESCE INST(m5_op, 0, 0, quiesce_func)
#define QUIESCENS(r1) INST(m5_op, r1, 0, quiescens_func)
#define QUIESCECYC(r1) INST(m5_op, r1, 0, quiescecycle_func)
#define QUIESCETIME INST(m5_op, 0, 0, quiescetime_func)
#define RPNS INST(m5_op, 0, 0, rpns_func)
#define WAKE_CPU(r1) INST(m5_op, r1, 0, wakecpu_func)
#define M5EXIT(reg) INST(m5_op, reg, 0, exit_func)
#define INITPARAM(reg) INST(m5_op, reg, 0, initparam_func)
#define LOADSYMBOL(reg) INST(m5_op, reg, 0, loadsymbol_func)
#define RESET_STATS(r1, r2) INST(m5_op, r1, r2, resetstats_func)
#define DUMP_STATS(r1, r2) INST(m5_op, r1, r2, dumpstats_func)
#define DUMPRST_STATS(r1, r2) INST(m5_op, r1, r2, dumprststats_func)
#define CHECKPOINT(r1, r2) INST(m5_op, r1, r2, ckpt_func)
#define READFILE INST(m5_op, 0, 0, readfile_func)
#define DEBUGBREAK INST(m5_op, 0, 0, debugbreak_func)
#define SWITCHCPU INST(m5_op, 0, 0, switchcpu_func)
#define ADDSYMBOL(r1,r2) INST(m5_op, r1, r2, addsymbol_func)
#define PANIC INST(m5_op, 0, 0, panic_func)
#define AN_BSM INST(m5_op, an_bsm, 0, annotate_func)
#define AN_ESM INST(m5_op, an_esm, 0, annotate_func)
#define AN_BEGIN INST(m5_op, an_begin, 0, annotate_func)
#define AN_END INST(m5_op, an_end, 0, annotate_func)
#define AN_Q INST(m5_op, an_q, 0, annotate_func)
#define AN_RQ INST(m5_op, an_rq, 0, annotate_func)
#define AN_DQ INST(m5_op, an_dq, 0, annotate_func)
#define AN_WF INST(m5_op, an_wf, 0, annotate_func)
#define AN_WE INST(m5_op, an_we, 0, annotate_func)
#define AN_WS INST(m5_op, an_ws, 0, annotate_func)
#define AN_SQ INST(m5_op, an_sq, 0, annotate_func)
#define AN_AQ INST(m5_op, an_aq, 0, annotate_func)
#define AN_PQ INST(m5_op, an_pq, 0, annotate_func)
#define AN_L INST(m5_op, an_l, 0, annotate_func)
#define AN_IDENTIFY INST(m5_op, an_identify, 0, annotate_func)
#define AN_GETID INST(m5_op, an_getid, 0, annotate_func)
.text
SIMPLE_OP(arm, ARM(0))
SIMPLE_OP(quiesce, QUIESCE)
SIMPLE_OP(quiesceNs, QUIESCENS(0))
SIMPLE_OP(quiesceCycle, QUIESCECYC(0))
SIMPLE_OP(quiesceTime, QUIESCETIME)
SIMPLE_OP(rpns, RPNS)
SIMPLE_OP(wakeCPU, WAKE_CPU(0))
SIMPLE_OP(m5_exit, M5EXIT(0))
SIMPLE_OP(m5_initparam, INITPARAM(0))
SIMPLE_OP(m5_loadsymbol, LOADSYMBOL(0))
SIMPLE_OP(m5_reset_stats, RESET_STATS(0, 0))
SIMPLE_OP(m5_dump_stats, DUMP_STATS(0, 1))
SIMPLE_OP(m5_dumpreset_stats, DUMPRST_STATS(0, 1))
SIMPLE_OP(m5_checkpoint, CHECKPOINT(0, 1))
SIMPLE_OP(m5_readfile, READFILE)
SIMPLE_OP(m5_debugbreak, DEBUGBREAK)
SIMPLE_OP(m5_switchcpu, SWITCHCPU)
SIMPLE_OP(m5_addsymbol, ADDSYMBOL(0, 1))
SIMPLE_OP(m5_panic, PANIC)
SIMPLE_OP(m5a_bsm, AN_BSM)
SIMPLE_OP(m5a_esm, AN_ESM)
SIMPLE_OP(m5a_begin, AN_BEGIN)
SIMPLE_OP(m5a_end, AN_END)
SIMPLE_OP(m5a_q, AN_Q)
SIMPLE_OP(m5a_rq, AN_RQ)
SIMPLE_OP(m5a_dq, AN_DQ)
SIMPLE_OP(m5a_wf, AN_WF)
SIMPLE_OP(m5a_we, AN_WE)
SIMPLE_OP(m5a_ws, AN_WS)
SIMPLE_OP(m5a_sq, AN_SQ)
SIMPLE_OP(m5a_aq, AN_AQ)
SIMPLE_OP(m5a_pq, AN_PQ)
SIMPLE_OP(m5a_l, AN_L)
SIMPLE_OP(m5a_identify, AN_IDENTIFY)
SIMPLE_OP(m5a_getid, AN_GETID)