Gabe Black
61a5e71be7
ARM: Decode the thumb version of the ldrd and strd instructions.
2010-06-02 12:58:09 -05:00
Gabe Black
9d4a1bf2ba
ARM: Explicitly keep track of the second destination for double loads/stores.
2010-06-02 12:58:09 -05:00
Gabe Black
28023f6f3d
ARM: Decode the thumb32 load byte/memory hint instructions.
2010-06-02 12:58:09 -05:00
Gabe Black
7a9dcdf99f
ARM: Decode the load halfword, memory hints instructions for 32 bit Thumb.
2010-06-02 12:58:09 -05:00
Gabe Black
a2d8dcebba
ARM: Decode the ldrex instruction.
2010-06-02 12:58:07 -05:00
Gabe Black
952253483b
ARM: Rearrange the load/store double/exclusive, table branch thumb decoding.
2010-06-02 12:58:07 -05:00
Gabe Black
1344fc2668
ARM: Decode the swp and swpb instructions.
2010-06-02 12:58:05 -05:00
Gabe Black
deb6e8f805
ARM: Eliminate the old memory formats which are no longer used.
2010-06-02 12:58:01 -05:00
Gabe Black
55465844dc
ARM: Make the addressing mode 3 loads/stores use the externally defined instructions.
2010-06-02 12:58:01 -05:00
Gabe Black
a86491fbf2
ARM: Decode 16 bit thumb PC relative memory instructions.
2010-06-02 12:58:01 -05:00
Gabe Black
dc8af1b211
ARM: Decode 16 bit thumb immediate addressed memory instructions.
2010-06-02 12:58:01 -05:00
Gabe Black
4bbd73649d
ARM: Decode 16 bit thumb register addressed memory instructions.
2010-06-02 12:58:01 -05:00
Gabe Black
462cf6f49b
ARM: Make single stores decode to the new external store instructions.
2010-06-02 12:58:01 -05:00
Gabe Black
fde3c8f41d
ARM: Make 32 bit thumb use the new, external load instructions.
2010-06-02 12:58:01 -05:00
Gabe Black
3b93015304
ARM: Define the store instructions from outside the decoder.
...
--HG--
rename : src/arch/arm/isa/insts/ldr.isa => src/arch/arm/isa/insts/str.isa
2010-06-02 12:58:01 -05:00
Gabe Black
81fdced83f
ARM: Define the load instructions from outside the decoder.
2010-06-02 12:58:01 -05:00
Steve Reinhardt
4d77ea7a57
cpu: fix exec tracing memory corruption bug
...
Accessing traceData (to call setAddress() and/or setData())
after initiating a timing translation was causing crashes,
since a failed translation could delete the traceData
object before returning.
It turns out that there was never a need to access traceData
after initiating the translation, as the traced data was
always available earlier; this ordering was merely
historical. Furthermore, traceData->setAddress() and
traceData->setData() were being called both from the CPU
model and the ISA definition, often redundantly.
This patch standardizes all setAddress and setData calls
for memory instructions to be in the CPU models and not
in the ISA definition. It also moves those calls above
the translation calls to eliminate the crashes.
2010-03-23 08:50:57 -07:00
Gabe Black
4eb18cc07a
ARM: Improve memory instruction disassembly.
2009-07-08 23:02:19 -07:00
Gabe Black
ddcf084f16
ARM: Get rid of the MemAcc and EAComp static insts.
2009-07-08 23:02:19 -07:00
Gabe Black
311f77f33d
ARM: Add an AddrMode2 format for memory instructions that use address mode 2.
2009-07-08 23:02:19 -07:00
Gabe Black
826a3582ea
ARM: Don't always update CPSR.
2009-07-08 23:02:19 -07:00
Gabe Black
17f0943398
ARM: Add an AddrMode3 format for memory instructions that use address mode 3.
2009-07-08 23:02:19 -07:00
Gabe Black
d4a03f1900
ARM: Simplify the ISA desc by pulling some classes out of it.
2009-06-21 17:21:25 -07:00
Gabe Black
47e71d674a
ARM: Don't downconvert ExtMachInsts to MachInsts.
2009-06-21 16:41:07 -07:00
Gabe Black
5bc1373050
ARM: Get rid of unnecessary fp_enable_checks.
2009-06-21 09:41:04 -07:00
Gabe Black
c20ce20e4c
ARM: Make the isa parser aware that CPSR is being used.
2009-06-21 09:37:41 -07:00
Gabe Black
71e0d1ded2
ARM: Pull some static code out of the isa desc and create miscregs.hh.
2009-06-21 09:21:07 -07:00
Gabe Black
19a1966079
ARM: Get rid of unused postacc_code.
2009-06-21 09:16:55 -07:00
Stephen Hines
7a7c4c5fca
arm: add ARM support to M5
2009-04-05 18:53:15 -07:00
