Commit graph

2867 commits

Author SHA1 Message Date
Kevin Lim
35ab2296d3 Push more default options to the Python object level as they are rarely changed. These are the changes that Steve was working on.
src/python/m5/objects/DiskImage.py:
src/python/m5/objects/Ethernet.py:
src/python/m5/objects/Ide.py:
src/python/m5/objects/Tsunami.py:
    Push more default options to the Python object level as they are rarely changed.

--HG--
extra : convert_revision : 963eb7a34cd04529b3c5f24b92904ab725c93efb
2006-07-12 17:16:00 -04:00
Kevin Lim
807afe8292 Updates for serialization. As long as the tickEvent doesn't need to be serialized (I don't believe it does because we drain all CPUs prior to checkpointing), it should be feasible to start up from other CPU's checkpoints.
src/cpu/simple/atomic.cc:
src/cpu/simple/atomic.hh:
src/cpu/simple/base.cc:
src/cpu/simple/timing.cc:
src/cpu/simple_thread.cc:
    Updates for serialization.

--HG--
extra : convert_revision : 0f150de75d4bc833e4c9b83568e7fd22688d5727
2006-07-12 17:11:57 -04:00
Kevin Lim
185a5502b7 Minor fixes.
src/cpu/checker/thread_context.hh:
src/cpu/ozone/cpu.hh:
src/cpu/ozone/cpu_impl.hh:
    Change functions to match Korey's changes.
src/cpu/ozone/lw_back_end.hh:
    Fix compile error.

--HG--
extra : convert_revision : fb11ac2d6db3a75c1cdbad2c1c02f921ad7344a6
2006-07-10 16:31:42 -04:00
Kevin Lim
5dbd7a3f76 Merge ktlim@zizzer:/bk/newmem
into  zamp.eecs.umich.edu:/z/ktlim2/clean/newmem-merge

--HG--
extra : convert_revision : 0e4c7684879b8552908e0b64a00b4824de807244
2006-07-10 15:41:35 -04:00
Kevin Lim
f60d8217e3 Some minor cleanups.
src/cpu/SConscript:
    Change the error message to be slightly nicer.
src/cpu/o3/commit.hh:
    Remove old code.
src/cpu/o3/commit_impl.hh:
    Remove old unused code.

--HG--
extra : convert_revision : 48aa430e1f3554007dd5e4f3d9e89b5e4f124390
2006-07-10 15:41:28 -04:00
Kevin Lim
fcaafdc48c Add parameters for backwards and forwards sizes for time buffers.
src/base/timebuf.hh:
    Add a function to return the size of the time buffer.

--HG--
extra : convert_revision : 8ffacd8b9013eb76264df065244e00dc1460efd4
2006-07-10 15:40:28 -04:00
Ron Dreslinski
5584e2b26e Update config for a system with an L2
--HG--
extra : convert_revision : c73a532ad6ad8d5115bda81fa778a4b97fbab713
2006-07-10 12:42:35 -04:00
Ron Dreslinski
39ffd24b64 Fix offset calculation. Now L2's work with timing&atomic.
src/mem/packet.hh:
    Offset is based on packet, not request.

--HG--
extra : convert_revision : d85af5838370541328ca35072c612d8198020625
2006-07-10 12:35:18 -04:00
Ron Dreslinski
aef232a942 Update FS configs to use cpu connectors for ports
--HG--
extra : convert_revision : 1e2e503401f92c1f30e2e487d7aeed1c7c5b7ee4
2006-07-10 12:07:21 -04:00
Ron Dreslinski
6c9bde608b Fix cpu in full system to match SE.
--HG--
extra : convert_revision : 95e422221ff5bab6104925d50a8882d31729b0f5
2006-07-10 12:03:13 -04:00
Korey Sewell
cdf27a0a86 Merge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/newmem
into  zizzer.eecs.umich.edu:/.automount/zooks/y/ksewell/research/m5-sim/newmem-o3

--HG--
extra : convert_revision : 9098d989832e2a5818b80771e3c02170c5c8cd5b
2006-07-07 19:02:12 -04:00
Kevin Lim
43245d9c2f Support for recent port changes.
src/cpu/ozone/cpu.hh:
src/cpu/ozone/cpu_impl.hh:
src/cpu/ozone/front_end.hh:
src/cpu/ozone/front_end_impl.hh:
src/cpu/ozone/lw_back_end.hh:
src/cpu/ozone/lw_lsq.hh:
src/cpu/ozone/lw_lsq_impl.hh:
src/python/m5/objects/OzoneCPU.py:
    Support Ron's recent port changes.
src/cpu/ozone/lw_back_end_impl.hh:
    Support Ron's recent port changes.  Also support handling faults in SE.

--HG--
extra : convert_revision : aa1ba5111b70199c052da3e13bae605525a69891
2006-07-07 18:24:13 -04:00
Kevin Lim
8ade33d324 Support Ron's changes for hooking up ports.
src/cpu/checker/cpu.hh:
    Now that BaseCPU is a MemObject, the checker must define this function.
src/cpu/o3/cpu.cc:
src/cpu/o3/cpu.hh:
src/cpu/o3/fetch.hh:
src/cpu/o3/iew.hh:
src/cpu/o3/lsq.hh:
src/cpu/o3/lsq_unit.hh:
    Implement getPort function so the connector can connect the ports properly.
src/cpu/o3/fetch_impl.hh:
src/cpu/o3/lsq_unit_impl.hh:
    The connector handles connecting the ports now.
src/python/m5/objects/O3CPU.py:
    Add ports to the parameters.

--HG--
extra : convert_revision : 0b1a216b9a5d0574e62165d7c6c242498104d918
2006-07-07 17:33:24 -04:00
Kevin Lim
744e0055b7 Fix for bug when draining and a memory access is outstanding.
--HG--
extra : convert_revision : 1af782cf023ae74c2a3ff9f7aefcea880bc87936
2006-07-07 16:48:44 -04:00
Kevin Lim
b2a479cfc8 Merge ktlim@zizzer:/bk/newmem
into  zamp.eecs.umich.edu:/z/ktlim2/clean/newmem-merge

--HG--
extra : convert_revision : e8933f852352164f4e50444f94cc6ee260e06766
2006-07-07 16:47:28 -04:00
Kevin Lim
1faada9bd9 Take the name of the checkpoint directory in when calling checkpoint() or restoreCheckpoint().
src/sim/main.cc:
src/sim/serialize.cc:
src/sim/serialize.hh:
    Take in the directory name when checkpointing.

--HG--
extra : convert_revision : 040e828622480f1051e2156f4439e24864c38d45
2006-07-07 16:46:08 -04:00
Korey Sewell
e5aff1a7f3 Merge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/newmem
into  zizzer.eecs.umich.edu:/.automount/zooks/y/ksewell/research/m5-sim/newmem-o3

--HG--
extra : convert_revision : be8b295ebf54a7c6bf720a20ab6aa9f02aee8060
2006-07-07 16:19:13 -04:00
Ron Dreslinski
7811500eef Fix address range calculation. Still need bus to handle snoop ranges.
On the way towards multi-level caches (L2)

src/mem/cache/base_cache.cc:
src/mem/cache/base_cache.hh:
    Fix address range calculation.  Still need bus to handle snoop ranges.

--HG--
extra : convert_revision : 800078d88aab5e563f4a9bb599f91cd44f36e625
2006-07-07 16:02:22 -04:00
Korey Sewell
743737c28b Merge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/newmem
into  zizzer.eecs.umich.edu:/.automount/zooks/y/ksewell/research/m5-sim/newmem-o3

--HG--
extra : convert_revision : f97469b7d19c82deb3d068f80546d729757c25e3
2006-07-07 15:58:22 -04:00
Korey Sewell
74d4d67138 Minor fix for SMT Hello Worlds to finish correctly.
Still, there is a problem with the LSQ and indexing out of range in the buffer.
I havent nailed down the fix yet, but it's coming ...

src/cpu/o3/commit_impl.hh:
    add space to DPRINT
src/cpu/o3/cpu.cc:
    add newline to DPRINT
src/cpu/o3/rob.hh:
src/cpu/o3/rob_impl.hh:
    Each thread needs it's own squashedSeqNum for the case where they are both squashing at the same time and they dont
    write over each other's squash number.

--HG--
extra : convert_revision : 2155421a8b5b20e4544eea3d3c53d3e715465fa6
2006-07-07 15:58:03 -04:00
Kevin Lim
018ba50f2c Switch out fixes for CPUs.
src/cpu/o3/cpu.cc:
    Fix up keeping proper state when switched out and drained.
src/cpu/simple/timing.cc:
src/cpu/simple/timing.hh:
    Keep track of the event we use to schedule fetch initially and upon resume.  We may have to cancel the event if the CPU is switched out.

--HG--
extra : convert_revision : 60a2a1bd2cdc67bd53ca4a67aa77166c826a4c8c
2006-07-07 15:38:15 -04:00
Ron Dreslinski
76c110d924 Remove hack now that ports work properly
--HG--
extra : convert_revision : 43c22294867d7cbbc67ae66ec41a1d1c89f5a59d
2006-07-07 15:16:41 -04:00
Ron Dreslinski
ea11c7bdbe Update cpus to use the getPort function to use a connector object to connect the I/D cache ports to memory
configs/test/test.py:
    Update to use new cpu getPort functionality
src/cpu/base.cc:
    Make cpu's a memObject to expose getPort interface
src/cpu/base.hh:
    Make cpu's a memObject to export getPort interface
src/cpu/simple/atomic.cc:
src/cpu/simple/atomic.hh:
src/cpu/simple/timing.cc:
src/cpu/simple/timing.hh:
    Now use the connector via getPort interface
src/mem/cache/base_cache.cc:
    Make sure the cache recognizes all port names

--HG--
extra : convert_revision : dbfefa978ec755bc8aa6f962ae158acf32dafe61
2006-07-07 15:15:11 -04:00
Korey Sewell
161e8bf874 Merge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/newmem
into  zizzer.eecs.umich.edu:/.automount/zooks/y/ksewell/research/m5-sim/newmem-o3

--HG--
extra : convert_revision : 90717b492139428e0c48be35a6bda45960c61086
2006-07-07 04:07:00 -04:00
Korey Sewell
c355df5bfe Fix so that O3CPU doesnt segfault on exit.
Major thing was to not execute commit if there are no active threads in CPU.

src/cpu/o3/alpha/thread_context.hh:
    call deallocate instead of deallocateContext
src/cpu/o3/commit_impl.hh:
    dont run commit stage if there are no instructions
src/cpu/o3/cpu.cc:
    add deallocate event, deactivateThread function, and edit deallocateContext.
src/cpu/o3/cpu.hh:
    add deallocate event and add optional delay to deallocateContext
src/cpu/o3/thread_context.hh:
    optional delay for deallocate
src/cpu/o3/thread_context_impl.hh:
    edit DPRINTFs to say Thread Context instead of Alpha TC
src/cpu/thread_context.hh:
    optional delay
src/sim/syscall_emul.hh:
    name stuff

--HG--
extra : convert_revision : f4033e1f66b3043d30ad98dcc70d8b193dea70b6
2006-07-07 04:06:26 -04:00
Kevin Lim
55e59e26c1 Merge ktlim@zizzer:/bk/newmem
into  zamp.eecs.umich.edu:/z/ktlim2/clean/newmem-merge

--HG--
extra : convert_revision : 942c43e2fdd68cde7aaaba5e88a667f80feab162
2006-07-06 23:20:44 -04:00
Kevin Lim
6872b99c29 Be sure to call resume after restoring from a checkpoint.
--HG--
extra : convert_revision : 4d672917038779a23f4ce7eb5d4e3039c1f5d726
2006-07-06 23:16:22 -04:00
Kevin Lim
fff7531677 Support serializing and unserializing in the O3 CPU. Also a few small fixes for draining/switching CPUs.
src/cpu/o3/commit_impl.hh:
    Fix to clear drainPending variable on call to resume.
src/cpu/o3/cpu.cc:
src/cpu/o3/cpu.hh:
    Support serializing and unserializing in the O3 CPU.
src/cpu/o3/lsq_impl.hh:
    Be sure to say we have no stores to write back if the active thread list is empty.
src/cpu/simple_thread.cc:
src/cpu/simple_thread.hh:
    Slightly change how SimpleThread is used to copy from other ThreadContexts.

--HG--
extra : convert_revision : 92a5109b3783a989d5b451036061ef82c56d3121
2006-07-06 23:13:38 -04:00
Kevin Lim
fbe3e22474 Fix the O3CPU to support the multi-pass method for checking if the system has fully drained.
src/cpu/o3/commit.hh:
src/cpu/o3/commit_impl.hh:
src/cpu/o3/decode.hh:
src/cpu/o3/decode_impl.hh:
src/cpu/o3/fetch.hh:
src/cpu/o3/fetch_impl.hh:
src/cpu/o3/iew.hh:
src/cpu/o3/iew_impl.hh:
src/cpu/o3/rename.hh:
src/cpu/o3/rename_impl.hh:
    Return a value so that the CPU can instantly return from draining if the pipeline is already drained.
src/cpu/o3/cpu.cc:
    Use values returned from pipeline stages so that the CPU can instantly return from draining if the pipeline is already drained.

--HG--
extra : convert_revision : d8ef6b811644ea67c8b40c4719273fa224105811
2006-07-06 17:57:20 -04:00
Kevin Lim
e7ccc94ea3 Various serialization changes to make it possible for the O3CPU to checkpoint.
src/arch/alpha/regfile.hh:
    Define serialize/unserialize functions on MiscRegFile itself.
src/cpu/o3/regfile.hh:
    Remove old commented code.
src/cpu/simple_thread.cc:
src/cpu/simple_thread.hh:
    Push common serialization code to ThreadState level.  Also allow the SimpleThread to be used for checkpointing by other models.
src/cpu/thread_state.cc:
src/cpu/thread_state.hh:
    Move common serialization code into ThreadState.

--HG--
extra : convert_revision : ef64ef515355437439af967eda2e610e8c1b658b
2006-07-06 17:53:26 -04:00
Ron Dreslinski
1ccfdb442f Timing cache works for hello world test.
Still need
1) detailed CPU (blocking ability in cache)
1a) Multiple outstanding requests (need to keep track of times for events)
2)Multi-level support
3)MP coherece support
4)LL/SC support
5)Functional path needs to be correctly implemented (temporarily works without multiple outstanding requests (simple cpu))

src/cpu/simple/timing.cc:
    Temp hack because timing cpu doesn't export ports properly so single I/D cache communicates only through the Icache port.
src/mem/cache/base_cache.cc:
    Handle marking MSHR's in service
    Add support for getting CSHR's
src/mem/cache/base_cache.hh:
    Make these functions visible at the base cache level
src/mem/cache/cache.hh:
    make the functions virtual
src/mem/cache/cache_impl.hh:
    Rename the function to make sense
src/mem/packet.hh:
    Accidentally clearing the needsResponse field when sending a response back.

--HG--
extra : convert_revision : 2325d4e0b77e470fa9da91490317dc8ed88b17e2
2006-07-06 16:52:05 -04:00
Kevin Lim
8bf9709d91 Two minor FS compile fixes.
src/dev/tsunami_pchip.hh:
    Need ULL() for 32-bit hosts.
src/sim/pseudo_inst.cc:
    Forgot to remove sampler include from here.

--HG--
extra : convert_revision : 6ab6bdc721290167b4c2b78da3d28a4992eb24d5
2006-07-06 16:26:44 -04:00
Kevin Lim
8ae4f45bc4 Fixes for draining.
src/cpu/simple/timing.cc:
    Update for changed return values.
src/python/m5/__init__.py:
    Loop in order to make sure all objects are really drained.  Objects may become undrained as other objects become drained (e.g. a bus-bridge has a packet, while a bus is empty, and the first drain() will cause the bus-bridge to give the packet to the bus).

    The only case we know every object is actually drained is if they all return immediately that they are drained.

--HG--
extra : convert_revision : 80057a1d6d30381bd0b67b23549bd202f447c5cb
2006-07-06 16:06:00 -04:00
Ron Dreslinski
a1d208a65d Merge zizzer:/z/m5/Bitkeeper/newmem
into  zizzer.eecs.umich.edu:/.automount/zazzer/z/rdreslin/m5bk/newmem

--HG--
extra : convert_revision : 507eefde3514c35ca8420408cc89590d83cc6fc6
2006-07-06 15:16:15 -04:00
Ron Dreslinski
329e32f8c6 Now timing reads work in single level of cache with simple cpu
src/mem/cache/base_cache.cc:
src/mem/cache/base_cache.hh:
src/mem/cache/cache.hh:
    Changes to handle timing reads in Simple CPU (blocking buffers)

--HG--
extra : convert_revision : a2e7d4287d7cdfd1bbf9c929ecbeafde499a5b9f
2006-07-06 15:15:37 -04:00
Kevin Lim
c8a37ce715 Merge ktlim@zizzer:/bk/newmem
into  zamp.eecs.umich.edu:/z/ktlim2/clean/newmem-merge

--HG--
extra : convert_revision : 0c4fbbe0826358a6a58f844bec34ce830ffd4ced
2006-07-06 14:54:09 -04:00
Ali Saidi
4b74110071 Merge zizzer:/bk/newmem
into  zeep.pool:/z/saidi/work/m5.newmem

--HG--
extra : convert_revision : 4669e87d29fa3e0ca9009f6b9dce72113220d7bc
2006-07-06 14:41:09 -04:00
Ali Saidi
93839380e7 Add default responder to bus
Update configuration for new default responder on bus
Update to devices to handle their own pci config space without pciconfigall
Remove most of pciconfigall, it now is a dumbdevice which gets it's address based on the bus it's supposed to respond for
Remove need for pci config space from platform, add registerPciDevice function to prevent more than one device from having same
bus:dev:func and interrupt
Remove pciconfigspace from pci devices, and py files
Add calcConfigAddr that returns address for config space based on bus/dev/function + offset

configs/test/fs.py:
    Update configuration for new default responder on bus
src/dev/ide_ctrl.cc:
src/dev/ide_ctrl.hh:
src/dev/ns_gige.cc:
src/dev/ns_gige.hh:
src/dev/pcidev.cc:
src/dev/pcidev.hh:
    Update to handle it's own pci config space without pciconfigall
src/dev/io_device.cc:
src/dev/io_device.hh:
    change naming for pio port
    break out recvTiming into two functions to reuse code
src/dev/pciconfigall.cc:
src/dev/pciconfigall.hh:
    removing most of pciconfigall, it now is a dumbdevice which gets it's address based on the bus it's supposed to respond for
src/dev/pcireg.h:
    add a max size for PCI config space (per PCI spec)
src/dev/platform.cc:
src/dev/platform.hh:
    remove need for pci config space from platform, add registerPciDevice function to prevent more than one device from having same
    bus:dev:func and interrupt
src/dev/sinic.cc:
    remove pciconfigspace as it's no longer a needed parameter
src/dev/tsunami.cc:
src/dev/tsunami.hh:
src/dev/tsunami_pchip.cc:
src/dev/tsunami_pchip.hh:
    add calcConfigAddr that returns address for config space based on bus/dev/function + offset (per PCI spec)
src/mem/bus.cc:
src/mem/bus.hh:
src/python/m5/objects/Bus.py:
    add idea of default responder to bus
src/python/m5/objects/Pci.py:
    add config port for pci devices
    add latency, bus and size parameters for pci config all (min is 8MB, max is 256MB see pci spec)

--HG--
extra : convert_revision : 99db43b0a3a077f86611d6eaff6664a3885da7c9
2006-07-06 14:41:01 -04:00
Kevin Lim
05eef5ee15 Merge ktlim@zizzer:/bk/newmem
into  zamp.eecs.umich.edu:/z/ktlim2/clean/newmem-merge

--HG--
extra : convert_revision : 00f8eecf99c771ae8943ed1d3a652bfbcfe1c6bc
2006-07-06 13:59:13 -04:00
Kevin Lim
30c516d51c Support for draining, and the new method of switching out. Now switching out happens after the pipeline has been drained, deferring the three way handshake to the normal drain mechanism. The calls of switchOut() and takeOverFrom() both take action immediately.
src/cpu/o3/commit.hh:
src/cpu/o3/commit_impl.hh:
src/cpu/o3/cpu.cc:
src/cpu/o3/cpu.hh:
src/cpu/o3/decode.hh:
src/cpu/o3/decode_impl.hh:
src/cpu/o3/fetch.hh:
src/cpu/o3/fetch_impl.hh:
src/cpu/o3/iew.hh:
src/cpu/o3/iew_impl.hh:
src/cpu/o3/rename.hh:
src/cpu/o3/rename_impl.hh:
    Support for draining, new method of switching out.

--HG--
extra : convert_revision : 05bf8b271ec85b3e2c675c3bed6c42aeba21f465
2006-07-06 13:59:02 -04:00
Kevin Lim
8c547d80b1 Change the return value of drain. False means the object wasn't able to drain yet.
src/python/m5/config.py:
    Invert the return value.
src/sim/sim_object.cc:
    Invert the return value of drain.
src/sim/sim_object.hh:
    Change the return value of drain.

--HG--
extra : convert_revision : 41bb122c6f29302d8b3815d7bd6a2ea8fba64df9
2006-07-06 13:57:21 -04:00
Korey Sewell
e60f998e29 Had to add this because for some reason gcc wasnt recognizing "THE_ISA == ALPHA_ISA"... wierd but OK
--HG--
extra : convert_revision : f847d6c01212e32200a319c16596b8e1c1d15c7d
2006-07-06 12:29:34 -04:00
Korey Sewell
a35898c18d Merge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/newmem
into  zizzer.eecs.umich.edu:/.automount/zooks/y/ksewell/research/m5-sim/newmem-o3

--HG--
extra : convert_revision : 2f08ea52ef54118d42aa590c0d86aa0cc7988713
2006-07-06 12:19:29 -04:00
Korey Sewell
03fa13b27c Use O3DynInst in cpu_models.py and in static_inst_exec_sigs.hh instead of a specific ISA dyn. inst.
src/cpu/cpu_models.py:
    Use O3DynInst
src/cpu/o3/dyn_inst.hh:
    declare O3DynInst here based off of ISA ... this must be updated for each ISA.
src/cpu/static_inst.hh:
    take out O3 forward declarations here and include header file to keep this file clean

--HG--
extra : convert_revision : 0d65463479c3cfc2d1154935b1032dae32c5efd0
2006-07-06 12:18:55 -04:00
Korey Sewell
215041215b more steps toward O3 SMT
src/arch/mips/isa/formats/fp.isa:
    Adjust for newmem
src/cpu/cpu_models.py:
    Use O3DynInst instead of convoluted way
src/cpu/o3/alpha/impl.hh:
    take out O3DynInst typedef here ...
src/cpu/o3/cpu.cc:
    open up the SMT functions in the O3CPU
src/cpu/static_inst.hh:
    Add O3DynInst
src/cpu/o3/dyn_inst.hh:
    Use to get ISA-specific O3DynInst

--HG--
extra : convert_revision : 3713187ead93e336e80889e23a1f1d2f36d664fe
2006-07-06 11:25:44 -04:00
Kevin Lim
eceba1405a For now using the checkpoint or switchcpu pseudo instructions will return control to Python, returning the cause to be the instruction name. The user's script must then interpret the reason for exiting the simulation loop and handle the action accordingly. This may change in the future.
src/sim/pseudo_inst.cc:
    Exit sim loop with a specific string to indicate to Python what caused the exit.  The user's script needs to interpret the exit events and handle them as desired.

--HG--
extra : convert_revision : 8eb4a42285dacb3ada3a791173c605b5acb78598
2006-07-05 23:38:11 -04:00
Kevin Lim
d598061dd6 Remove sampler and serializer. Now they are handled through C++ interacting with Python.
src/SConscript:
src/cpu/base.cc:
src/cpu/base.hh:
src/cpu/checker/cpu.hh:
src/cpu/checker/cpu_impl.hh:
src/cpu/o3/cpu.cc:
src/cpu/o3/cpu.hh:
src/cpu/o3/fetch.hh:
src/cpu/ozone/cpu.hh:
src/cpu/ozone/cpu_impl.hh:
src/cpu/simple/base.cc:
src/cpu/simple/base.hh:
src/sim/pseudo_inst.cc:
    Remove sampler.
src/sim/sim_object.cc:
    Remove serializer.

--HG--
extra : convert_revision : ce7616189440f3dc70040148da6d07309a386008
2006-07-05 21:14:36 -04:00
Kevin Lim
d8fd09cc15 Rename quiesce to drain to avoid confusion with the pseudo instruction.
src/cpu/simple/timing.cc:
src/cpu/simple/timing.hh:
src/python/m5/__init__.py:
src/python/m5/config.py:
src/sim/main.cc:
src/sim/sim_events.cc:
src/sim/sim_events.hh:
src/sim/sim_object.cc:
src/sim/sim_object.hh:
    Rename quiesce to drain.

--HG--
extra : convert_revision : fc3244a3934812e1edb8050f1f51f30382baf774
2006-07-05 17:59:33 -04:00
Kevin Lim
bd26dbdb13 Checker ignores any faults that occur in syscall emulation mode for now.
src/cpu/checker/cpu_impl.hh:
    The only fault we handle in SE causes troubles when invoked with the Checker.  This is because it changes state within the process, and not the checker, so the state isn't correct when the main CPU calls invoke.  It's safe to just ignore the fault in the Checker and continue.

--HG--
extra : convert_revision : 5000d763a75009c7a6011646a6790ac5b23df6bb
2006-07-05 17:25:37 -04:00
Kevin Lim
ea9697250c Fix up some merge problems.
src/base/traceflags.py:
    Remove BaseCPU traceflag.
src/cpu/o3/alpha/params.hh:
    Move non-Alpha specific parameters out of this params class.
src/cpu/o3/params.hh:
    Move non-Alpha specific params into this params class.

--HG--
extra : convert_revision : e5b652adb47a240376733400e6054c66c50bd514
2006-07-05 16:54:24 -04:00