Commit graph

9593 commits

Author SHA1 Message Date
Andreas Hansson
2ca42cd626 cpu: Avoid including inorder TLBUnit to avoid gcc LTO bug
This patch comments out the inclusion of the inorder TLBUnit which is
only used in the 9-stage pipeline. With the TLBUnit present, gcc >=
4.6 in combination with LTO ends up throwing away the definition of
the TLBUnit destructor, and consequently fail to link. See
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=53808 for more details
about the bug, and http://gcc.gnu.org/ml/gcc/2012-06/msg00397.html for
the discussion thread that also touches on similar issues seen with
clang.
2013-03-20 06:41:23 -04:00
Andreas Sandberg
e28e6246fc scons: Try to use 'tcmalloc' before 'tcmalloc_minimal'
tcmalloc_minimal doesn't support the heap checker on Debian, while
tcmalloc does. Instead of always linking with tcmalloc_minimal, if it
exists, we first check for tcmalloc and then use tcmalloc_minimal as a
fallback.
2013-03-18 11:24:56 +01:00
Andreas Sandberg
468ad10f50 scons: Avoid malloc/free compiler optimization when using tcmalloc
According to the tcmalloc readme, the recommended way of compiling
applications that make use of tcmalloc is to disable compiler
optimizations that make assumptions about malloc and friends. This
changeset adds the necessary compiler flags for both gcc and clang.

From the tcmalloc readme:
"NOTE: When compiling with programs with gcc, that you plan to link
with libtcmalloc, it's safest to pass in the flags

 -fno-builtin-malloc -fno-builtin-calloc
 -fno-builtin-realloc -fno-builtin-free

when compiling."
2013-03-18 10:57:26 +01:00
Andreas Sandberg
9e9a47cb9a scons: Don't explicitly add tcmalloc_minimal to LIBS
SCons automatically adds a library to LIBS if conf.CheckLib succeeds,
so there is no need to explicitly add the library.
2013-03-18 10:44:34 +01:00
Andreas Sandberg
3e3475138b scons: Include flags required to link statically with Python
Python requires the flags in LINKFORSHARED to be added the linker
flags when linking with a statically with Python. Failing to do so can
lead to errors from the Python's dynamic module loader at start up.

--HG--
extra : rebase_source : e7a8daf72f4ede7ee5a4a5398a0b12e978a919b9
2013-03-18 10:22:21 +01:00
Andreas Hansson
c01c5e971b mem: Fix missing delete of packet in DRAM access
This patch fixes a memory leak caused by not deleting packets that
require no response.
2013-03-18 05:22:45 -04:00
Nilay Vaish
dc37b03439 ruby: set: corrects csprintf() call introduced by 7d95b650c9b6 2013-03-15 16:28:08 -05:00
Andreas Sandberg
9544e8fbe0 scons: Check for known buggy version of SWIG (2.0.9)
SWIG version 2.0.9 uses fully qualified module names despite of the
importing module being in the same package as the imported
module. This has the unfortunate consequence of causing the following
error when importing m5.internal.event:

Traceback (most recent call last):
  File "<string>", line 1, in <module>
  File "src/python/importer.py", line 75, in load_module
    exec code in mod.__dict__
  File "src/python/m5/__init__.py", line 35, in <module>
    import internal
  File "src/python/importer.py", line 75, in load_module
    exec code in mod.__dict__
  File "src/python/m5/internal/__init__.py", line 32, in <module>
    import event
  File "src/python/importer.py", line 75, in load_module
    exec code in mod.__dict__
  File "build/X86/python/swig/event.py", line 107, in <module>
    class Event(m5.internal.serialize.Serializable):
AttributeError: 'module' object has no attribute 'internal'

When 'event' is loaded, it triggers 'serialize' to be loaded. However,
it seems like the dictionary of 'm5' isn't updated until after
__init__.py terminates, which means that 'event' never sees the
'internal' attribute on 'm5'. Older versions of SWIG didn't include
the fully qualified module name if the modules were in the same
package.
2013-03-14 16:08:55 +01:00
Andreas Sandberg
fc6f569d94 cpu: Fix state transition bug in the traffic generator
The traffic generator used to incorrectly determine the next state in
when state 0 had a non-zero probability. Due to the way the next
transition was determined, state 0 could never be entered other than
as an initial state. This changeset updates the transitition() method
to correctly handle such cases and cases where the transition matrix
is a 1x1 matrix.
2013-03-12 18:41:29 +01:00
Nilay Vaish
53a0597805 regressions: x86: stats updates due to new x87 insts 2013-03-11 17:45:09 -05:00
Nilay Vaish
5c940fec0a x86: implement some of the x87 instructions
This patch implements ftan, fprem, fyl2x, fld* floating-point instructions.
2013-03-11 13:15:46 -05:00
Andreas Hansson
82f600e02d base: Fix address range granularity calculations
This patch fixes a bug in the address range granularity
calculations. Previously it incorrectly used the high bit to establish
the size of the regions created, when it should really be looking at
the low bit.
2013-03-07 05:55:03 -05:00
Andreas Hansson
92e973b310 ruby: Fix gcc 4.8 maybe-uninitialized compilation error
This patch fixes the one-and-only gcc 4.8 compilation error, being a
warning about "maybe uninitialized" in Orion.
2013-03-07 05:55:02 -05:00
Andreas Hansson
c4645c0d68 x86: Make the table walker reset the packet delay
This patch fixes an issue related to the table walker recycling
packets that still have a bus delay that is not accounted for. For
now, we simply ignore the values and reset them to zero.
2013-03-07 05:55:01 -05:00
Nilay Vaish
d24d5446c5 regressions: stats updates due to no physmem in ruby 2013-03-06 21:57:10 -06:00
Nilay Vaish
c061819890 ruby: remove the functional copy of memory in se mode
This patch removes the functional copy of the memory that was maintained in
the se mode. Now ruby itself will provide the data.
2013-03-06 21:53:57 -06:00
Nilay Vaish
e8802fa127 ruby: garnet: fixed: implement functional access 2013-03-06 21:53:16 -06:00
Ali Saidi
09b2430e95 stats: update patches for branch predictor and fetch updates. 2013-03-04 23:33:47 -05:00
Ali Saidi
f205d83359 cpu: fix a switching issue with the o3 cpu.
This change fixes the switcheroo test that broke earlier this month. The code
that was checking for the pipeline being blocked wasn't checking for a pending
translation, only for a icache access.
2013-03-04 23:33:47 -05:00
Ali Saidi
f4fd12d49e ARM: fix some cases where instructions that write to fp reg 15 are accidently branches. 2013-03-04 23:33:47 -05:00
Blake Hechtman ext:(%2C%20Nilay%20Vaish%20%3Cnilay%40cs.wisc.edu%3E)
af8eb67fb4 ruby: fixes functional writes to RubyRequest
The functional write code was assuming that all writes are block sized,
which may not be true for Ruby Requests. This bug can lead to a buffer
overflow.

Committed by: Nilay Vaish <nilay@cs.wisc.edu>
2013-03-02 23:12:55 -06:00
Nilay Vaish
a4e8512afa sim: remove duplicate check on stack size 2013-03-02 18:04:51 -06:00
Andreas Hansson
e5bcb30756 mem: Add check if SimpleDRAM nextReqEvent is scheduled
This check covers a case where a retry is called from the SimpleDRAM
causing a new request to appear before the DRAM itself schedules a
nextReqEvent. By adding this check, the event is not scheduled twice.
2013-03-01 13:20:33 -05:00
Andreas Hansson
da5356ccce mem: Add a method to build multi-channel DRAM configurations
This patch adds a class method that allows easy creation of
channel-interleaved multi-channel DRAM configurations. It is enabled
by a class method to allow customisation of the class independent of
the channel configuration. For example, the user can create a MyDDR
subclass of e.g. SimpleDDR3, and then create a four-channel
configuration of the subclass by calling MyDDR.makeMultiChannel(4,
mem_start, mem_size).
2013-03-01 13:20:32 -05:00
Andreas Hansson
cb9e208a4c stats: Update stats to reflect SimpleDRAM changes
This patch bumps the stats to reflect the slight change in how the
retry is handled, and also the pruning of some redundant stats.
2013-03-01 13:20:30 -05:00
Andreas Hansson
0facc8e1ac mem: SimpleDRAM variable naming and whitespace fixes
This patch fixes a number of small cosmetic issues in the SimpleDRAM
module. The most important change is to move the accounting of
received packets to after the check is made if the packet should be
retried or not. Thus, packets are only counted if they are actually
accepted.
2013-03-01 13:20:24 -05:00
Andreas Hansson
3ba131f4d5 mem: Add support for multi-channel DRAM configurations
This patch adds support for multi-channel instances of the DRAM
controller model by stripping away the channel bits in the address
decoding. The patch relies on the availiability of address
interleaving and, at this time, it is up to the user to configure the
interleaving appropriately. At the moment it is assumed that the
channel interleaving bits are immediately following the column bits
(smallest sensible interleaving). Convenience methods for building
multi-channel configurations will be added later.
2013-03-01 13:20:22 -05:00
Andreas Hansson
1a58362e25 mem: Merge interleaved ranges when creating backing store
This patch adds merging of interleaved ranges before creating the
backing stores. The backing stores are always a contigous chunk of the
address space, and with this patch it is possible to have interleaved
memories in the system.
2013-03-01 13:20:21 -05:00
Andreas Hansson
cafd38f36c mem: Merge ranges in bus before passing them on
This patch adds basic merging of address ranges to the bus, such that
interleaved ranges are merged together before being passed on by the
bus. As such, the bus aggregates the address ranges of the connected
slave ports and then passes on the merged ranges through its master
ports. The bus thus hides the complexity of the interleaved ranges and
only exposes contigous ranges to the surrounding system.

As part of this patch, the bus ranges are also cached for any future
queries.
2013-03-01 13:20:19 -05:00
Dibakar Gope ext:(%2C%20Nilay%20Vaish%20%3Cnilay%40cs.wisc.edu%3E)
c636a09e83 ruby: mesi coherence protocol: invalidate lock
The MESI CMP directory coherence protocol, while transitioning from SM to IM,
did not invalidate the lock that it might have taken on a cache line. This
patch adds an action for doing so.

The problem was found by Dibakar, but I was not happy with his proposed
solution. So I implemented a different solution.

Committed by: Nilay Vaish <nilay@cs.wisc.edu>
2013-02-28 10:04:26 -06:00
Ali Saidi
82cf1565d0 config: Fix --prog-interval command line option 2013-02-20 08:18:22 -05:00
Nilay Vaish
fea27bc49b slicc: remove unused variable message_buffer_names 2013-02-19 22:58:51 -06:00
Nilay Vaish
e95e78ff2f ruby: remove unused variable m_print_config in class Topology 2013-02-19 22:58:50 -06:00
Andreas Hansson
da950caed2 mem: Fix sender state bug and delay popping
This patch fixes a newly introduced bug where the sender state was
popped before checking that it should be. Amazingly all regressions
pass, but Linux fails to boot on the detailed CPU with caches enabled.
2013-02-19 12:57:47 -05:00
Ali Saidi
a86f67e706 stats: more zizzer stats fun 2013-02-19 09:53:07 -05:00
Andreas Hansson
a62afd094b scons: Fix warnings issued by clang 3.2svn (XCode 4.6)
This patch fixes the warnings that clang3.2svn emit due to the "-Wall"
flag. There is one case of an uninitialised value in the ARM neon ISA
description, and then a whole range of unused private fields that are
pruned.
2013-02-19 05:56:08 -05:00
Andreas Hansson
08a5fd328b scons: Unify the flags shared by gcc and clang
This patch restructures and unifies the flags used by gcc and clang as
they are largely the same. The common parts are now dealt with in a
shared block of code, and the few bits and pieces that are
specifically affecting either gcc or clang are done separately.
2013-02-19 05:56:07 -05:00
Andreas Hansson
5eddb63877 scons: Add warning delete with non-virtual destructor
This patch enables a warning for deleting derived classes that do not
have a virtual destructor. The patch merely adds additional checks,
and there are currently no cases that had to be fixed.
2013-02-19 05:56:07 -05:00
Andreas Hansson
319443d42d scons: Add warning for missing declarations
This patch enables warnings for missing declarations. To avoid issues
with SWIG-generated code, the warning is only applied to non-SWIG
code.
2013-02-19 05:56:07 -05:00
Andreas Hansson
b44e0ce52b scons: Add warning for overloaded virtual functions
Fix the ISA startup warnings
2013-02-19 05:56:07 -05:00
Andreas Hansson
0acd2a96e5 scons: Add warning for overloaded virtual functions
A derived function with a different signature than a base class
function will result in the base class function of the same name being
hidden. The parameter list and return type for the member function in
the derived class must match those of the member function in the base
class, otherwise the function in the derived class will hide the
function in the base class and no polymorphic behaviour will occur.

This patch addresses these warnings by ensuring a unique function name
to avoid (unintentionally) hiding any functions.
2013-02-19 05:56:06 -05:00
Andreas Hansson
d670fa60a1 scons: Add warning for missing field initializers
This patch adds a warning for missing field initializers for both gcc
and clang, and addresses the warnings that were generated.
2013-02-19 05:56:06 -05:00
Andreas Hansson
c10098f28b scons: Fix up numerous warnings about name shadowing
This patch address the most important name shadowing warnings (as
produced when using gcc/clang with -Wshadow). There are many
locations where constructor parameters and function parameters shadow
local variables, but these are left unchanged.
2013-02-19 05:56:06 -05:00
Andreas Hansson
860155a5fc mem: Enforce strict use of busFirst- and busLastWordTime
This patch adds a check to ensure that the delay incurred by
the bus is not simply disregarded, but accounted for by someone. At
this point, all the modules do is to zero it out, and no additional
time is spent. This highlights where the bus timing is simply dropped
instead of being paid for.

As a follow up, the locations identified in this patch should add this
additional time to the packets in one way or another. For now it
simply acts as a sanity check and highlights where the delay is simply
ignored.

Since no time is added, all regressions remain the same.
2013-02-19 05:56:06 -05:00
Andreas Hansson
40d0e6c899 mem: Change accessor function names to match the port interface
This patch changes the names of the cache accessor functions to be in
line with those used by the ports. This is done to avoid confusion and
get closer to a one-to-one correspondence between the interface of the
memory object (the cache in this case) and the port itself.

The member function timingAccess has been split into a snoop/non-snoop
part to avoid branching on the isResponse() of the packet.
2013-02-19 05:56:06 -05:00
Andreas Hansson
b3fc8839c4 mem: Make packet bus-related time accounting relative
This patch changes the bus-related time accounting done in the packet
to be relative. Besides making it easier to align the cache timing to
cache clock cycles, it also makes it possible to create a Last-Level
Cache (LLC) directly to a memory controller without a bus inbetween.

The bus is unique in that it does not ever make the packets wait to
reflect the time spent forwarding them. Instead, the cache is
currently responsible for making the packets wait. Thus, the bus
annotates the packets with the time needed for the first word to
appear, and also the last word. The cache then delays the packets in
its queues before passing them on. It is worth noting that every
object attached to a bus (devices, memories, bridges, etc) should be
doing this if we opt for keeping this way of accounting for the bus
timing.
2013-02-19 05:56:06 -05:00
Andreas Hansson
362160c8ae mem: Add deferred packet class to prefetcher
This patch removes the time field from the packet as it was only used
by the preftecher. Similar to the packet queue, the prefetcher now
wraps the packet in a deferred packet, which also has a tick
representing the absolute time when the packet should be sent.
2013-02-19 05:56:06 -05:00
Andreas Hansson
7cd49b24d2 sim: Make clock private and access using clockPeriod()
This patch makes the clock member private to the ClockedObject and
forces all children to access it using clockPeriod(). This makes it
impossible to inadvertently change the clock, and also makes it easier
to transition to a situation where the clock is derived from e.g. a
clock domain, or through a multiplier.
2013-02-19 05:56:06 -05:00
Andreas Hansson
5c7ebee434 x86: Move APIC clock divider to Python
This patch moves the 16x APIC clock divider to the Python code to
avoid the post-instantiation modifications to the clock. The x86 APIC
was the only object setting the clock after creation time and this
required some custom functionality and configuration. With this patch,
the clock multiplier is moved to the Python code and the objects are
instantiated with the appropriate clock.
2013-02-19 05:56:06 -05:00
Sascha Bischoff
86a4d09269 mem: Fix SenderState related cache deadlock
This patch fixes a potential deadlock in the caches. This deadlock
could occur when more than one cache is used in a system, and
pkt->senderState is modified in between the two caches. This happened
as the caches relied on the senderState remaining unchanged, and used
it for instantaneous upstream communication with other caches.

This issue has been addressed by iterating over the linked list of
senderStates until we are either able to cast to a MSHR* or
senderState is NULL. If the cast is successful, we know that the
packet has previously passed through another cache, and therefore
update the downstreamPending flag accordingly. Otherwise, we do
nothing.
2013-02-19 05:56:06 -05:00