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ARM: fix some cases where instructions that write to fp reg 15 are accidently branches.

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This commit is contained in:
Ali Saidi 2013-03-04 23:33:47 -05:00
parent af8eb67fb4
commit f4fd12d49e
2 changed files with 6 additions and 6 deletions
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8
src/arch/arm/isa/templates/mem.isa
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@ -1122,7 +1122,7 @@ def template LoadRegConstructor {{
#if %(use_uops)d
assert(numMicroops >= 2);
uops = new StaticInstPtr[numMicroops];
if (_dest == INTREG_PC) {
if (_dest == INTREG_PC && !isFloating()) {
IntRegIndex wbIndexReg = index;
uops[0] = new %(acc_name)s(machInst, INTREG_UREG0, _base, _add,
_shiftAmt, _shiftType, _index);
@ -1156,7 +1156,7 @@ def template LoadRegConstructor {{
}
#else
if (_dest == INTREG_PC) {
if (_dest == INTREG_PC && !isFloating()) {
flags[IsControl] = true;
flags[IsIndirectControl] = true;
if (conditional)
@ -1185,7 +1185,7 @@ def template LoadImmConstructor {{
#if %(use_uops)d
assert(numMicroops >= 2);
uops = new StaticInstPtr[numMicroops];
if (_dest == INTREG_PC) {
if (_dest == INTREG_PC && !isFloating()) {
uops[0] = new %(acc_name)s(machInst, INTREG_UREG0, _base, _add,
_imm);
uops[0]->setDelayedCommit();
@ -1208,7 +1208,7 @@ def template LoadImmConstructor {{
uops[1]->setLastMicroop();
}
#else
if (_dest == INTREG_PC) {
if (_dest == INTREG_PC && !isFloating()) {
flags[IsControl] = true;
flags[IsIndirectControl] = true;
if (conditional)

4
src/arch/arm/isa/templates/pred.isa
View file

@ -77,7 +77,7 @@ def template DataImmConstructor {{
}
}
if (%(is_branch)s){
if (%(is_branch)s && !isFloating()){
flags[IsControl] = true;
flags[IsIndirectControl] = true;
if (condCode == COND_AL || condCode == COND_UC)
@ -117,7 +117,7 @@ def template DataRegConstructor {{
}
}
if (%(is_branch)s){
if (%(is_branch)s && !isFloating()){
flags[IsControl] = true;
flags[IsIndirectControl] = true;
if (condCode == COND_AL || condCode == COND_UC)