Commit graph

6896 commits

Author SHA1 Message Date
Brad Beckmann
1907e39fd2 ruby: added ruby stats print
Moved the previous rubymem stats print feature to ruby System so that ruby
stats are printed on simulation exit.
2010-01-29 20:29:21 -08:00
Brad Beckmann
020716cab3 ruby: fixed Set.cc bug to allow zero sized sets
This is necessary for example when no dma sequencers are necessary in the
simulated system.
2010-01-29 20:29:21 -08:00
Brad Beckmann
ce2d13195b ruby: FS support using the new configuration system 2010-01-29 20:29:21 -08:00
Brad Beckmann
dc758641c9 ruby: reorganized ruby python configuration
Reorganized ruby python configuration so that protocol and ruby memory system
configuration code can be shared by multiple front-end configuration files
(i.e. memory tester, full system, and hopefully the regression tester).  This
code works for memory tester, but have not tested fs mode.
2010-01-29 20:29:20 -08:00
Brad Beckmann
e735ca7c77 ruby: Removed out_link_vec from Consumer
Removed the out_line_vec data structure from the Consumer.  I'm not sure
what this did before, but currently it has no usefulness.
2010-01-29 20:29:20 -08:00
Brad Beckmann
0f6535dba1 ruby: Convered ruby tracing support usage of sequencer
Modified ruby's tracing support to no longer rely on the RubySystem map
to convert a sequencer string name to a sequencer pointer.  As a
temporary solution, the code uses the sim_object find function.
Eventually, we should develop a better fix.
2010-01-29 20:29:20 -08:00
Brad Beckmann
2c9ca672df ruby: Memory Controller Profiler with new config system
This patch includes a rather substantial change to the memory controller
profiler in order to work with the new configuration system.  Most
noteably, the mem_cntrl_profiler no longer uses a string map, but instead
a vector.  Eventually this support should be removed from the main
profiler and go into a separate object.  Each memory controller should have
a pointer to that new mem_cntrl profile object.
2010-01-29 20:29:20 -08:00
Brad Beckmann
2a0555470c ruby: Converted MOESI_hammer dma cntrl to new config system 2010-01-29 20:29:19 -08:00
Brad Beckmann
3b290a35ac ruby: Added the cache profiler to the new config system 2010-01-29 20:29:19 -08:00
Brad Beckmann
4e5f4b5074 ruby: Converted the sequencer deadlock event to m5 eventq 2010-01-29 20:29:19 -08:00
Brad Beckmann
e15abd17f9 ruby: Wrapped ruby events into m5 events
Wrapped ruby events using the m5 event object.  Removed the prio_heap
from ruby's event queue and instead schedule ruby events on the m5 event
queue.
2010-01-29 20:29:19 -08:00
Brad Beckmann
63a60cc81e ruby: Removed the tech_nm variable from RubySystem 2010-01-29 20:29:19 -08:00
Brad Beckmann
12daaed84a ruby: Added clock to ruby system
As a first step to migrate ruby to the M5 eventqueue, added a clock
variable to the ruby system.
2010-01-29 20:29:19 -08:00
Brad Beckmann
ed81489954 ruby: Ruby changes required to use the python config system
This patch includes the necessary changes to connect ruby objects using
the python configuration system.  Mainly it consists of removing
unnecessary ruby object pointers and connecting the necessary object
pointers using the generated param objects.  This patch includes the
slicc changes necessary to connect generated ruby objects together using
the python configuraiton system.
2010-01-29 20:29:19 -08:00
Brad Beckmann
42bebab779 ruby: connects sm queues to the network 2010-01-29 20:29:18 -08:00
Steve Reinhardt
a8ea70dac6 ruby: Calculate system total memory capacity in Python
rather than in RubySystem object.
2010-01-29 20:29:18 -08:00
Steve Reinhardt
0b54f1db8e ruby: Add support for generating topologies in Python. 2010-01-29 20:29:17 -08:00
Steve Reinhardt
184cf4db5b scons: ignore blank lines in .slicc files 2010-01-29 20:29:17 -08:00
Steve Reinhardt
c6f1d959be ruby: Make SLICC-generated objects SimObjects.
Also add SLICC support for state-machine parameter defaults
(passed through to Python as SimObject Param defaults).
2010-01-29 20:29:17 -08:00
Steve Reinhardt
98c94cfe3c ruby: Convert most Ruby objects to M5 SimObjects.
The necessary companion conversion of Ruby objects generated by SLICC
are converted to M5 SimObjects in the following patch, so this patch
alone does not compile.
Conversion of Garnet network models is also handled in a separate
patch; that code is temporarily disabled from compiling to allow
testing of interim code.
2010-01-29 20:29:17 -08:00
Steve Reinhardt
b43994ba45 ruby: get rid of obsolete, unused CustomTopology class. 2010-01-29 20:29:14 -08:00
Steve Reinhardt
2f567f69cf tests: added M5_TEST_PROGS environment variable
to allow override of global location for regression test binaries.
2010-01-29 20:29:14 -08:00
Brad Beckmann
7f03dce012 ruby: fix out_port declaration 2010-01-29 20:29:14 -08:00
Brad Beckmann
43e4f59e4f ruby: Added message type check to OutPortDeclAST.py
Though OutPort's message type is not used to generate code, this fix checks
that the programmer's intent is correct.  Eventually, we may want to
remove the message type from the OutPort declaration statement.
2010-01-29 20:29:13 -08:00
Derek Hower
cf08b232ff Automated merge with ssh://hg@m5sim.org/m5 2010-01-25 11:53:06 -06:00
Derek Hower
5a4ebd6d12 config: changed default ruby config file for regression 2010-01-25 11:51:16 -06:00
Nathan Binkert
5b90934dd2 build: need to include cstdio 2010-01-23 14:02:03 -08:00
Nathan Binkert
6bb9486598 style_hook: Fix the style hook
Re-enable it and update it for more modern versions of mercurial.
2010-01-23 09:43:18 -08:00
Derek Hower
589218168c Automated merge with ssh://hg@m5sim.org/m5 2010-01-22 17:23:21 -06:00
Lisa Hsu
1c448e2ab0 copyrights: add copyright info to the files I added.
checkpoint-aggregator.py was written at UM so I added a UM copyright, agg_se.py was
written at AMD so I added the AMD copyright.
2010-01-20 16:47:40 -08:00
Lisa Hsu
d6da172517 util: do checkpoint aggregation more cleanly, fix last changeset.
1) Move alpha-specific code out of page_table.cc:serialize().
2) Begin serializing M5_pid and unserializing it, but adding an function to do optional paramIn so that old checkpoints don't need to be fixed up.
3) Fix up alpha startup code so that the unserialized M5_pid value is properly written to DTB_IPR_ASN.
4) Fix the memory unserialize that I forgot somehow in the last changeset.
5) Add in an agg_se.py to handle aggregated checkpoints. --bench foo-bar plus positional arguments foo bar are the only changes in usage from se.py.
Note this aggregation stuff has only been tested for Alpha and nothing else, though it should take a very minimal amount of work to get it to work with another ISA.
2010-01-19 22:03:44 -08:00
Derek Hower
f7de30ab1a memtest differences from Derek's changes 2010-01-19 17:17:19 -06:00
Derek Hower
07ea0891f1 ruby: new atomics implementation
This patch changes the way that Ruby handles atomic RMW instructions. This implementation, unlike the prior one, is protocol independent. It works by locking an address from the sequencer immediately after the read portion of an RMW completes. When that address is locked, the coherence controller will only satisfy requests coming from one port (e.g., the mandatory queue) and will ignore all others. After the write portion completed, the line is unlocked. This should also work with multi-line atomics, as long as the blocks are always acquired in the same order.
2010-01-19 17:11:36 -06:00
Derek Hower
279f179bab merge 2010-01-19 15:48:12 -06:00
Lisa Hsu
0484432a7c Automated merge with ssh://hsul@localhost:4444//repo/m5 2010-01-18 14:33:02 -08:00
Lisa Hsu
4a40ac71f8 util: make a generic checkpoint aggregator that can aggregate different cpts into one multi-programmed cpt. Make minor changes to serialization/unserialization to get it to work properly. Note that checkpoints were made with a comment at the beginning with // - this must be changed to ## to work properly with the python config parser in the aggregator. 2010-01-18 14:30:31 -08:00
Gabe Black
de904a6d39 SCons: Make --help reflect the arguments to scons.
The arguments were added to the global_sticky_vars Variables object after the
basic help text was generated. As a result, the "actual:" value wouldn't
reflect the arguments to scons and wouldn't really be the "actual" value used
by the build. This change fixes that by updating global_sticky_vars slightly
earlier.
2010-01-17 02:22:30 -08:00
Lisa Hsu
8b4e8690b7 cache: make tags->insertBlock() and tags->accessBlock() context aware so that the cache can make context-specific decisions within their various tag policy implementations. 2010-01-12 10:53:02 -08:00
Lisa Hsu
9f63548478 since totalInstructions() is impl'ed by all the cpus, make it an abstract base class. 2010-01-12 10:22:46 -08:00
Lisa Hsu
daebe18e89 faults: i think these fault invocations should be panic and not fatal. it definitely made implementing a trace cpu easier this way. 2010-01-12 10:17:19 -08:00
Gabe Black
4f4e6fc099 MIPS: Update the stats of the RUBY version of the regressions. 2010-01-02 07:06:26 -05:00
Gabe Black
47a1f11381 MIPS: Update stats for updated initial environment. 2009-12-31 15:30:51 -05:00
Matt DeVuyst
18dc80e07b MIPS: Beef up process initialization. 2009-12-31 15:30:51 -05:00
Gabe Black
ecaa7070e6 MIPS: Implement the SE mode version of rdhwr. 2009-12-31 15:30:51 -05:00
Gabe Black
c70f3c93af MIPS: Fix decoding of the rdhwr instruction. 2009-12-31 15:30:51 -05:00
Gabe Black
134937b594 MIPS: Implement the set_thread_area system call. 2009-12-31 15:30:50 -05:00
Gabe Black
d3ed32b989 MIPS: Create an artificial control register to hold the thread pointer.
In Linux, the set_thread_area system call stores the address of the thread
local storage area into a field of the current thread_info structure. Later,
to access that value, the program uses the rdhwr instruction to read a
"hardware register" with index 29. The 64 bit MIPS manual, volume II, says
that index 29 is reserved for a future ABI extension and should cause a
"Reserved Instruction Exception". In Linux (and potentially other ISAs) that
exception is trapped and emulated to return the value stored by
set_thread_area as if that were actually stored by a physical register.

The tp_value address (as named in the Linux kernel) is ironically stored as a
control register so that it goes with a particular ThreadContext. Syscall
emulation will use that to emulate storing to the OS's thread info structure,
and rdhwr will emulate faulting and returning that value from software by
returning the value itself, as if it was in hardware. In other words, we fake
faking the register in SE mode. In an FS mode implementation it should
work as specified in the manual.
2009-12-31 15:30:50 -05:00
Gabe Black
cc07dcf026 MIPS: Extract CPU pointer from the thread context in scheduleCP0 setMiscReg.
The MIPS ISA object expects to be constructed with a CPU pointer it uses to
look at other thread contexts and allow them to be manipulated with control
registers. Unfortunately, that differs from all the other ISA classes and
would complicate their implementation.

This change makes the event constructor use a CPU pointer pulled out of the
thread context passed to setMiscReg instead.
2009-12-31 15:30:50 -05:00
Gabe Black
1261f1d8db MIPS: Add missing syscall slots.
These are all after the existing ones, suggesting they were added after the
original list was created.
2009-12-21 14:59:40 -08:00
Soumyaroop Roy
1bd0f772f1 Alpha: Implement MVI and remaining BWX instructions. 2009-12-20 15:03:23 -06:00